CN104409488B - Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor and its manufacture method - Google Patents
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor and its manufacture method Download PDFInfo
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- CN104409488B CN104409488B CN201410747246.5A CN201410747246A CN104409488B CN 104409488 B CN104409488 B CN 104409488B CN 201410747246 A CN201410747246 A CN 201410747246A CN 104409488 B CN104409488 B CN 104409488B
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- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 63
- 238000005530 etching Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
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- 239000002019 doping agent Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
Gate insulation tunnelling bipolar transistor is folded the present invention relates to a kind of anti-breakdown SOI; contrast is with size MOSFETs or tunneling field-effect transistor, by introducing the breakdown protection area of low impurity concentration in collector junction and emitter junction to be obviously improved forward and reverse anti-breakdown ability of the device under deep nanoscale；There is insulation tunneling structure simultaneously in base both sides and upper surface, insulation tunneling effect is made under the control action of gate electrode while occurring in base both sides and upper surface, therefore improve the generation rate of tunnelling current；Outstanding switching characteristic is realized using the correlation of tunneling insulation layer impedance and its fields inside Qianghian extremely sensitivity；Tunneling through signal enhancing by emitter stage realizes outstanding forward conduction characteristic；The invention also provides a kind of anti-breakdown SOI folds the specific manufacture method of gate insulation tunnelling bipolar transistor unit and its array in addition.The transistor significantly improves the working characteristics of nanometer-grade IC unit, it is adaptable to popularization and application.
Description
Technical field：
Field is manufactured the present invention relates to super large-scale integration, is related to a kind of integrated suitable for high-performance superelevation integrated level
The anti-breakdown SOI of circuit manufacture folds the structure of gate insulation tunnelling bipolar transistor, and it is bipolar that anti-breakdown SOI folds gate insulation tunnelling
The specific manufacture method of transistor array.
Background technology：
Currently, with the continuous lifting of integrated level, integrated circuit unit mos field effect transistor
(MOSFETs) precipitous mutation is formd within several nanometers between the source electrode and raceway groove of device or between drain electrode and raceway groove
PN junction, when drain-source voltage is larger, punch-through effect can occur for this precipitous abrupt PN junction, so that component failure, with device
The continuous reduction of part size, this punch-through effect becomes clear day by day.In addition, the continuous shortening of channel length result in MOSFETs devices
The increase of part subthreshold swing, therefore bring the serious deterioration of switching characteristic and the obvious increase of quiescent dissipation.Although passing through
Improving the mode of gate electrode structure can alleviate the degeneration of this device performance, but when device size is further reduced to 20
When nanometer is following, even with the gate electrode structure of optimization, the subthreshold swing of device similarly can be long with device channel
Degree further reduction and increase, so as to result in the deterioration again of device performance.
Tunneling field-effect transistor (TFETs), in contrast to MOSFETs devices, although its average subthreshold swing has been carried
Rise, but its forward conduction electric current is too small, although it is narrower by introducing the energy gaps such as compound semiconductor, SiGe or germanium
Material can increase tunnelling probability to lift transfer characteristic to be generated as the tunnelling part of tunneling field-effect transistor, but add work
Skill difficulty.In addition, being used as the insulating medium layer between grid and substrate using high dielectric constant insulating material, although can improve
Grid but can not inherently improve the tunnelling probability of silicon materials to the control ability of electric field distribution in channel, therefore for tunnelling
The transfer characteristic of field-effect transistor improves very limited.
The content of the invention：
Goal of the invention
To be obviously improved the energy that sub- 20 nanoscale devices prevent from puncturing on the premise of compatibility is existing based on silicon process technology
Power；It is obviously improved the switching characteristic of nanometer-grade IC basic unit device；Ensure device while lifting switch characteristic
With good forward current on state characteristic, the present invention provides a kind of suitable for high-performance, high integration IC manufacturing
Anti-breakdown SOI folds the structure of gate insulation tunnelling bipolar transistor and its manufacture method of unit and array.
Technical scheme
The present invention is achieved through the following technical solutions：
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, it is characterised in that：Using including monocrystalline substrate 1 and crystalline substance
The SOI wafer for justifying insulating barrier 2 is used as the substrate of generating device；Launch site 3, base 4, collecting zone 5 and breakdown protection area 12 are located at
The top of the wafer insulating barrier 2 of SOI wafer, base 4 and breakdown protection area 12 are located between launch site 3 and collecting zone 5, Ji Chuanbao
Protect the both sides that area 12 is located at base 4；Emitter stage 9 is located at the top of launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；Fold
Conductive layer 6 forms three bread to the upper surface of base 4 and both sides and enclosed；Fold the upper surface of 7 pairs of folding conductive layers 6 of tunneling insulation layer
Three bread are formed with both sides to enclose；The upper surface and both sides three bread of formation for folding 8 pairs of folding tunneling insulation layers 7 of gate electrode are enclosed；Resistance
Gear insulating barrier 11 is dielectric.
To reach device function of the present invention, it is bipolar that the present invention proposes that a kind of anti-breakdown SOI folds gate insulation tunnelling
Transistor, its core texture is characterized as：
The impurity concentration in breakdown protection area 12 is less than 1016It is per cubic centimeter.
The impurity concentration of base 4 is not less than 1017Per cubic centimeter, the both sides of base 4 and upper surface connect with folding conductive layer 6
Touch and form Ohmic contact.
Between launch site 3 and base 4, there is opposite impurity type, and launch site 3 and transmitting between collecting zone 5 and base 4
Ohmic contact is formed between pole 9, Ohmic contact is formed between collecting zone 3 and colelctor electrode 10.
It is that metal material either has identical dopant type with base 4 and doping concentration is more than to fold conductive layer 6
1019Semi-conducting material per cubic centimeter.
It is the insulation material layer for producing tunnelling current to fold tunneling insulation layer 7.
Fold conductive layer 6, fold tunneling insulation layer 7 and fold gate electrode 8 by barrier insulating layer 11 and launch site 3,
Emitter stage 9, collecting zone 5 and colelctor electrode 10 are mutually isolated；Pass through barrier insulating layer 11 between adjacent launch site 3 and collecting zone 5
Isolation, is isolated between adjacent emitter stage 9 and colelctor electrode 10 by barrier insulating layer 11.
Conductive layer 6 is folded, tunneling insulation layer 7 is folded and folds gate electrode 8 and has collectively constituted anti-breakdown SOI foldings gate insulation
The tunnelling base stage of tunnelling bipolar transistor, when folding tunneling insulation layer 7 in generation tunnelling under folding the control of gate electrode 8, electricity
Stream flow to folding conductive layer 6 from folding gate electrode 8 through folding tunneling insulation layer 7, and is powered for base 4.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, by taking N-type as an example, 5 points of launch site 3, base 4 and collecting zone
Not Wei N areas, P areas and N areas, its specific operation principle is：When the positively biased of colelctor electrode 10, and when folding gate electrode 8 in low potential,
Fold and do not form enough electrical potential differences between gate electrode 8 and folding conductive layer 6, now fold tunneling insulation layer 7 and be in high resistant
State, it is similar to MOSFET gate insulator, pass through without obvious tunnelling current, hence in so that between base 4 and launch site 3
Sufficiently large base electric current can not be formed and be in pass to drive anti-breakdown SOI to fold gate insulation tunnelling bipolar transistor, i.e. device
Disconnected state；With gradually rising for the voltage of gate electrode 8 is folded, the electrical potential difference between folding gate electrode 8 and folding conductive layer 6 is gradually
Increase so that positioned at folding gate electrode 8 and fold the electric-field intensity folded in tunneling insulation layer 7 between conductive layer 6 also therewith
Gradually increase, when folding the electric-field intensity in tunneling insulation layer 7 below critical value, fold tunneling insulation layer 7 and protect all the time
Good high-impedance state is held, the electrical potential difference between gate electrode 8 and emitter stage 9 is folded and almost drops completely in folding tunneling insulation layer 7
Inner and outer wall both sides between, the electrical potential difference also allowed between base 4 and launch site 3 is minimum, therefore base does not almost have
Electric current flows through, and therefore device also keeps good off state, and when the electric-field intensity folded in tunneling insulation layer 7 reaches and exceeded
During critical value, the tunnelling of carrier, folding can be occurred by folding tunneling insulation layer 7 by folding between gate electrode 8 and folding conductive layer 6
Folded tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current can be with folding gate electrode 8
The increase of potential is precipitous at a terrific speed to be risen, and this allows for folding tunneling insulation layer 7 in the extremely short potential of folding gate electrode 8
Low resistance state is rapidly converted into by high-impedance state in constant interval；Low resistance state is in when folding tunneling insulation layer 7, tunnelling is now folded exhausted
Edge layer 7 between folding gate electrode 8 and folding conductive layer 6 resistance that is formed will much smaller than fold conductive layer 6 and emitter stage 3 it
Between the resistance that is formed, this electrical potential difference for allowing for folding between gate electrode 8 and emitter stage 9 almost drops to the He of base 4 completely
Between launch site 3, sufficiently large positive bias-voltage is formd, and in the presence of tunneling effect, is folding tunneling insulation layer 7
A large amount of electronics movements are produced between inner and outer wall, as base 4 provides current source, hence in so that between base 4 and launch site 3
Form sufficiently large base electric current and be in unlatching to drive anti-breakdown SOI to fold gate insulation tunnelling bipolar transistor, i.e. device
State.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, prevents the forward and reverse of device from hitting by breakdown protection area 12
Wear.By taking N-type device as an example, when colelctor electrode 10 is relative to 9 positively biased of emitter stage, by folding conductive layer 6, base 4, breakdown protection area
12 and the collector junction that is constituted of collecting zone 5 be in reverse-biased, 12 pairs of the breakdown protection area between base 4 and collecting zone 5
In reverse-biased collector junction there is resistance to wear protective effect, therefore the positive voltage endurance capability of device can be obviously improved；When colelctor electrode 10
When reverse-biased relative to emitter stage 9, at the emitter junction that folding conductive layer 6, base 4, breakdown protection area 12 and launch site 3 are constituted
In reverse-biased, the breakdown protection area 12 between base 4 and launch site 3 has anti-breakdown protection for reverse-biased emitter junction
Effect, therefore the reverse voltage endurance capability of device can be obviously improved；
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, has insulation tunnel simultaneously in the both sides and upper surface of base 4
Structure is worn, insulation tunneling effect is made in the case where folding the control action of gate electrode 8 while occurring in base both sides and upper surface, therefore
Greatly improve the generation rate of tunnelling current.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, using folding the impedance of tunneling insulation layer 7 and tunneling insulation layer
Correlation extremely sensitive between electric field intensity inside high, by choosing appropriate runnel insulator material to folding tunneling insulation layer 7,
And the Sidewall Height, sidewall thickness, top thickness for folding tunneling insulation layer 7 are suitably adjusted, so that it may so as to fold tunnelling
Insulating barrier 7 realizes the conversion between high-impedance state and low resistance state in minimum gate electrode potential constant interval, makes the switch of device
Characteristic is substantially improved.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, and gate insulation tunnelling current flows to base by folding conductive layer 6
Area 4, and signal enhancing is carried out by launch site 3, with general T FETs just with a small amount of semiconductor interband tunnelling current conduct
The conducting electric current of device is compared, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices
Part, anti-breakdown SOI, which folds gate insulation tunnelling bipolar transistor pipe, can realize higher forward conduction electric current.
Advantage and effect
The invention has the advantages that and beneficial effect：
Puncture function 1. putting
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, prevents the forward and reverse of device from hitting by breakdown protection area 12
Wear.By taking N-type device as an example, when colelctor electrode 10 is relative to 9 positively biased of emitter stage, by folding conductive layer 6, base 4, breakdown protection area
12 and the collector junction that is constituted of collecting zone 5 be in reverse-biased, 12 pairs of the breakdown protection area between base 4 and collecting zone 5
In reverse-biased collector junction there is resistance to wear protective effect, therefore the positive voltage endurance capability of device can be obviously improved；When colelctor electrode 10
When reverse-biased relative to emitter stage 9, at the emitter junction that folding conductive layer 6, base 4, breakdown protection area 12 and launch site 3 are constituted
In reverse-biased, the breakdown protection area 12 between base 4 and launch site 3 has anti-breakdown protection for reverse-biased emitter junction
Effect, therefore the reverse voltage endurance capability of device can be obviously improved；
2. high tunnelling current generation rate
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, has insulation tunnel simultaneously in the both sides and upper surface of base 4
Structure is worn, insulation tunneling effect is made in the case where folding the control action of gate electrode 8 while occurring in base both sides and upper surface, therefore
Greatly improve the generation rate of tunnelling current.
2. switching characteristic is obviously improved
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, using folding the impedance of tunneling insulation layer 7 and tunneling insulation layer
Correlation extremely sensitive between electric field intensity inside high, by choosing appropriate runnel insulator material to folding tunneling insulation layer 7,
And the Sidewall Height, sidewall thickness, top thickness for folding tunneling insulation layer 7 are suitably adjusted, so that it may so as to fold tunnelling
Insulating barrier 7 realizes the conversion between high-impedance state and low resistance state in minimum gate electrode potential constant interval, makes the switch of device
Characteristic is substantially improved.
3. the lifting of forward conduction ability
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, and gate insulation tunnelling current flows to base by folding conductive layer 6
Area 4, and signal enhancing is carried out by launch site 3, with general T FETs just with a small amount of semiconductor interband tunnelling current conduct
The conducting electric current of device is compared, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices
Part, anti-breakdown SOI, which folds gate insulation tunnelling bipolar transistor pipe, can realize higher forward conduction electric current.
Brief description of the drawings
Fig. 1 folds the three-dimensional structure that gate insulation tunnelling bipolar transistor is formed on soi substrates for anti-breakdown SOI of the invention
Schematic diagram；
Fig. 2 has peeled off three after barrier insulating layer 11 for anti-breakdown SOI foldings gate insulation tunnelling bipolar transistor of the invention
Tie up structural representation；
Fig. 3 folds gate insulation tunnelling bipolar transistor for anti-breakdown SOI of the invention and has peeled off emitter stage 9, the and of colelctor electrode 10
Three dimensional structure diagram after barrier insulating layer 11；
Fig. 4 folds gate insulation tunnelling bipolar transistor for anti-breakdown SOI of the invention and has peeled off emitter stage 9, colelctor electrode 10, resistance
Keep off insulating barrier 11 and fold the three dimensional structure diagram after gate electrode 8；
Fig. 5 folds gate insulation tunnelling bipolar transistor for anti-breakdown SOI of the invention and has peeled off emitter stage 9, colelctor electrode 10, resistance
Insulating barrier 11 is kept off, gate electrode 8 is folded and folds the three dimensional structure diagram after tunneling insulation layer 7；
Fig. 6 folds gate insulation tunnelling bipolar transistor for anti-breakdown SOI of the invention and has peeled off emitter stage 9, colelctor electrode 10, resistance
Insulating barrier 11 is kept off, gate electrode 8 is folded, fold tunneling insulation layer 7 and folds the three dimensional structure diagram after conductive layer 6；
Fig. 7 anti-breakdown SOI of the invention fold gate insulation tunnelling bipolar transistor and obtained along along Fig. 1 after A plane cuttings
Two-dimensional cross section；
Fig. 8 anti-breakdown SOI of the invention fold gate insulation tunnelling bipolar transistor and obtained along along Fig. 1 after B plane cuttings
Two-dimensional cross section；
Fig. 9 is the schematic top plan view of step one,
Figure 10 is Fig. 9 diagrammatic cross-sections that tangentially A cuttings are obtained,
Figure 11 is the schematic top plan view of step 2,
Figure 12 be Figure 11 tangentially A cuttings the step of obtain two diagrammatic cross-section,
Figure 13 is the schematic top plan view of step 3,
Figure 14 be Figure 13 tangentially A cuttings the step of obtain three diagrammatic cross-section,
Figure 15 is the schematic top plan view of step 4,
Figure 16 be Figure 15 tangentially A cuttings the step of obtain four diagrammatic cross-section,
Figure 17 is the schematic top plan view of step 5,
Figure 18 be Figure 17 tangentially B cuttings the step of obtain five diagrammatic cross-section,
Figure 19 is the schematic top plan view of step 6,
Figure 20 be Figure 19 tangentially B cuttings the step of obtain six diagrammatic cross-section,
Figure 21 is the schematic top plan view of step 7,
Figure 22 be Figure 21 tangentially B cuttings the step of obtain seven diagrammatic cross-section,
Figure 23 is the schematic top plan view of step 8,
Figure 24 be Figure 23 tangentially A cuttings the step of obtain eight diagrammatic cross-section,
Figure 25 be Figure 23 tangentially B cuttings the step of obtain eight diagrammatic cross-section,
Figure 26 is the schematic top plan view of step 9,
Figure 27 be Figure 26 tangentially A cuttings the step of obtain nine diagrammatic cross-section,
Figure 28 be Figure 26 tangentially B cuttings the step of obtain nine diagrammatic cross-section,
Figure 29 is the schematic top plan view of step 10,
Figure 30 be Figure 29 tangentially A cuttings the step of obtain ten diagrammatic cross-section,
Figure 31 be Figure 29 tangentially B cuttings the step of obtain ten diagrammatic cross-section,
Figure 32 is the schematic top plan view of step 11,
Figure 33 be Figure 32 tangentially A cuttings the step of obtain 11 diagrammatic cross-section,
Figure 34 be Figure 32 tangentially B cuttings the step of obtain 11 diagrammatic cross-section,
Figure 35 is the schematic top plan view of step 12,
Figure 36 be Figure 35 tangentially A cuttings the step of obtain 12 diagrammatic cross-section,
Figure 37 be Figure 35 tangentially B cuttings the step of obtain 12 diagrammatic cross-section,
Figure 38 is the schematic top plan view of step 13,
Figure 39 be Figure 38 tangentially A cuttings the step of obtain 13 diagrammatic cross-section,
Figure 40 be Figure 38 tangentially B cuttings the step of obtain 13 diagrammatic cross-section,
Figure 41 is the schematic top plan view of step 14,
Figure 42 be Figure 41 tangentially A cuttings the step of obtain 14 diagrammatic cross-section,
Figure 43 be Figure 41 tangentially B cuttings the step of obtain 14 diagrammatic cross-section,
Figure 44 is the schematic top plan view of step 15,
Figure 45 be Figure 44 tangentially A cuttings the step of obtain 15 diagrammatic cross-section,
Figure 46 be Figure 44 tangentially B cuttings the step of obtain 15 diagrammatic cross-section,
Figure 47 is the schematic top plan view of step 10 six,
Figure 48 be Figure 47 tangentially A cuttings the step of obtain 16 diagrammatic cross-section,
Figure 49 is the schematic top plan view of step 10 seven,
Figure 50 be Figure 49 tangentially A cuttings the step of obtain 17 diagrammatic cross-section.
Description of reference numerals：
1st, monocrystalline substrate；2nd, wafer insulating barrier；3rd, launch site；4th, base；5th, collecting zone；6th, conductive layer is folded；7th, roll over
Folded tunneling insulation layer；8th, gate electrode is folded；9th, emitter stage；10th, colelctor electrode；11st, barrier insulating layer；12nd, breakdown protection area.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：Fig. 1 folds gate insulation tunnelling for anti-breakdown SOI of the invention
The three dimensional structure diagram that bipolar transistor is formed on soi substrates；Fig. 2 folds gate insulation tunnelling for anti-breakdown SOI of the invention
Bipolar transistor has peeled off the three dimensional structure diagram after barrier insulating layer 11；Fig. 3 folds gate insulation for anti-breakdown SOI of the invention
Tunnelling bipolar transistor has peeled off the three dimensional structure diagram after emitter stage 9, colelctor electrode 10 and barrier insulating layer 11；Fig. 4 is
The anti-breakdown SOI of the present invention folds gate insulation tunnelling bipolar transistor and has peeled off emitter stage 9, colelctor electrode 10, the and of barrier insulating layer 11
Fold the three dimensional structure diagram after gate electrode 8；Fig. 5 folds gate insulation tunnelling bipolar transistor for anti-breakdown SOI of the invention
Peel off emitter stage 9, colelctor electrode 10, barrier insulating layer 11, folding gate electrode 8 and fold the three-dimensional knot after tunneling insulation layer 7
Structure schematic diagram；Fig. 6 for anti-breakdown SOI of the invention fold gate insulation tunnelling bipolar transistor peeled off emitter stage 9, colelctor electrode 10,
Three dimensional structure diagram after barrier insulating layer 11, folding gate electrode 8, folding tunneling insulation layer 7 and folding conductive layer 6；Fig. 7
The two-dimensional cross section that gate insulation tunnelling bipolar transistor is obtained along along Fig. 1 after A plane cuttings is folded for anti-breakdown SOI of the invention；
Fig. 8 folds the two dimensional cross-section that gate insulation tunnelling bipolar transistor is obtained along along Fig. 1 after B plane cuttings for anti-breakdown SOI of the invention
Figure；
Specifically include monocrystalline substrate 1；Wafer insulating barrier 2；Launch site 3；Base 4；Collecting zone 5；Fold conductive layer 6；Folding
Folded tunneling insulation layer 7；Fold gate electrode 8；Emitter stage 9；Colelctor electrode 10；Barrier insulating layer 11；Breakdown protection area 12.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, it is characterised in that：Using including monocrystalline substrate 1 and crystalline substance
The SOI wafer for justifying insulating barrier 2 is used as the substrate of generating device；Launch site 3, base 4, collecting zone 5 and breakdown protection area 12 are located at
The top of the wafer insulating barrier 2 of SOI wafer, base 4 and breakdown protection area 12 are located between launch site 3 and collecting zone 5, Ji Chuanbao
Protect the both sides that area 12 is located at base 4；Emitter stage 9 is located at the top of launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；Fold
Conductive layer 6 forms three bread to the upper surface of base 4 and both sides and enclosed；Fold the upper surface of 7 pairs of folding conductive layers 6 of tunneling insulation layer
Three bread are formed with both sides to enclose；The upper surface and both sides three bread of formation for folding 8 pairs of folding tunneling insulation layers 7 of gate electrode are enclosed；Resistance
Gear insulating barrier 11 is dielectric.
To reach device function of the present invention, it is bipolar that the present invention proposes that a kind of anti-breakdown SOI folds gate insulation tunnelling
Transistor, its core texture is characterized as：
The impurity concentration in breakdown protection area 12 is less than 1016It is per cubic centimeter.
The impurity concentration of base 4 is not less than 1017Per cubic centimeter, the both sides of base 4 and upper surface connect with folding conductive layer 6
Touch and form Ohmic contact.
Between launch site 3 and base 4, there is opposite impurity type, and launch site 3 and transmitting between collecting zone 5 and base 4
Ohmic contact is formed between pole 9, Ohmic contact is formed between collecting zone 3 and colelctor electrode 10.
It is that metal material either has identical dopant type with base 4 and doping concentration is more than to fold conductive layer 6
1019Semi-conducting material per cubic centimeter.
It is the insulation material layer for producing tunnelling current to fold tunneling insulation layer 7；
Fold conductive layer 6, fold tunneling insulation layer 7 and fold gate electrode 8 by barrier insulating layer 11 and launch site 3,
Emitter stage 9, collecting zone 5 and colelctor electrode 10 are mutually isolated.
Conductive layer 6 is folded, tunneling insulation layer 7 is folded and folds gate electrode 8 and has collectively constituted anti-breakdown SOI foldings gate insulation
The tunnelling base stage of tunnelling bipolar transistor, when folding tunneling insulation layer 7 in generation tunnelling under folding the control of gate electrode 8, electricity
Stream flow to folding conductive layer 6 from folding gate electrode 8 through folding tunneling insulation layer 7, and is powered for base 4.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, by taking N-type as an example, 5 points of launch site 3, base 4 and collecting zone
Not Wei N areas, P areas and N areas, its specific operation principle is：When the positively biased of colelctor electrode 10, and when folding gate electrode 8 in low potential,
Fold and do not form enough electrical potential differences between gate electrode 8 and folding conductive layer 6, now fold tunneling insulation layer 7 and be in high resistant
State, it is similar to MOSFET gate insulator, pass through without obvious tunnelling current, hence in so that between base 4 and launch site 3
Sufficiently large base electric current can not be formed and be in pass to drive anti-breakdown SOI to fold gate insulation tunnelling bipolar transistor, i.e. device
Disconnected state；With gradually rising for the voltage of gate electrode 8 is folded, the electrical potential difference between folding gate electrode 8 and folding conductive layer 6 is gradually
Increase so that positioned at folding gate electrode 8 and fold the electric-field intensity folded in tunneling insulation layer 7 between conductive layer 6 also therewith
Gradually increase, when folding the electric-field intensity in tunneling insulation layer 7 below critical value, fold tunneling insulation layer 7 and protect all the time
Good high-impedance state is held, the electrical potential difference between gate electrode 8 and emitter stage 9 is folded and almost drops completely in folding tunneling insulation layer 7
Inner and outer wall both sides between, the electrical potential difference also allowed between base 4 and launch site 3 is minimum, therefore base does not almost have
Electric current flows through, and therefore device also keeps good off state, and when the electric-field intensity folded in tunneling insulation layer 7 reaches and exceeded
During critical value, the tunnelling of carrier, folding can be occurred by folding tunneling insulation layer 7 by folding between gate electrode 8 and folding conductive layer 6
Folded tunneling insulation layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current can be with folding gate electrode 8
The increase of potential is precipitous at a terrific speed to be risen, and this allows for folding tunneling insulation layer 7 in the extremely short potential of folding gate electrode 8
Low resistance state is rapidly converted into by high-impedance state in constant interval；Low resistance state is in when folding tunneling insulation layer 7, tunnelling is now folded exhausted
Edge layer 7 between folding gate electrode 8 and folding conductive layer 6 resistance that is formed will much smaller than fold conductive layer 6 and emitter stage 3 it
Between the resistance that is formed, this electrical potential difference for allowing for folding between gate electrode 8 and emitter stage 9 almost drops to the He of base 4 completely
Between launch site 3, sufficiently large positive bias-voltage is formd, and in the presence of tunneling effect, is folding tunneling insulation layer 7
A large amount of electronics movements are produced between inner and outer wall, as base 4 provides current source, hence in so that between base 4 and launch site 3
Form sufficiently large base electric current and be in unlatching to drive anti-breakdown SOI to fold gate insulation tunnelling bipolar transistor, i.e. device
State.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, prevents the forward and reverse of device from hitting by breakdown protection area 12
Wear.By taking N-type device as an example, when colelctor electrode 10 is relative to 9 positively biased of emitter stage, by folding conductive layer 6, base 4, breakdown protection area
12 and the collector junction that is constituted of collecting zone 5 be in reverse-biased, 12 pairs of the breakdown protection area between base 4 and collecting zone 5
In reverse-biased collector junction there is resistance to wear protective effect, therefore the positive voltage endurance capability of device can be obviously improved；When colelctor electrode 10
When reverse-biased relative to emitter stage 9, at the emitter junction that folding conductive layer 6, base 4, breakdown protection area 12 and launch site 3 are constituted
In reverse-biased, the breakdown protection area 12 between base 4 and launch site 3 has anti-breakdown protection for reverse-biased emitter junction
Effect, therefore the reverse voltage endurance capability of device can be obviously improved；
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, has insulation tunnel simultaneously in the both sides and upper surface of base 4
Structure is worn, insulation tunneling effect is made in the case where folding the control action of gate electrode 8 while occurring in base both sides and upper surface, therefore
Greatly improve the generation rate of tunnelling current.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, using folding the impedance of tunneling insulation layer 7 and tunneling insulation layer
Correlation extremely sensitive between electric field intensity inside high, by choosing appropriate runnel insulator material to folding tunneling insulation layer 7,
And the Sidewall Height, sidewall thickness, top thickness for folding tunneling insulation layer 7 are suitably adjusted, so that it may so as to fold tunnelling
Insulating barrier 7 realizes the conversion between high-impedance state and low resistance state in minimum gate electrode potential constant interval, makes the switch of device
Characteristic is substantially improved.
Anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, and gate insulation tunnelling current flows to base by folding conductive layer 6
Area 4, and signal enhancing is carried out by launch site 3, with general T FETs just with a small amount of semiconductor interband tunnelling current conduct
The conducting electric current of device is compared, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices
Part, anti-breakdown SOI, which folds gate insulation tunnelling bipolar transistor pipe, can realize higher forward conduction electric current.
It is specific in SOI wafer that anti-breakdown SOI proposed by the invention folds gate insulation tunnelling bipolar transistor array
Manufacturing technology steps are as follows：
Step 1: there is provided a SOI wafer as shown in Fig. 9 to Figure 10, the lower section of SOI wafer is the monocrystalline silicon of SOI wafer
Substrate 1, the centre of SOI wafer is wafer insulating barrier 2, by ion implanting or diffusion technique, to the monocrystalline silicon above SOI wafer
Film is doped, and preliminarily forms base 4.
Step 2: as shown in Figure 11 to Figure 12, again by ion implanting or diffusion technique, to the list above SOI wafer
Polycrystal silicon film is doped, and the both sides of the base 4 formed in step one form opposite with the dopant type in step one, dense
Degree is not less than 1019Heavily doped region per cubic centimeter, the heavily doped region is used to further form launch site 3 and collecting zone 5, and this is heavy
Undoped region is left between doped region and base, the undoped region is used to form breakdown protection area 12.
Step 3: as shown in Figure 13 to Figure 14, forming rectangular in the SOI wafer provided by photoetching, etching technics
Body shape monocrystalline silicon isolated island queue, makes to be arranged in sequence with launch site 3, breakdown protection area 12, base 4, Ji Chuanbao in each unit
Protect area 12 and collecting zone 5.
Step 4: as shown in Figure 15 to Figure 16, planarization surface is to exposing transmitting after deposit dielectric above wafer
Area 3, base 4, collecting zone 5 and breakdown protection area 12, preliminarily form barrier insulating layer 11.
Step 5: as shown in Figure 17 to Figure 18, further by photoetching, etching technics in the SOI wafer provided shape
Into rectangular-shape monocrystalline silicon isolated island array, each the monocrystalline silicon isolated island queue for being formed step 3 is divided into multiple only each other
Vertical unit.
Step 6: as shown in Figure 19 to Figure 20, dielectric is deposited above wafer, make the portion being etched away in step 5
Divide and be fully filled, and planarize surface to launch site 3, base 4, collecting zone 5 and breakdown protection area 12 is exposed, further formed
Barrier insulating layer 11.
Step 7: as shown in Figure 21 to Figure 22, by etching technics, to the both sides of base 4 of each unit of crystal column surface
Barrier insulating layer 11 is performed etching to exposing wafer insulating barrier 2.
Step 8: as shown in Figure 23 to Figure 25, deposited above wafer metal or with the identical dopant type in base 4
The polysilicon of heavy doping, is completely filled the barrier insulating layer 11 being etched away in step 7, and planarization passes through again behind surface
Etching technics is etched away for generating the part beyond folding conductive layer 6, exposes launch site 3, collecting zone 5, barrier insulating layer 11
With base 4 adjacent to launch site 3, the two ends of collecting zone 5, formed and fold conductive layer 6.
Step 9: as shown in Figure 26 to Figure 28, dielectric is deposited above wafer, then by surface planarisation to exposing folding
The upper surface of folded conductive layer 6, then by etching technics respectively base both sides tunneling insulation layer 7 remote base side pair
Barrier insulating layer 11 is performed etching to exposing wafer insulating barrier 2.
Step 10: as shown in Figure 29 to Figure 31, tunneling insulation layer medium being deposited above wafer, makes to be etched in step 9
The barrier insulating layer 11 fallen is completely filled, planarization surface after again by etching technics etch away for generate fold tunnelling it is exhausted
Edge layer 7, to barrier insulating layer 11 is exposed, is formed with outer portion and folds tunneling insulation layer 7.
Step 11: as shown in Figure 32 to Figure 34, respectively base both sides folding tunneling insulation layer 7 remote base
Side is performed etching to barrier insulating layer 11 to exposing wafer insulating barrier 2.
Step 12: as shown in FIG. 35 to 37, metal or the polysilicon of heavy doping being deposited above wafer, makes step 10
The barrier insulating layer 11 being etched away in one is completely filled；Etched away again by etching technics for generating behind planarization surface
Gate electrode 8 is folded with outer portion to barrier insulating layer 11 is exposed, folding gate electrode 8 is preliminarily formed.
Step 13: as shown in Figure 38 to Figure 40, dielectric is deposited above wafer, then by surface planarisation to exposing
The upper surface of the folding gate electrode 8 formed among step 12.
Step 14: as shown in Figure 41 to Figure 43, metal or the polysilicon of heavy doping are deposited above wafer, and etch away
For forming the part between device cell beyond trace portions, further formed and fold gate electrode 8.
Step 15: as shown in Figure 44 to Figure 46, dielectric is deposited above wafer, by surface planarisation.
Step 16: as shown in Figure 47 to Figure 48, etched away by etching technics positioned at the upper of launch site 3 and collecting zone 5
The barrier insulating layer 11 of side, forms the through hole of emitter stage 9 and colelctor electrode 10.
Step 17: as shown in Figure 49 to Figure 50, metal is deposited above wafer, make the transmitting formed in step 10 six
The through hole of pole 9 and colelctor electrode 10 is completely filled, and passes through etching technics formation emitter stage 9 and colelctor electrode 10.
Claims (7)
1. anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, it is characterised in that：Using including monocrystalline substrate（1）And crystalline substance
Circle insulating barrier（2）SOI wafer as generating device substrate；Launch site（3）, base（4）, collecting zone（5）And breakdown protection
Area（12）Positioned at the wafer insulating barrier of SOI wafer（2）Top, base（4）With breakdown protection area（12）Positioned at launch site（3）With
Collecting zone（5）Between, breakdown protection area（12）Positioned at base（4）Both sides；Emitter stage（9）Positioned at launch site（3）Top；Collection
Electrode（10）Positioned at collecting zone（5）Top；Fold conductive layer（6）To base（4）Upper surface and both sides formed three bread enclose；
Fold tunneling insulation layer（7）To folding conductive layer（6）Upper surface and both sides formed three bread enclose；Fold gate electrode（8）Doubling
Folded tunneling insulation layer（7）Upper surface and both sides formed three bread enclose；Barrier insulating layer（11）For dielectric；Breakdown protection area
（12）Impurity concentration be less than 1016It is per cubic centimeter；Base（4）Impurity concentration be not less than 1017It is per cubic centimeter, base（4）
Both sides and upper surface are with folding conductive layer（6）It is in contact and forms Ohmic contact.
2. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterised in that：Launch site
（3）With base（4）Between, collecting zone（5）With base（4）Between there is opposite impurity type, and launch site（3）With emitter stage
（9）Between form Ohmic contact, collecting zone（3）With colelctor electrode（10）Between form Ohmic contact.
3. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterised in that：Folding is led
Electric layer（6）It is metal material either same base（4）With identical dopant type and doping concentration is more than 1019Every cube li
The semi-conducting material of rice.
4. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterised in that：Fold tunnel
Wear insulating barrier（7）For the insulation material layer for producing tunnelling current.
5. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterised in that：Folding is led
Electric layer（6）, fold tunneling insulation layer（7）With folding gate electrode（8）Pass through barrier insulating layer（11）With launch site（3）, transmitting
Pole（9）, collecting zone（5）And colelctor electrode（10）It is mutually isolated；Adjacent launch site（3）With collecting zone（5）Between it is exhausted by stopping
Edge layer（11）Isolation, adjacent emitter stage（9）With colelctor electrode（10）Between pass through barrier insulating layer（11）Isolation.
6. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterised in that：Folding is led
Electric layer（6）, fold tunneling insulation layer（7）With folding gate electrode（8）Anti-breakdown SOI foldings gate insulation tunnelling is collectively constituted bipolar
The tunnelling base stage of transistor, when folding tunneling insulation layer（7）Folding gate electrode（8）Control under occur tunnelling when, electric current from
Fold gate electrode（8）Through folding tunneling insulation layer（7）It flow to folding conductive layer（6）, and be base（4）Power supply.
7. a kind of anti-breakdown SOI as claimed in claim 1 folds the unit and its array of gate insulation tunnelling bipolar transistor
Manufacture method, it is characterised in that：This method step is as follows：
Step 1: providing a SOI wafer, the lower section of SOI wafer is the monocrystalline substrate of SOI wafer（1）, in SOI wafer
Between be wafer insulating barrier（2）, by ion implanting or diffusion technique, the monocrystalline silicon thin film above SOI wafer is doped, just
Step forms base（4）；
Step 2: again by ion implanting or diffusion technique, being doped to the monocrystalline silicon thin film above SOI wafer, in step
Rapid one base formed（4）Both sides formed, concentration opposite with the dopant type in step one be not less than 1019Every cube li
The heavily doped region of rice, the heavily doped region is used to further form launch site（3）And collecting zone（5）, the heavily doped region and base it
Between leave undoped region, the undoped region be used for form breakdown protection area（12）；
Step 3: forming rectangular-shape monocrystalline silicon isolated island queue in the SOI wafer provided by photoetching, etching technics, make
Launch site is arranged in sequence with each unit（3）, breakdown protection area（12）, base（4）, breakdown protection area（12）And collecting zone
（5）；
Step 4: above the wafer after deposit dielectric planarization surface to exposing launch site（3）, base（4）, collecting zone
（5）With breakdown protection area（12）, preliminarily form barrier insulating layer（11）；
Step 5: rectangular-shape monocrystalline silicon isolated island battle array is further formed in the SOI wafer provided by photoetching, etching technics
Row, make each monocrystalline silicon isolated island queue that step 3 is formed be divided into multiple units independent of each other；
Step 6: depositing dielectric above wafer, the part being etched away in step 5 is set fully to be filled, and planarize
Surface is to exposing launch site（3）, base（4）, collecting zone（5）With breakdown protection area（12）, further form barrier insulating layer
（11）；
Step 7: by etching technics, to the base of each unit of crystal column surface（4）The barrier insulating layer of both sides（11）Carved
Erosion is to exposing wafer insulating barrier（2）；
Step 8: depositing metal above wafer or having and base（4）The polysilicon of the heavy doping of identical dopant type, makes step
The barrier insulating layer being etched away in rapid seven（11）It is completely filled, being etched away again by etching technics behind planarization surface is used for
Generation folds conductive layer（6）Part in addition, exposes launch site（3）, collecting zone（5）, barrier insulating layer（11）And base（4）It is adjacent
Nearly launch site（3）, collecting zone（5）Two ends, formed fold conductive layer（6）；
Step 9: deposit dielectric above wafer, then by surface planarisation to exposing folding conductive layer（6）Upper surface,
Again by etching technics respectively in the tunneling insulation layer of base both sides（7）Remote base side to barrier insulating layer（11）Enter
Row, which is etched to, exposes wafer insulating barrier（2）；
Step 10: depositing tunneling insulation layer medium above wafer, make the barrier insulating layer being etched away in step 9（11）It is complete
It is filled entirely, is etched away again by etching technics behind planarization surface and fold tunneling insulation layer for generating（7）With outer portion extremely
Expose barrier insulating layer（11）, formed and fold tunneling insulation layer（7）；
Step 11: respectively in the folding tunneling insulation layer of base both sides（7）Remote base side to barrier insulating layer
（11）Perform etching to exposing wafer insulating barrier（2）；
Step 12: depositing metal or the polysilicon of heavy doping above wafer, make the stop being etched away in step 11 exhausted
Edge layer（11）It is completely filled；Etched away again by etching technics behind planarization surface and fold gate electrode for generating（8）In addition
Part is to exposing barrier insulating layer（11）, preliminarily form folding gate electrode（8）；
Step 13: deposit dielectric above wafer, then by surface planarisation to exposing the folding that is formed among step 12
Stacked gate electrode（8）Upper surface；
Step 14: depositing metal or the polysilicon of heavy doping above wafer, and etch away for being formed between device cell
Part beyond trace portions, further forms and folds gate electrode（8）；
Step 15: dielectric is deposited above wafer, by surface planarisation；
Step 16: being etched away by etching technics positioned at launch site（3）And collecting zone（5）Top barrier insulating layer
（11）, form emitter stage（9）And colelctor electrode（10）Through hole；
Step 17: depositing metal above wafer, make the emitter stage formed in step 10 six（9）And colelctor electrode（10）It is logical
Hole is completely filled, and forms emitter stage by etching technics（9）And colelctor electrode（10）.
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