CN104409465B - Manufacturing method of high-voltage light emitting diode having high light emitting efficiency - Google Patents
Manufacturing method of high-voltage light emitting diode having high light emitting efficiency Download PDFInfo
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- CN104409465B CN104409465B CN201410666659.0A CN201410666659A CN104409465B CN 104409465 B CN104409465 B CN 104409465B CN 201410666659 A CN201410666659 A CN 201410666659A CN 104409465 B CN104409465 B CN 104409465B
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Abstract
The invention relates to a manufacturing method of a high-voltage light emitting diode having high light emitting efficiency; sub light emitting diodes having n independent light emitting structures are connected in series through a chip manufacturing process, so that an integrated chip module is formed, wherein a first electrode is arranged on the first sub light emitting diode; and a second electrode is arranged on the n<th> sub light emitting diode. By means of the invention, the light exit area of an active area can be increased; and thus, the light emitting efficiency is increased.
Description
Technical field
The present invention relates to LED technology field, refer in particular to a kind of high-voltage LED system of high-luminous-efficiency
Make method.
Background technology
Light emitting diode has that low-power consumption, size be little and high reliability, is rapidly sent out as main light source
Exhibition.In recent years, the application of light emitting diode extends rapidly, and range of application gradually expands, and improves brightness and reduction
Cost becomes light emitting diode field developing goal.
Using high-voltage LED（HV-LED）Can obviously reduce the application cost of light emitting diode.HV-LED has two
Advantage：One, effectively reduce light-emitting diode (LED) illuminating lamp cost and weight, can light more than 270 degree；The high electricity of two, HV-LED
Pressure, small current work, reduce heating, thus reducing the requirement to cooling system, fitting structure can save heat sink material.
HV-LED high voltage, small current condition of work have overturned traditional LED low-voltage, high current condition of work.Meanwhile,
HV-LED only needs high-voltage linear constant-current source just can work, and high-voltage linear constant-current supply transless, no electrolytic capacitor device solve general
The driving power supply of logical LED and the life problems of electrolytic capacitor.
However, in prior art, improving high-voltage LED brightness and essentially consist in the interior of the single light emitting diode of raising
Quantum efficiency and external quantum efficiency, the main single LED internal structure of change of passing through is realized, and the high pressure of described raising
The limitation of optical diode luminous efficiency is difficult to break through, and the present invention provides a kind of height of new raising light-emitting diode luminous efficiency
Laminated structure, this case thus produces.
Content of the invention
It is an object of the invention to provide a kind of high-voltage LED preparation method of high-luminous-efficiency, active to increase
The lighting area in area, improves luminous efficiency.
For reaching above-mentioned purpose, the solution of the present invention is：
A kind of high-voltage LED preparation method of high-luminous-efficiency, comprises the following steps：
One, epitaxial substrate is provided, the first type conductive layer, active area, Second-Type conductive layer are set gradually on epitaxial substrate；
Two, adopt mask in Second-Type conductive layer surface, ICP etches, form extension isolation channel, and etch depth is to extension
Substrate, the son forming several independent extension ray structures is level led；
Three, it is deposited with extension insulating barrier in extension isolation channel, be deposited with dielectric layer in Second-Type conductive layer surface simultaneously；
Four, extension insulating barrier and dielectric layer form multiple through holes for making conductive channel；
Five, in through hole and dielectric layer surface evaporation metal, form conductive channel and metallic reflector, metallic reflector steams
Plating metal conducting layer；
Six, metallic conduction layer surface mask, photoetching and etching smithcraft, metallic conduction layer surface formed metal every
From groove, the depth of metal isolation channel is to dielectric layer surface；Metal between the adjacent each son of non-series connection is level led every
Overlap in the vertical direction of ray structure with extension isolation channel from groove；
Seven, using non-conductive bonding material, metal conducting layer is bonded together with substrate, and non-conductive bonding material fills
Full metal isolation channel；
Eight, erosion removal epitaxial substrate, the exposed first sub level led first type level led to the n-th son
Conductive channel in conductive layer, and extension insulating barrier；
9th, mask, photoetching process are adopted on the first type conductive layer：Expose the surface of the second light emitting diode, bag simultaneously
Containing the region adjacent with the first light emitting diode, scope is until comprise conductive channel region and and conductive channel in extension insulating barrier
The surface that edge maintains an equal level, according to this until expose the surface of the n-th light emitting diode simultaneously, comprises adjacent with the (n-1)th light emitting diode
Region, scope is until comprise conductive channel region in extension insulating barrier and the surface maintaining an equal level with conductive channel edge；
Ten, on the level led exposed surface of each son evaporation ITO conductive layer so that each son level led it
Between extension insulating barrier in conductive channel and son adjacent thereto level led first type conductive layer formed connect；
11, adopt mask, photoetching, ICP etching in the level led ITO conductive layer of the n-th son, form second electrode
Making region, below etch depth to the Second-Type conductive layer and not up to contact surface of Second-Type conductive layer and dielectric layer；?
N-th son makes electrode isolation layers and second electrode on the level led making region of second electrode respectively；
12, the first level led type conductive layer of the first son forms first electrode；
13, surrounding's cutting splitting of a big module of each sub level led composition, formed described a kind of high
The high-voltage LED of luminous efficiency.
A kind of high-voltage LED preparation method of high-luminous-efficiency, comprises the following steps：
One, epitaxial substrate is provided, the first type conductive layer, active area, Second-Type conductive layer are set gradually on epitaxial substrate；
Two, adopt mask in Second-Type conductive layer surface, ICP etches, form extension isolation channel, and etch depth is to extension
Substrate, the son forming several independent extension ray structures is level led；
Three, it is deposited with extension insulating barrier in extension isolation channel；
Four, form the through hole for making conductive channel in extension insulating barrier；
Five, it is deposited with ITO material in through hole and Second-Type conductive layer surface, form conductive channel and the second ITO conductive layer；And
Form metallic reflector on the second ITO conductive layer surface；
Six, in the technique of metallic reflection layer surface mask, photoetching and etching metal and ITO, in metallic conduction layer surface shape
Become metal isolation channel, the depth of metal isolation channel is to extension surface of insulating layer；Level led in the adjacent each son of non-series connection
Between metal isolation channel overlap in the vertical direction of ray structure with the side of extension insulating barrier；
Seven, using non-conductive bonding material, metal conducting layer is bonded together with substrate, and non-conductive bonding material fills
Full metal isolation channel；
Eight, remove epitaxial substrate, the level led first type conduction level led to the n-th son of exposed first son
Layer, and the conductive channel in extension insulating barrier；
Nine, the first type conductive layer adopts mask, photoetching process, exposes the surface of the second light emitting diode simultaneously, bag
Containing the region adjacent with the first light emitting diode, scope is until comprise conductive channel region and and conductive channel in extension insulating barrier
The surface that edge maintains an equal level, according to this until expose the surface of the n-th light emitting diode simultaneously, comprises adjacent with the (n-1)th light emitting diode
Region, scope is until comprise conductive channel region in extension insulating barrier and the surface maintaining an equal level with conductive channel edge；
Ten, on the level led exposed surface of each son evaporation ITO conductive layer so that each son level led it
Between extension insulating barrier in conductive channel and son adjacent thereto level led first type conductive layer formed connect；
11, adopt mask, photoetching, ICP etching in the level led ITO conductive layer of the n-th son, form second electrode
Making region, below etch depth to the Second-Type conductive layer and not up to contact surface of Second-Type conductive layer and dielectric layer；?
N-th son makes electrode isolation layers and second electrode on the level led making region of second electrode respectively；
12, the first level led type conductive layer of the first son forms first electrode；
13, surrounding's cutting splitting of a big module of each sub level led composition, formed described a kind of high
The high-voltage LED of luminous efficiency.
A kind of high-voltage LED of high-luminous-efficiency, the son by n with independent ray structure is level led
In series, wherein, each son is level led all to comprise independent active area and separated from each other by extension insulating barrier；Active
First type conductive layer is arranged on area first contact surface, active area second contact surface arranges Second-Type conductive layer；
On the first level led type conductive layer of first son, first electrode is set, Second-Type conductive layer arranges medium
Layer, arranges conductive channel in dielectric layer, and dielectric layer arranges metallic reflector, and metallic reflector passes through conductive channel and second
Type conductive layer forms Ohmic contact, and metallic reflector arranges non-conductive bonded layer, arranges substrate on non-conductive bonded layer；
On the first level led type conductive layer of second son, ITO conductive layer is set, setting on Second-Type conductive layer is situated between
Matter layer, arranges conductive channel in dielectric layer, and dielectric layer arranges metallic reflector, and metallic reflector passes through conductive channel and second
Type conductive layer forms Ohmic contact, and metallic reflector arranges non-conductive bonded layer, arranges substrate on non-conductive bonded layer；
Second son is level led and the first son level led between extension insulating barrier, and extension insulating barrier are set
Middle setting conductive channel, conductive channel is formed with the first level led metallic reflector of son and is connected, and with the second sub- level
The ITO conductive layer of light emitting diode forms and connects；
On the first level led type conductive layer of 3rd son, ITO conductive layer is set, setting on Second-Type conductive layer is situated between
Matter layer, arranges conductive channel in dielectric layer, and dielectric layer arranges metallic reflector, and metallic reflector passes through conductive channel and second
Type conductive layer forms Ohmic contact, and metallic reflector arranges non-conductive bonded layer, arranges substrate on non-conductive bonded layer；According to
The secondary ITO conductive layer being connected to setting on the level led first type conductive layer of the n-th son, Second-Type conductive layer is arranged
Second electrode, and second electrode separated by second electrode insulating barrier and extension ray structure lateral side regions.
A kind of high-voltage LED of high-luminous-efficiency, the son by n with independent ray structure is level led
In series, wherein, each son is level led all to comprise independent active area and separated from each other by extension insulating barrier；Active
First type conductive layer is arranged on area first contact surface, active area second contact surface arranges Second-Type conductive layer；
On the first level led type conductive layer of first son, first electrode is set, Second-Type conductive layer arranges second
ITO conductive layer, the second ITO conductive layer arranges metallic reflector, metallic reflector arranges non-conductive bonded layer, non-conductive key
Close and substrate is arranged on layer；
The first level led type conductive layer of second son arranges the first ITO conductive layer, and Second-Type conductive layer is arranged
Second ITO conductive layer, the second ITO conductive layer arranges metallic reflector, metallic reflector arranges non-conductive bonded layer, non-leads
Substrate is arranged on bond layer；
Second son is level led and the first son level led between extension insulating barrier, and extension insulating barrier are set
Middle setting conductive channel, conductive channel second ITO conductive layer level led with the first son forms and is connected, and sub with second
The first level led ITO conductive layer forms and connects；
On the first level led type conductive layer of 3rd son, the first ITO conductive layer is set, Second-Type conductive layer sets
Put the second ITO conductive layer, the second ITO conductive layer arrange metallic reflector, non-conductive bonded layer is arranged on metallic reflector,
Substrate is arranged on non-conductive bonded layer；It is sequentially connected in series to setting on the level led first type conductive layer of the n-th son
First ITO conductive layer；On second ITO conductive layer, second electrode is set, and second electrode passes through second electrode insulating barrier and extension
Ray structure lateral side regions are separately.
Further, level led number n of son is 2-220.The level led number of sub-series is 2-220,
The overall work voltage range of the light emitting diode connected is between 3-440V.Had extensively using the high-voltage LED that this designs
Range of application, also may be directly applied to civilian voltage range, can save encapsulation and application in circuit and device making
Cost, also saves the power consumption using process.
Further, each son is level led shares this same layer functional structure of non-conductive bonded layer, and each sub- level lights
This same supporter of diode common substrate.
Further, between each son is level led, extension dielectric width d is 2 μm≤d≤100 μm.Extension insulate
Layer meets the width range of common LED Cutting Road using the scope of width；Or it is narrower than the width range of common LED Cutting Road, but
Width is not narrower than the width making extension insulating barrier conductive through hole；Or be wider than the width range of common LED Cutting Road, but too wide
The effectively luminous interval of whole Light-Emitting Diode high-pressure modular can be wasted.
Further, between each son is level led, the extension insulating barrier conductive channel of setting is regularly arranged, and its arrangement
Density D is 1≤D≤800/mm2.
Further, between each son is level led the figure of extension insulating barrier conductive channel include circle, square, three
Angle-style, ellipse, rectangle or trapezoidal, and the length of side of single extension insulating barrier conductive channel or diameter d are 1≤d≤200 μ
m.
The size of extension insulating barrier conductive channel, figure, distribution density are chosen interval in suitable numerical value.Size, distribution
Density, figure choose too small and improper can lead to cannot to be formed effective electric current between each son is level led and conduct, make
Become current crowding, the internal resistance increase of high-voltage LED module and chip overheating problem.Size, distribution density, figure are chosen
Excessive and improper each son can be caused level led between extension insulating barrier need to design wide, lead to baroluminescence two
Effective luminous zone of pole pipe module diminishes, and reduces the luminous efficiency of high-voltage LED module.
Further, the level led spread geometry of son of n series connection includes 2*（n/2）Matrix, 3*（n/3）Matrix, 4*
（n/4）Matrix, 5*（n/5）Matrix；Also non-matrix L-type, П type, Ш type are included.
Further, across non-between level led each the adjacent and non-connected independent metallic reflector of each son
Conductive bonding material.
Further, the interval of level led each the adjacent and non-connected second independent ITO conductive layer of each son
Non-conductive bonding material.
After such scheme, the present invention is connected in series level led for the son of each independent ray structure, is formed
The chip module of one, it will be apparent that increasing the area that active area goes out light, effectively improves the entirety of series connection light-emitting diode (LED) module
Luminous efficiency.
Brief description
Fig. 1 is the epitaxial structure schematic diagram of the embodiment of the present invention one；
Fig. 2 be the embodiment of the present invention one each son level led between isolation channel schematic diagram；
Fig. 3 be the embodiment of the present invention one each son level led between extension insulating barrier and dielectric layer schematic diagram；
Fig. 4 is the through hole schematic diagram that the embodiment of the present invention one makes extension insulating barrier and dielectric layer；
Fig. 5 is each son level led making conductive channel and the metallic mirror schematic diagram of the embodiment of the present invention one；
Fig. 6 is each son level led making metallic mirror isolation channel schematic diagram of the embodiment of the present invention one；
Fig. 7 is each sub level led metallic mirror isolation channel and the extension insulating barrier conduction of the embodiment of the present invention one
The plane distribution schematic diagram of passage；
Fig. 8 is that the light emitting diode of the embodiment of the present invention one is bonded substrate schematic diagram；
Fig. 9 is the light emitting diode construction schematic diagram that the embodiment of the present invention one removes epitaxial substrate；
Figure 10 is the level led schematic diagram making ITO conductive layer of each son of the embodiment of the present invention one；
Figure 11 is each sub level led extension insulating barrier conductive channel and the ITO conductive layer of the embodiment of the present invention one
Plane distribution schematic diagram；
Figure 12 is the side schematic view of the etching shape of second electrode making groove of the embodiment of the present invention one；
Figure 13 is that the first electrode of the embodiment of the present invention one makes schematic diagram with second electrode；
Figure 14 is that the plane distribution of a big module of each sub level led composition of the embodiment of the present invention one is illustrated
Figure；
Figure 15 is the epitaxial structure schematic diagram of the embodiment of the present invention two；
Figure 16 be the embodiment of the present invention two each son level led between isolation channel schematic diagram；
Figure 17 be the embodiment of the present invention two each son level led between extension insulating barrier schematic diagram；
Figure 18 is the schematic diagram of the through hole that the embodiment of the present invention two makes extension insulating barrier；
Figure 19 is each son level led making conductive channel, the second ITO conductive layer and the gold of the embodiment of the present invention two
Belong to the schematic diagram in reflecting layer；
Figure 20 is each son level led making second ITO conductive layer of the embodiment of the present invention two, metallic reflector
The schematic diagram of isolation channel；
Figure 21 is level led second ITO conductive layer of each son of the embodiment of the present invention two, metallic mirror every
Plane distribution schematic diagram from groove and the conductive channel of extension insulating barrier；
Figure 22 is the schematic diagram of the light emitting diode bonding substrate of the embodiment of the present invention two；
Figure 23 is the light emitting diode construction schematic diagram after the embodiment of the present invention two peels off epitaxial substrate；
Figure 24 is the level led schematic diagram making the first ITO conductive layer of each son of the embodiment of the present invention two；
Figure 25 is the conductive channel of each sub- LED epitaxial insulating barrier and the ITO conduction of the embodiment of the present invention two
The plane distribution schematic diagram of layer；
Figure 26 is the side schematic view of the etching shape of second electrode making groove of the embodiment of the present invention two；
Figure 27 is first electrode and the second electrode making schematic diagram of the embodiment of the present invention two；
Figure 28 is that the plane distribution of a big module of each sub level led composition of the embodiment of the present invention two is illustrated
Figure.
Label declaration
Level led 10 first electrodes 20 of son
Second electrode 30 second electrode insulating barrier 301
Epitaxial substrate 40 cushion 50
Etch stop layers 60 extension isolation channel 70
Sacrifice layer 80
Active area 1
First type conductive layer 2 Second-Type conductive layer 3
Dielectric layer 4 conductive channel 41
Metallic reflector 5 metal isolation channel 51
Non-conductive bonded layer 6 substrate 7
ITO conductive layer 8 first ITO conductive layer 81
Second ITO conductive layer 82 extension insulating barrier 9
Conductive channel 91 through hole 92.
Specific embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in detail.
Embodiment one
A kind of high-voltage LED of high-luminous-efficiency, by 100 sub- level light-emitting diodes with independent ray structure
Pipe 10 is in series, and spread geometry is the matrix arrangement of 10*10, as shown in figure 14, the first son level led 10 sets
Put first electrode 20, the n-th son level led 10 arranges second electrode 30.
As shown in figure 13, wherein each height level led 10 all comprises independent active area 1, in active area 1 first
First type conductive layer 2 is arranged on contact surface, Second-Type conductive layer 3 is arranged on active area 1 second contact surface.First type conductive layer
2 are made up of the first type current extending and the first type limiting layer.It is specially the first type current extending by (Al0.35Ga0.65)0.5In0.5P III-V compound is constituted, and thickness is 4 μm.First type limiting layer is by (Al0.8Ga0.2)0.5In0.5P III-V chemical combination
Thing is constituted, and thickness is 800nm.Active layer 1 is by 20 groups of (Al0.8Ga0.2)0.5In0.5P/Ga0.5In0.5P III-V compound replaces
Constitute.Second-Type conductive layer 3 is made up of Second-Type limiting layer and Second-Type current extending.Second-Type limiting layer by
(Al0.8Ga0.2)0.5In0.5P III-V compound is constituted, and thickness is 800nm.Second-Type current extending is by GaP III-V
Compound is constituted, and thickness is 4 μm.
On first type current extending of the first son level led 10, first electrode 20, Second-Type conductive layer 3 are set
Upper setting SiO2Dielectric layer 4, SiO2It is provided with the conductive channel 41, SiO of filling metal material in dielectric layer 42Set on dielectric layer 4
Put metallic reflector 5, and metallic reflector 5 passes through conductive channel 41 and forms Ohmic contact with Second-Type current extending, in gold
Belong to and on reflecting layer 5, non-conductive bonded layer 6 is set, silicon substrate 7 is arranged on non-conductive bonded layer 6.
On first type current extending of the second son level led 10, ITO conductive layer 8, Second-Type current expansion are set
SiO is arranged on layer2Dielectric layer 4, SiO2It is provided with the conductive channel 41, SiO of filling metal material in dielectric layer 42On dielectric layer 4
Setting metallic reflector 5, and metallic reflector 5 passes through conductive channel 41 and Second-Type current extending formation Ohmic contact,
Non-conductive bonded layer 6 is arranged on metallic reflector 5, silicon substrate 7 is arranged on non-conductive bonded layer 6.
It is provided with SiO between second son level led 10 and the first son level led 102Extension insulating barrier 9,
And SiO2It is provided with the conductive channel 91 of filling metal material, conductive channel 91 and the first sub- level luminous two in extension insulating barrier 9
The metallic reflector 5 of pole pipe 10 forms and connects, and is connected with ITO conductive layer 8 formation of the second son level led 10.
On first type current extending of the 3rd son level led 10, ITO conductive layer 5, Second-Type current expansion are set
SiO is arranged on layer2Dielectric layer 4, SiO2It is provided with the conductive channel 41, SiO of filling metal material in dielectric layer 42On dielectric layer 4
Setting metallic reflector 5, and metallic reflector 5 passes through conductive channel 41 and Second-Type current extending formation Ohmic contact,
Non-conductive bonded layer 6 is arranged on metallic reflector 5, silicon substrate 7 is arranged on non-conductive bonded layer 6.
It is provided with SiO between 3rd son level led 10 and the second son level led 102Extension insulating barrier 9,
And SiO2It is provided with the conductive channel 91 of filling metal material, conductive channel 91 and the second sub- level luminous two in extension insulating barrier 9
The metallic reflector 5 of pole pipe 10 forms and connects, and is connected with ITO conductive layer 8 formation of the 3rd son level led 10.
The chip structure connected mode of described two sons level led 10 of circulation is to the 99th sub- level luminous two
Pole pipe 10.
ITO conductive layer 8 is arranged on the first type current extending of the first the ancient philosophers level led 10, Second-Type electric current expands
On exhibition layer, SiO is set2Dielectric layer 4, SiO2It is provided with the conductive channel 41, SiO of filling metal material in dielectric layer 42Dielectric layer 4
Upper setting metallic reflector 5, and metallic reflector 5 passes through conductive channel 41 and Second-Type current extending formation Ohmic contact,
Non-conductive bonded layer 6 is arranged on metallic reflector 5, silicon substrate 7 is arranged on non-conductive bonded layer 6；Second-Type current expansion
Layer and active area 1 adjacent surface are provided with second electrode 30, and second electrode 30 is passed through second electrode insulating barrier 301 and lighted with extension
Structure is separately.
It is provided with SiO between first the ancient philosophers the level led 10 and the 99th son level led 102Extension is exhausted
Edge layer 9, and SiO2It is provided with the conductive channel 91 of filling metal material, conductive channel 91 and the 99th in extension insulating barrier 9
Son level led 10 metallic reflector 5 formed connect, and level led with the first the ancient philosophers 10 ITO conductive layer 8
Formed and connect.
A kind of high-voltage LED preparation method of described high-luminous-efficiency, mainly includes the following steps that：
One, as shown in figure 1, in the upper surface of epitaxial substrate 40 extension successively from the bottom to top：Cushion 50, etch stop layers
60th, the first type conductive layer 2, active area 1, Second-Type conductive layer 3.
Epitaxial substrate 40 adopts 2 inches of GaAs substrate, and thickness is 270 μm.Cushion 50 is by the GaAs material group of 300nm
Become.Etch stop layers 60 are by the thick (Al of 300nm0.7Ga0.3)0.5In0.5P material forms.
Two, as shown in Fig. 2 adopting mask on the Second-Type conductive layer 3 on 2 inches of epitaxial wafer surface, ICP etches,
The level led 10 formation width of each son of non-series connection are 4 μm of extension isolation channel 70, in each sub- level light-emitting diodes of series connection
It is 20 μm of extension isolation channels 70 that pipe 10 forms width, and etch depth, to etch stop layers 60, forms tens of thousands of 10mil*10mil
The independent extension ray structure of size.
Three, as shown in figure 3, being deposited with SiO in extension isolation channel 702Form extension insulating barrier 9, simultaneously conductive in Second-Type
Layer 3 surface evaporation SiO2Form dielectric layer 4.
Four, as shown in figure 4, the extension insulating barrier 9 of 20 μm wide between each son level led 10 of series connection is formed
Density is 300/mm2, a diameter of 4 μm circle extension insulating barrier through hole 92；And form density in dielectric layer 4 simultaneously
For 150/mm2, the dielectric layer through hole 42 of a diameter of 10 μm of circle.
Five, as shown in figure 5, in extension insulating barrier through hole 92, dielectric layer through hole 42 and dielectric layer 4 surface evaporation metal, gold
Belong to filling full extension insulating barrier through hole 92, dielectric layer through hole 42, form conductive channel（91、41）；And form the thick gold of 400nm
Belong to reflecting layer 5；Thicken metallic reflector 5 to 1 μ m-thick again so that metallic reflector 5 forms preferable conductive effect.
Six, as shown in fig. 6, in metallic reflector 5 surface mask, photoetching and etching smithcraft, in metallic reflector 5 table
The metal isolation channel 51 of face formation rule, the width size of metal isolation channel 51 is 4 μm, and the depth of metal isolation channel 51 is to medium
Layer 4 surface；Metal isolation channel 51 between the adjacent each son of non-series connection level led 10 and extension insulating barrier 9 are luminous
Overlap in the vertical direction of structure；Exhausted with extension in the adjacent metal isolation channel 51 connected between each son level led 10
Edge layer 9 conductive channel 91 staggers, and with monolateral extension insulating barrier 9 in the vertical direction of ray structure, overlaps, and is formed as schemed
Metal isolation channel 51 distribution situation shown in 7.
Seven, as shown in figure 8, metallic reflector 5 is bonded together with silicon substrate 7 using non-conductive bonding material, and shape
Become non-conductive bonded layer 6, non-conductive bonded layer 6 is full of metal isolation channel 51 and forms insulation.
Eight, as shown in figure 9, erosion removal epitaxial substrate 40, cushion 50 and etch stop layers 60 respectively, expose the first type
Conductive layer 2.
Nine, on the first type conductive layer 2 after mask, photoetching process, expose level led 10 surfaces of the second son
The first type conductive layer 2, comprise and the first level led 10 adjacent regions of son, scope is to comprising in extension insulating barrier 9
Conductive channel 91 region, and the surface maintaining an equal level with conductive channel 91 edge；Expose level led 10 surfaces of the 3rd son simultaneously
First type conductive layer 2, comprises and the second level led 10 adjacent regions of son, and scope is to comprising to lead in extension insulating barrier 9
Electric channel 91 region, and the surface maintaining an equal level with conductive channel 91 edge, successively until expose first the ancient philosophers's level light-emitting diodes simultaneously
Pipe 10 surface the first type conductive layer 2, comprises 10 adjacent regions level led with the 99th son, until it is exhausted to comprise extension
Conductive channel 91 region in edge layer 9, and the surface maintaining an equal level with conductive channel 91 edge.
Ten, as shown in Figures 10 and 11, level led 10 exposed the first type conductive layer 2 surfaces of each son are deposited with
ITO conductive layer 8 is so that conductive channel 91 and son adjacent thereto in extension insulating barrier 9 between each son level led 10
Level led 10 first type conductive layer 2 forms and connects.
11, as shown in figure 12, adopt mask, photoetching, ICP in the ITO conductive layer 8 of the first the ancient philosophers level led 10
Etching, forms the making region of second electrode 30,2 μm below etch depth to Second-Type current extending.
12, as shown in figure 13, make in the second electrode 30 of the first the ancient philosophers level led 10 and make respectively on region
Make second electrode insulating barrier 301 and second electrode 30.
13, as shown in figure 13, the first electricity is formed on the first type current extending of the first son level led 10
Pole 20.
14, as shown in figure 14, surrounding's cutting of the big module that 100 sons level led 10 are formed is split
Piece, forms the high-voltage LED of described high-luminous-efficiency.
Embodiment two
A kind of high-voltage LED of high-luminous-efficiency, by 72 sub- levels luminous two with independent ray structure
Pole pipe 10 is in series, and spread geometry is the matrix arrangement of 8*9, as shown in figure 28.
As shown in figure 27, wherein each height level led 10 all comprises independent active area 1, and active area 1 first connects
First type conductive layer 2 is arranged on contacting surface, active area 1 second contact surface arranges Second-Type conductive layer 3.First type conductive layer 2 is adopted
The GaN III-V compound being adulterated with Si, thickness is 2.5 μm.Active layer 1 adopts 5 to build intersection growth to SQW and quantum
Structure.It is specially quantum and builds and be made up of AlGaN III-V compound, thickness is 12nm.SQW is by GaInN III-V compound
Constitute, thickness is 4nm.Second-Type conductive layer 3 adopts the GaN III-V compound of Mg doping, and thickness is 200nm.
On first type conductive layer 2 of the first son level led 10, first electrode 20 is set, Second-Type conductive layer 3 sets
Put the second ITO conductive layer 82, the second ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 is arranged non-conductive
Bonded layer 6, arranges silicon substrate 7 on non-conductive bonded layer 6.
On first type conductive layer 2 of the second son level led 10, the first ITO conductive layer 81, Second-Type conductive layer are set
Second ITO conductive layer 82 is set on 3, the second ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 is arranged non-
Conductive bond layer 6, arranges silicon substrate 7 on non-conductive bonded layer 6.
It is provided with SiO between second son level led 10 and the first son level led 102Extension insulating barrier 9,
And SiO2It is provided with the conductive channel 91 of the full metal of filling, conductive channel 91 and the first sub grade light-emitting diodes in extension insulating barrier 9
Second ITO conductive layer 82 of pipe 10 forms and connects, and is formed even with first ITO conductive layer 81 of the second son level led 10
Connect.
On first type conductive layer 2 of the 3rd son level led 10, the first ITO conductive layer 81, Second-Type conductive layer are set
Second ITO conductive layer 82 is set on 3, the second ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 is arranged non-
Conductive bond layer 6, arranges silicon substrate 7 on non-conductive bonded layer 6.
It is provided with SiO between 3rd son level led 10 and the second son level led 102Extension insulating barrier 9,
And SiO2It is provided with the conductive channel 91 of the full metal of filling, conductive channel 91 and the second sub grade light-emitting diodes in extension insulating barrier 9
Second ITO conductive layer 82 of pipe 10 forms and connects, and is formed even with first ITO conductive layer 81 of the 3rd son level led 10
Connect.
The connected mode circulating the chip structure of described son level led 10 is level led to the 71st son
10.
On first type conductive layer 2 of the 72nd son level led 10, first ITO conductive layer 81 is set, Second-Type is led
Second ITO conductive layer 82 is arranged on electric layer 3, the second ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 sets
Put non-conductive bonded layer 6, silicon substrate 7 is arranged on non-conductive bonded layer 6；Second ITO conductive layer 82 and Second-Type conductive layer 3
Second electrode 30 is provided with phase-contact surface, and second electrode 30 passes through SiO2Second electrode insulating barrier 301 and extension light-emitting junction
Structure is separately.
It is provided with SiO between 72nd son the level led 10 and the 71st son level led 102Extension
Insulating barrier 9, and SiO2It is provided with the conductive channel 91 of the full metal of filling, conductive channel 91 and the 71st in extension insulating barrier 9
Second ITO conductive layer 82 of son level led 10 forms and connects, and first with the 72nd son level led 10
ITO conductive layer 81 forms and connects.
A kind of high-voltage LED preparation method of described high-luminous-efficiency, mainly includes the following steps that：
One, as shown in figure 15, in the upper surface of epitaxial substrate 40 extension successively from the bottom to top：Cushion 50, sacrifice layer 80,
First type conductive layer 2, active area 1, Second-Type conductive layer 3.
It is specially the Sapphire Substrate that epitaxial substrate 40 adopts 4 inches, thickness is 400 μm.Cushion 50 adopts non-impurity-doped
GaN III-V compound, thickness be 2 μm.
Two, as shown in figure 16, mask is adopted on the Second-Type conductive layer 3 on 4 inches of epitaxial wafer surface, ICP etches, shape
Become extension isolation channel 70, extension isolation channel 70 is 3 μm in level led 10 width of each son of non-series connection, extension isolation channel 70
Form width in each son of series connection level led 10 and be 24 μm, and etch depth, to sacrifice layer 80, forms tens of thousands of
The independent extension ray structure of 10mil*10mil size.
Three, as shown in figure 17, it is deposited with SiO in extension isolation channel 702Material, forms extension insulating barrier 9.
Four, as shown in figure 18, forming density in extension insulating barrier 9 is 200/mm2, a diameter of 8 μm circle through hole
92.
Five, as shown in figure 19, be deposited with ITO material on through hole 92 and Second-Type conductive layer 3 surface, formed conductive channel 91 and
Second ITO conductive layer 82；And form metallic reflector 5 on the second ITO conductive layer 82 surface.
Six, as shown in figure 20, on metallic reflector 5 surface through mask, photoetching and the technique etching metal, ITO, in gold
Belong to the metal isolation channel 51 of reflecting layer 5 surface formation rule, the width size of metal isolation channel 51 is 4 μm, metal isolation channel 51
Depth to extension insulating barrier 9 surface；Metal isolation channel 51 between the adjacent each son of non-series connection level led 10 with
Extension insulating barrier 9 overlaps in the vertical direction of ray structure；In the adjacent gold connected between each son level led 10
Belong to isolation channel 51 to stagger with conductive channel 91, and overlap in the vertical direction of ray structure with monolateral extension insulating barrier 9, shape
Become metal isolation channel 51 distribution situation as shown in figure 21.
Seven, as shown in figure 22, using non-conductive bonding material, metallic reflector 5 is bonded together with silicon substrate 7, and shape
Become non-conductive bonded layer 6, non-conductive bonded layer 6 is full of metal isolation channel 51 and forms insulation.
Eight, as shown in figure 23, epitaxial substrate 40, cushion 50 and sacrifice layer 80 are removed using laser lift-off technique, exposes
First type conductive layer 2.
Nine, the first type conductive layer 2 adopts mask, photoetching process, exposes the second light emitting diode 10 first type conductive
The surface of layer 2, comprises the region adjacent with the first light emitting diode 10, and scope is to comprising conductive channel 91 in extension insulating barrier 9
Region, and the surface maintaining an equal level with conductive channel 91 edge；Expose the table of the 3rd light emitting diode 10 first type conductive layer 2 simultaneously
Face, comprises the region adjacent with the second light emitting diode 10, scope until comprise conductive channel 91 region in extension insulating barrier 9,
And the surface fair with conductive channel 91 edge, successively until expose the 72nd light emitting diode 10 first type conductive layer simultaneously
2 surface, comprises the region adjacent with the 71st light emitting diode 10, and scope is until comprise conductive logical in extension insulating barrier 9
Road 91 region, and the surface maintaining an equal level with conductive channel 91 edge.
Ten, as shown in Figure 24 and Figure 25, exposed the first type conductive layer 2 surface of each son level led 10 is steamed
Plate the first ITO conductive layer 81 so that conductive channel 91 and phase therewith in extension insulating barrier 9 between each son level led 10
Adjacent single first type conductive layer 2 forms and connects.
11, as shown in figure 26, the first ITO conductive layer 81 of the 72nd son level led 10 adopt mask,
Photoetching, ICP etching, form second electrode 30 and make region, and etch depth is to the second ITO conductive layer 82 and Second-Type conductive layer 3
Contact surface.
12, as shown in figure 27, make on region respectively in the second electrode 30 of the 72nd son level led 10
Make second electrode insulating barrier 301 and second electrode 30.
13, as shown in figure 27, the first type conductive layer 2 of the first son level led 10 forms first electrode
20.
14, as shown in figure 28, surrounding's cutting of the big module that 72 sons level led 10 are formed
Sliver, forms the high-voltage LED of described high-luminous-efficiency.
The foregoing is only the preferred embodiments of the present invention, not the restriction to this case design, all designs according to this case are closed
The equivalent variations that key is done, each fall within the protection domain of this case.
Claims (10)
1. a kind of high-voltage LED preparation method of high-luminous-efficiency is it is characterised in that comprise the following steps：
One, epitaxial substrate is provided, the first type conductive layer, active area, Second-Type conductive layer are set gradually on epitaxial substrate；
Two, adopt mask in Second-Type conductive layer surface, ICP etches, form extension isolation channel, and etch depth serves as a contrast to extension
Bottom, the son forming several independent extension ray structures is level led；
Three, it is deposited with extension insulating barrier in extension isolation channel, be deposited with dielectric layer in Second-Type conductive layer surface simultaneously；
Four, extension insulating barrier and dielectric layer form multiple through holes for making conductive channel；
Five, in through hole and dielectric layer surface evaporation metal, form conductive channel and metallic reflector, gold evaporation on metallic reflector
Belong to conductive layer；
Six, in metallic conduction layer surface mask, photoetching and etching smithcraft, form metal isolation in metallic conduction layer surface
Groove, the depth of metal isolation channel is to dielectric layer surface；Metal isolation between the adjacent each son of non-series connection is level led
Groove is overlapped in the vertical direction of ray structure with extension isolation channel；
Seven, using non-conductive bonding material, metal conducting layer is bonded together with substrate, and non-conductive bonding material is full of gold
Belong to isolation channel；
Eight, erosion removal epitaxial substrate, the level led first type conduction level led to the n-th son of exposed first son
Layer, and the conductive channel in extension insulating barrier；
9th, mask, photoetching process are adopted on the first type conductive layer：Expose the surface of the second light emitting diode simultaneously, comprise with
The adjacent region of first light emitting diode, scope until comprise in extension insulating barrier conductive channel region and with conductive channel edge
Fair surface, according to this until expose the surface of the n-th light emitting diode simultaneously, comprises the area adjacent with the (n-1)th light emitting diode
Domain, scope is until comprise conductive channel region and the surface fair with conductive channel edge in extension insulating barrier；
Ten, on the level led exposed surface of each son, evaporation ITO conductive layer is so that between each son is level led
In extension insulating barrier conductive channel and son adjacent thereto level led first type conductive layer formed connect；
11, adopt mask, photoetching, ICP etching in the level led ITO conductive layer of the n-th son, form the system of second electrode
Make region, below etch depth to Second-Type conductive layer and not up to the contact surface of Second-Type conductive layer and dielectric layer；In the n-th son
Electrode isolation layers and second electrode is made respectively on the making region of level led second electrode；
12, the first level led type conductive layer of the first son forms first electrode；
13, surrounding's cutting splitting of a big module of each sub level led composition, formed described a kind of high luminous
The high-voltage LED of efficiency.
2. a kind of high-voltage LED preparation method of high-luminous-efficiency is it is characterised in that comprise the following steps：
One, epitaxial substrate is provided, the first type conductive layer, active area, Second-Type conductive layer are set gradually on epitaxial substrate；
Two, adopt mask in Second-Type conductive layer surface, ICP etches, form extension isolation channel, and etch depth serves as a contrast to extension
Bottom, the son forming several independent extension ray structures is level led；
Three, it is deposited with extension insulating barrier in extension isolation channel；
Four, form the through hole for making conductive channel in extension insulating barrier；
Five, it is deposited with ITO material in through hole and Second-Type conductive layer surface, form conductive channel and the second ITO conductive layer；And
Two ITO conductive layer surfaces form metallic reflector；
Six, in the technique of metallic reflection layer surface mask, photoetching and etching metal and ITO, form gold in metallic conduction layer surface
Belong to isolation channel, the depth of metal isolation channel is to extension surface of insulating layer；Between the adjacent each son of non-series connection is level led
Metal isolation channel overlap in the vertical direction of ray structure with the side of extension insulating barrier；
Seven, using non-conductive bonding material, metal conducting layer is bonded together with substrate, and non-conductive bonding material is full of gold
Belong to isolation channel；
Eight, removal epitaxial substrate, the exposed first sub level led first type conductive layer level led to the n-th son,
And the conductive channel in extension insulating barrier；
Nine, on the first type conductive layer adopt mask, photoetching process, expose the surface of the second light emitting diode simultaneously, comprise with
The adjacent region of first light emitting diode, scope until comprise in extension insulating barrier conductive channel region and with conductive channel edge
Fair surface, according to this until expose the surface of the n-th light emitting diode simultaneously, comprises the area adjacent with the (n-1)th light emitting diode
Domain, scope is until comprise conductive channel region and the surface fair with conductive channel edge in extension insulating barrier；
Ten, on the level led exposed surface of each son, evaporation ITO conductive layer is so that between each son is level led
In extension insulating barrier conductive channel and son adjacent thereto level led first type conductive layer formed connect；
11, adopt mask, photoetching, ICP etching in the level led ITO conductive layer of the n-th son, form the system of second electrode
Make region, below etch depth to Second-Type conductive layer and not up to the contact surface of Second-Type conductive layer and dielectric layer；In the n-th son
Electrode isolation layers and second electrode is made respectively on the making region of level led second electrode；
12, the first level led type conductive layer of the first son forms first electrode；
13, surrounding's cutting splitting of a big module of each sub level led composition, formed described a kind of high luminous
The high-voltage LED of efficiency.
3. as claimed in claim 1 or 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that
Level led number n of son is 2-220.
4. as claimed in claim 1 or 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that
Using non-conductive bonding material, metal conducting layer is bonded together with substrate, thus being formed between metal conducting layer and substrate
Non-conductive bonded layer, each son is level led to share non-conductive bonded layer, and each sub level led common substrate.
5. as claimed in claim 1 or 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that
Between each son is level led, extension dielectric width d is 2 μm≤d≤100 μm.
6. as claimed in claim 1 or 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that
Between each son is level led setting extension insulating barrier conductive channel regularly arranged, and its arranging density D be 1≤D≤
800/mm2.
7. as claimed in claim 1 or 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that
Between each son is level led, the figure of extension insulating barrier conductive channel includes circle, square, triangular form, ellipse, length
Square or trapezoidal, and the length of side of single extension insulating barrier conductive channel or diameter d are 1≤d≤200 μm.
8. as claimed in claim 1 or 2 a kind of high-voltage LED preparation method of high-luminous-efficiency it is characterised in that n
The level led spread geometry of son of individual series connection includes 2*（n/2）Matrix, 3*（n/3）Matrix, 4*（n/4）Matrix, 5*（n/5）
Matrix；Also non-matrix L-type, П type, Ш type are included.
9. as claimed in claim 1 a kind of high-voltage LED preparation method of high-luminous-efficiency it is characterised in that each son
Across non-conductive bonding material between level led each adjacent and non-connected independent metallic reflector.
10. as claimed in claim 2 a kind of high-luminous-efficiency high-voltage LED preparation method it is characterised in that：Respectively
Across non-conductive bonding material between level led each the adjacent and non-connected second independent ITO conductive layer of son.
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