CN204243043U - A kind of high-voltage LED of high-luminous-efficiency - Google Patents
A kind of high-voltage LED of high-luminous-efficiency Download PDFInfo
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- CN204243043U CN204243043U CN201420699609.8U CN201420699609U CN204243043U CN 204243043 U CN204243043 U CN 204243043U CN 201420699609 U CN201420699609 U CN 201420699609U CN 204243043 U CN204243043 U CN 204243043U
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Abstract
The high-voltage LED of a kind of high-luminous-efficiency of the utility model, the son by n with independent ray structure is level led in series, wherein, arranges the first electrode on the first son is level led, arranges the second electrode on the n-th son is level led.The utility model can increase the lighting area of active area, improves luminous efficiency.
Description
Technical field
The utility model relates to LED technology field, refers in particular to a kind of high-voltage LED of high-luminous-efficiency.
Background technology
Light-emitting diode has the little and high reliability of low-power consumption, size, obtains fast development as main light source.In recent years, the application of light-emitting diode is expanded rapidly, and range of application expands gradually, and improves brightness and reduce costs and become light-emitting diode field developing goal.
Use high-voltage LED (HV-LED) obviously can reduce the application cost of light-emitting diode.HV-LED has two advantages: one, effectively reduces light-emitting diode (LED) illuminating lamp cost and weight, can be greater than 270 degree of luminescences; Two, HV-LED high voltage, small area analysis work, reduce heating, thus reduce the requirement to cooling system, and fitting structure can save heat sink material.
HV-LED high voltage, small area analysis condition of work have overturned traditional LED low-voltage, big current condition of work.Meanwhile, HV-LED only needs high-voltage linear constant-current source just can work, and high-voltage linear constant-current supply transless, no electrolytic capacitor device solve the driving power of common LED and the life problems of electrolytic capacitor.
But, in prior art, improve high-voltage LED brightness and be mainly the internal quantum efficiency and the external quantum efficiency that improve single light-emitting diode, realize mainly through changing single LED internal structure, and the limitation of described raising high-voltage LED luminous efficiency is difficult to break through, the utility model provides a kind of high voltage structures of novel raising light-emitting diode luminous efficiency, and this case produces thus.
Utility model content
The purpose of this utility model is the high-voltage LED providing a kind of high-luminous-efficiency, to increase the lighting area of active area, improves luminous efficiency.
For reaching above-mentioned purpose, solution of the present utility model is:
A high-voltage LED for high-luminous-efficiency, the son by n with independent ray structure is level led in series, and wherein, each son is level led all comprises independently active area and separated from each other by extension insulating barrier; Active area first contact-making surface is arranged the first type conductive layer, active area second contact-making surface arranges Second-Type conductive layer;
The first type conductive layer that first son is level led arranges the first electrode, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, and metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
The first type conductive layer that second son is level led arranges ITO conductive layer, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
Second son level led and first son level led between extension insulating barrier is set, and in extension insulating barrier, conductive channel is set, conductive channel is formed with the first son level led metallic reflector and is connected, and is formed with the second sub level led ITO conductive layer and be connected;
The first type conductive layer that 3rd son is level led arranges ITO conductive layer, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate; Be sequentially connected in series the ITO conductive layer arranged to the level led first type conductive layer of the n-th son, Second-Type conductive layer is arranged the second electrode, and the second electrode separated with extension ray structure lateral side regions by the second electrode dielectric layer.
A high-voltage LED for high-luminous-efficiency, the son by n with independent ray structure is level led in series, and wherein, each son is level led all comprises independently active area and separated from each other by extension insulating barrier; Active area first contact-making surface is arranged the first type conductive layer, active area second contact-making surface arranges Second-Type conductive layer;
The first type conductive layer that first son is level led arranges the first electrode, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
The first level led type conductive layer of second son arranges an ITO conductive layer, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
Second son level led and first son level led between extension insulating barrier is set, and in extension insulating barrier, conductive channel is set, conductive channel is formed with the first son level led the 2nd ITO conductive layer and is connected, and is formed with the second sub level led ITO conductive layer and be connected;
The first type conductive layer that 3rd son is level led arranges an ITO conductive layer, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector arranges non-conductive bonded layer, non-conductive bonded layer arranges substrate; Be sequentially connected in series the ITO conductive layer arranged to the level led first type conductive layer of the n-th son; 2nd ITO conductive layer arranges the second electrode, and the second electrode is separated with extension ray structure lateral side regions by the second electrode dielectric layer.
Further, the level led number n of son is 2-220.The level led number of sub-series is 2-220, and the overall work voltage range of the light-emitting diode of connecting is between 3-440V.The high-voltage LED adopting this to design is with a wide range of applications, and also can directly apply to civilian voltage range, can save the cost of manufacture of encapsulation and the circuit in applying and device, also save the power consumption of use procedure.
Further, each son is level led shares this same layer functional structure of non-conductive bonded layer, and this same supporter of the level led common substrate of each son.
Further, each son level led between extension dielectric width d be 2 μm≤d≤100 μm.Extension insulating barrier adopts the scope of width to meet the width range of common LED Cutting Road; Or be narrower than the width range of common LED Cutting Road, but width is not narrower than the width making extension insulating barrier conductive through hole; Or wider than the width range of common LED Cutting Road, but between the too wide effective luminous zone wasting whole Light-Emitting Diode high-pressure modular.
Further, the extension insulating barrier conductive channel arranged between each son is level led is regularly arranged, and its arranging density D is 1≤D≤800/mm
2.
Further, between each son is level led, the figure of extension insulating barrier conductive channel comprises circle, square, triangular form, ellipse, rectangle or trapezoidal, and the length of side of single extension insulating barrier conductive channel or diameter d are 1≤d≤200 μm.
The size of extension insulating barrier conductive channel, figure, distribution density choose interval at suitable numerical value.Size, distribution density, figure choose too small and improper meeting cause each son level led between cannot form the conduction of effective electric current, cause current crowding, the internal resistance increase of high-voltage LED module and chip overheating problem.Size, distribution density, figure choose excessive and improper meeting cause each son level led between extension insulating barrier need design wide, cause effective luminous zone of high-voltage LED module to diminish, reduce the luminous efficiency of high-voltage LED module.
Further, n series connection the level led spread geometry of son comprise 2*(n/2) matrix, 3*(n/3) matrix, 4*(n/4) matrix, 5*(n/5) matrix; Also non-matrix L-type, П type, Ш type is comprised.
Further, level led adjacent of each son and non-connected each independently between metallic reflector across non-conductive bonding material.
Further, level led adjacent of each son and non-connected each independently between the 2nd ITO conductive layer across non-conductive bonding material.
A high-voltage LED manufacture method for high-luminous-efficiency, comprises the following steps:
One, epitaxial substrate is provided, epitaxial substrate sets gradually the first type conductive layer, active area, Second-Type conductive layer;
Two, adopt mask at Second-Type conductive layer surface, ICP etches, and form extension isolation channel, and etch depth is to epitaxial substrate, the son forming several independent extension ray structures is level led;
Three, evaporation extension insulating barrier in extension isolation channel, simultaneously at Second-Type conductive layer surface evaporation dielectric layer;
Four, in extension insulating barrier and dielectric layer, form multiple through hole for making conductive channel;
Five, at through hole and dielectric layer surface evaporation metal, form conductive channel and metallic reflector, evaporation metal conductive layer on metallic reflector;
Six, in metal conducting layer surface mask, photoetching and etching metal technique, form metal isolation channel on metal conducting layer surface, the degree of depth of metal isolation channel is to dielectric layer surface; Metal isolation channel between the adjacent each son of non-series connection is level led overlaps in the vertical direction of ray structure with extension isolation channel;
Seven, adopt non-conductive bonding material that metal conducting layer and substrate are bonded together, and non-conductive bonding material is full of metal isolation channel;
Eight, erosion removal epitaxial substrate, the level led first type conductive layer level led to the n-th son of exposed first son, and the conductive channel in extension insulating barrier;
Nine, on the first type conductive layer, mask, photoetching process is adopted: the surface of simultaneously exposing the second light-emitting diode, comprise the region adjacent with the first light-emitting diode, scope is until comprise conductive channel region in extension insulating barrier and the surface fair with conductive channel edge, according to this until expose the surface of the n-th light-emitting diode simultaneously, comprise the region adjacent with the (n-1)th light-emitting diode, scope is until comprise conductive channel region in extension insulating barrier and the surface fair with conductive channel edge;
Ten, evaporation ITO conductive layer on the exposed surface that each son is level led, make each son level led between extension insulating barrier in level led the first type conductive layer of conductive channel and son adjacent with it formed and be connected;
11, adopt mask, photoetching, ICP etching at the level led ITO conductive layer of the n-th son, form the making region of the second electrode, below etch depth to Second-Type conductive layer, do not reach the contact-making surface of Second-Type conductive layer and dielectric layer; The making region of level led the second electrode of the n-th son makes electrode isolation layers and the second electrode respectively;
12, the first type conductive layer that the first son is level led forms the first electrode;
13, surrounding's cutting splitting of a large module of level led for each son composition, form the high-voltage LED of described a kind of high-luminous-efficiency.
A high-voltage LED manufacture method for high-luminous-efficiency, comprises the following steps:
One, epitaxial substrate is provided, epitaxial substrate sets gradually the first type conductive layer, active area, Second-Type conductive layer;
Two, adopt mask at Second-Type conductive layer surface, ICP etches, and form extension isolation channel, and etch depth is to epitaxial substrate, and the son forming n independent extension ray structure is level led;
Three, evaporation extension insulating barrier in extension isolation channel;
Four, in extension insulating barrier, form the through hole for making conductive channel;
Five, at through hole and Second-Type conductive layer surface evaporation ITO material, form conductive channel and the 2nd ITO conductive layer; And form metallic reflector at the 2nd ITO conductive layer surface;
Six, in the technique of metallic reflector surface mask, photoetching and etching metal and ITO, form metal isolation channel on metal conducting layer surface, the degree of depth of metal isolation channel is to extension surface of insulating layer; Metal isolation channel between the adjacent each son of non-series connection is level led overlaps in the vertical direction of ray structure with the side of extension insulating barrier;
Seven, adopt non-conductive bonding material that metal conducting layer and substrate are bonded together, and non-conductive bonding material is full of metal isolation channel;
Eight, remove epitaxial substrate, the level led first type conductive layer level led to the n-th son of exposed first son, and the conductive channel in extension insulating barrier;
Nine, first type conductive layer adopts mask, photoetching process, expose the surface of the second light-emitting diode simultaneously, comprise the region adjacent with the first light-emitting diode, scope is until comprise conductive channel region in extension insulating barrier and the surface fair with conductive channel edge, according to this until expose the surface of the n-th light-emitting diode simultaneously, comprise the region adjacent with the (n-1)th light-emitting diode, scope is until comprise conductive channel region in extension insulating barrier and the surface fair with conductive channel edge;
Ten, evaporation ITO conductive layer on the exposed surface that each son is level led, make each son level led between extension insulating barrier in level led the first type conductive layer of conductive channel and son adjacent with it formed and be connected;
11, adopt mask, photoetching, ICP etching at the level led ITO conductive layer of the n-th son, form the making region of the second electrode, below etch depth to Second-Type conductive layer, do not reach the contact-making surface of Second-Type conductive layer and dielectric layer; The making region of level led the second electrode of the n-th son makes electrode isolation layers and the second electrode respectively;
12, the first type conductive layer that the first son is level led forms the first electrode;
13, surrounding's cutting splitting of a large module of level led for each son composition, form the high-voltage LED of described a kind of high-luminous-efficiency.
After adopting such scheme, the utility model is connected in series level led for the son of each independent ray structure, shape all-in-one-piece chip module, increases the area of active area bright dipping significantly, effectively improves the whole lighting efficiency of series connection light-emitting diode (LED) module.
Accompanying drawing explanation
Fig. 1 is the epitaxial structure schematic diagram of the utility model embodiment one;
Fig. 2 be each son of the utility model embodiment one level led between isolation channel schematic diagram;
Fig. 3 be each son of the utility model embodiment one level led between extension insulating barrier and dielectric layer schematic diagram;
Fig. 4 is the through hole schematic diagram that the utility model embodiment one makes extension insulating barrier and dielectric layer;
Fig. 5 is the level led making conductive channel of each son and the metallic mirror schematic diagram of the utility model embodiment one;
Fig. 6 is each son level led making metallic mirror isolation channel schematic diagram of the utility model embodiment one;
Fig. 7 is the level led metallic mirror isolation channel of each son of the utility model embodiment one and the plane distribution schematic diagram of extension insulating barrier conductive channel;
Fig. 8 is the light-emitting diode bonding substrate schematic diagram of the utility model embodiment one;
Fig. 9 is the light emitting diode construction schematic diagram that the utility model embodiment one removes epitaxial substrate;
Figure 10 is the schematic diagram of each son of the utility model embodiment one level led making ITO conductive layer;
Figure 11 is each son level led extension insulating barrier conductive channel of the utility model embodiment one and the plane distribution schematic diagram of ITO conductive layer;
Figure 12 is the side schematic view of the etching shape of the second electrode fabrication groove of the utility model embodiment one;
Figure 13 is the first electrode and the second electrode fabrication schematic diagram of the utility model embodiment one;
Figure 14 is the plane distribution schematic diagram of a large module of the level led formation of each son of the utility model embodiment one;
Figure 15 is the epitaxial structure schematic diagram of the utility model embodiment two;
Figure 16 be each son of the utility model embodiment two level led between the schematic diagram of isolation channel;
Figure 17 be each son of the utility model embodiment two level led between extension insulating barrier schematic diagram;
Figure 18 is the schematic diagram that the utility model embodiment two makes the through hole of extension insulating barrier;
Figure 19 is the schematic diagram of the level led making conductive channel of each son of the utility model embodiment two, the 2nd ITO conductive layer and metallic reflector;
Figure 20 is the schematic diagram of the level led making of each son the 2nd ITO conductive layer of the utility model embodiment two, the isolation channel of metallic reflector;
Figure 21 is the plane distribution schematic diagram of level led the 2nd ITO conductive layer, the isolation channel of metallic mirror and the conductive channel of extension insulating barrier of each son of the utility model embodiment two;
Figure 22 is the schematic diagram of the light-emitting diode bonding substrate of the utility model embodiment two;
Figure 23 is the light emitting diode construction schematic diagram after the utility model embodiment two peels off epitaxial substrate;
Figure 24 is the schematic diagram of the level led making of each son the one ITO conductive layer of the utility model embodiment two;
Figure 25 is the conductive channel of each sub-LED epitaxial insulating barrier of the utility model embodiment two and the plane distribution schematic diagram of an ITO conductive layer;
Figure 26 is the side schematic view of the etching shape of the second electrode fabrication groove of the utility model embodiment two;
Figure 27 is the first electrode and the second electrode fabrication schematic diagram of the utility model embodiment two;
Figure 28 is the plane distribution schematic diagram of a large module of the level led formation of each son of the utility model embodiment two.
Label declaration
Level led 10 first electrodes 20 of son
Second electrode 30 second electrode dielectric layer 301
Epitaxial substrate 40 resilient coating 50
Etch stop layers 60 extension isolation channel 70
Sacrifice layer 80
Active area 1
First type conductive layer 2 Second-Type conductive layer 3
Dielectric layer 4 conductive channel 41
Metallic reflector 5 metal isolation channel 51
Non-conductive bonded layer 6 substrate 7
ITO conductive layer 8 the one ITO conductive layer 81
2nd ITO conductive layer 82 extension insulating barrier 9
Conductive channel 91 through hole 92.
Embodiment
Below in conjunction with drawings and the specific embodiments, the utility model is described in detail.
Embodiment one
A kind of high-voltage LED of high-luminous-efficiency, the son level led 10 by 100 with independent ray structure is in series, and spread geometry is the matrix arrangement of 10*10, as shown in figure 14, first son level led 10 is arranged on the first electrode 20, n-th level led 10 and second electrode 30 is set.
As shown in figure 13, wherein each height level led 10 all comprises independently active area 1, and active area 1 first contact-making surface arranges the first type conductive layer 2, and active area 1 second contact-making surface arranges Second-Type conductive layer 3.First type conductive layer 2 is made up of the first type current extending and the first type limiting layer.Be specially the first type current extending by (Al
0.35ga
0.65)
0.5in
0.5p tri-or five compounds of group is formed, and thickness is 4 μm.First type limiting layer is by (Al
0.8ga
0.2)
0.5in
0.5p tri-or five compounds of group is formed, and thickness is 800nm.Active layer 1 is by 20 groups of (Al
0.8ga
0.2)
0.5in
0.5p/Ga
0.5in
0.5p tri-or five compounds of group is alternately formed.Second-Type conductive layer 3 is made up of Second-Type limiting layer and Second-Type current extending.Second-Type limiting layer is by (Al
0.8ga
0.2)
0.5in
0.5p tri-or five compounds of group is formed, and thickness is 800nm.Second-Type current extending is made up of GaP tri-or five compounds of group, and thickness is 4 μm.
First type current extending of the first son level led 10 arranges the first electrode 20, Second-Type conductive layer 3 arranges SiO
2dielectric layer 4, SiO
2the conductive channel 41, SiO of filling metal material is provided with in dielectric layer 4
2dielectric layer 4 is arranged metallic reflector 5, and metallic reflector 5 forms ohmic contact by conductive channel 41 and Second-Type current extending, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
First type current extending of the second son level led 10 arranges ITO conductive layer 8, Second-Type current extending arranges SiO
2dielectric layer 4, SiO
2the conductive channel 41, SiO of filling metal material is provided with in dielectric layer 4
2dielectric layer 4 is arranged metallic reflector 5, and metallic reflector 5 forms ohmic contact by conductive channel 41 and Second-Type current extending, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
SiO is provided with between second son level led 10 and the first son level led 10
2extension insulating barrier 9, and SiO
2be provided with in extension insulating barrier 9 and fill the conductive channel 91 of metal material, conductive channel 91 is formed with the metallic reflector 5 of the first son level led 10 and is connected, and is formed be connected with the ITO conductive layer 8 of second sub level led 10.
First type current extending of the 3rd son level led 10 arranges ITO conductive layer 5, Second-Type current extending arranges SiO
2dielectric layer 4, SiO
2the conductive channel 41, SiO of filling metal material is provided with in dielectric layer 4
2dielectric layer 4 is arranged metallic reflector 5, and metallic reflector 5 forms ohmic contact by conductive channel 41 and Second-Type current extending, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
SiO is provided with between 3rd son level led 10 and the second son level led 10
2extension insulating barrier 9, and SiO
2be provided with in extension insulating barrier 9 and fill the conductive channel 91 of metal material, conductive channel 91 is formed with the metallic reflector 5 of the second son level led 10 and is connected, and is formed be connected with the ITO conductive layer 8 of the 3rd sub level led 10.
The chip structure connected mode of two sons level led 10 described in circulation is to the 99 son level led 10.
The first type current extending of the first the ancient philosophers level led 10 arranges ITO conductive layer 8, Second-Type current extending arranges SiO
2dielectric layer 4, SiO
2the conductive channel 41, SiO of filling metal material is provided with in dielectric layer 4
2dielectric layer 4 is arranged metallic reflector 5, and metallic reflector 5 forms ohmic contact by conductive channel 41 and Second-Type current extending, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7; Second-Type current extending and active area 1 adjacent surface are provided with the second electrode 30, and the second electrode 30 is separated with extension ray structure by the second electrode dielectric layer 301.
SiO is provided with between first the ancient philosophers the level led 10 and the 99 level led 10
2extension insulating barrier 9, and SiO
2be provided with in extension insulating barrier 9 and fill the conductive channel 91 of metal material, conductive channel 91 with the 99 sub level led 10 metallic reflector 5 formed and be connected, and formed with the ITO conductive layer 8 of the first the ancient philosophers level led 10 and be connected.
The high-voltage LED manufacture method of described a kind of high-luminous-efficiency, mainly comprises the following steps:
One, as shown in Figure 1, the upper surface extension successively from the bottom to top in epitaxial substrate 40: resilient coating 50, etch stop layers 60, first type conductive layer 2, active area 1, Second-Type conductive layer 3.
Epitaxial substrate 40 adopts the GaAs substrate of 2 inches, and thickness is 270 μm.Resilient coating 50 is made up of the GaAs material of 300nm.Etch stop layers 60 is by the thick (Al of 300nm
0.7ga
0.3)
0.5in
0.5p material forms.
Two, as shown in Figure 2, the Second-Type conductive layer 3 on the epitaxial wafer surface of 2 inches adopts mask, ICP etches, the extension isolation channel 70 that width is 4 μm is formed at each son of non-series connection level led 10, forming width at each son of series connection level led 10 is 20 μm of extension isolation channels 70, and etch depth is to etch stop layers 60, forms the independent extension ray structure of several ten thousand 10mil*10mil sizes.
Three, as shown in Figure 3, evaporation SiO in extension isolation channel 70
2form extension insulating barrier 9, simultaneously at the surperficial evaporation SiO of Second-Type conductive layer 3
2form dielectric layer 4.
Four, as shown in Figure 4, it is 300/mm that the extension insulating barrier 9 of 20 μm wide between each son level led 10 of series connection forms density
2, diameter is the extension insulating barrier through hole 92 of the circle of 4 μm; And simultaneously to form density in dielectric layer 4 be 150/mm
2, diameter is the dielectric layer through hole 42 of the circle of 10 μm.
Five, as shown in Figure 5, at extension insulating barrier through hole 92, dielectric layer through hole 42 and the surperficial evaporation metal of dielectric layer 4, metal filled full extension insulating barrier through hole 92, dielectric layer through hole 42, form conductive channel (91,41); And form the thick metallic reflector 5 of 400nm; Thicken metallic reflector 5 to 1 μm thicker, make metallic reflector 5 form good conductive effect.
Six, as shown in Figure 6, in the surperficial mask of metallic reflector 5, photoetching and etching metal technique, at the metal isolation channel 51 of the surperficial formation rule of metallic reflector 5, the width size of metal isolation channel 51 is 4 μm, and the degree of depth of metal isolation channel 51 is to dielectric layer 4 surface; Metal isolation channel 51 between the adjacent each son of non-series connection level led 10 overlaps in the vertical direction of ray structure with extension insulating barrier 9; Metal isolation channel 51 between each son of adjacent series connection level led 10 staggers with extension insulating barrier 9 conductive channel 91, and with monolateral extension insulating barrier 9 in the vertical direction of ray structure, overlap, form metal isolation channel 51 distribution situation as shown in Figure 7.
Seven, as shown in Figure 8, adopt non-conductive bonding material that metallic reflector 5 and silicon substrate 7 are bonded together, and form non-conductive bonded layer 6, non-conductive bonded layer 6 is full of metal isolation channel 51 and forms insulation.
Eight, as shown in Figure 9, erosion removal epitaxial substrate 40, resilient coating 50 and etch stop layers 60, expose the first type conductive layer 2 respectively.
Nine, on the first type conductive layer 2 after mask, photoetching process, expose the first type conductive layer 2 on the second level led 10 surfaces of son, comprise and the first level led 10 adjacent regions of son, scope is to comprising conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge; Expose the level led 10 surperficial first type conductive layers 2 of the 3rd son simultaneously, comprise and the second level led 10 adjacent regions of son, scope is to comprising conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge, successively until expose the level led 10 surperficial first type conductive layers 2 of the first the ancient philosophers simultaneously, comprise and the 99 level led 10 adjacent regions of son, until comprise conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge.
Ten, as shown in Figures 10 and 11, at level led 10 exposed the first type conductive layer 2 evaporation ITO conductive layers 8 on the surface of each son, conductive channel 91 in the extension insulating barrier 9 between each son level led 10 is formed with the level led 10 first type conductive layers 2 of son adjacent with it and is connected.
11, as shown in figure 12, adopt mask, photoetching, ICP etching at the ITO conductive layer 8 of the first the ancient philosophers level led 10, form the making region of the second electrode 30, below etch depth to Second-Type current extending 2 μm.
12, as shown in figure 13, make on region at second electrode 30 of the first the ancient philosophers level led 10 and make the second electrode dielectric layer 301 and the second electrode 30 respectively.
13, as shown in figure 13, the first type current extending of the first son level led 10 forms the first electrode 20.
14, as shown in figure 14, surrounding's cutting splitting of a large module of 100 level led 10 compositions of son, form the high-voltage LED of described high-luminous-efficiency.
Embodiment two
A high-voltage LED for high-luminous-efficiency, the son level led 10 by 72 with independent ray structure is in series, and spread geometry is the matrix arrangement of 8*9, as shown in figure 28.
As shown in figure 27, wherein each height level led 10 all comprises independently active area 1, and active area 1 first contact-making surface arranges the first type conductive layer 2, and active area 1 second contact-making surface arranges Second-Type conductive layer 3.GaN tri-or five compounds of group that first type conductive layer 2 adopts Si to adulterate, thickness is 2.5 μm.Active layer 1 adopts 5 pairs of quantum well and quantum to build the structure of intersecting and growing.Be specially quantum base to be made up of AlGaN tri-or five compounds of group, thickness is 12nm.Quantum well is made up of GaInN tri-or five compounds of group, and thickness is 4nm.GaN tri-or five compounds of group that Second-Type conductive layer 3 adopts Mg to adulterate, thickness is 200nm.
First type conductive layer 2 of the first son level led 10 arranges the first electrode 20, Second-Type conductive layer 3 is arranged the 2nd ITO conductive layer 82,2nd ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
First type conductive layer 2 of the second son level led 10 arranges an ITO conductive layer 81, Second-Type conductive layer 3 is arranged the 2nd ITO conductive layer 82,2nd ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
SiO is provided with between second son level led 10 and the first son level led 10
2extension insulating barrier 9, and SiO
2be provided with the conductive channel 91 of filling full metal in extension insulating barrier 9, conductive channel 91 is formed with the 2nd ITO conductive layer 82 of the first son level led 10 and is connected, and is formed be connected with an ITO conductive layer 81 of second sub level led 10.
First type conductive layer 2 of the 3rd son level led 10 arranges an ITO conductive layer 81, Second-Type conductive layer 3 is arranged the 2nd ITO conductive layer 82,2nd ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7.
SiO is provided with between 3rd son level led 10 and the second son level led 10
2extension insulating barrier 9, and SiO
2be provided with the conductive channel 91 of filling full metal in extension insulating barrier 9, conductive channel 91 is formed with the 2nd ITO conductive layer 82 of the second son level led 10 and is connected, and is formed be connected with an ITO conductive layer 81 of the 3rd sub level led 10.
Circulate described son level led 10 chip structure connected mode to the 71 son level led 10.
First type conductive layer 2 of the 72 son level led 10 arranges an ITO conductive layer 81, Second-Type conductive layer 3 is arranged the 2nd ITO conductive layer 82,2nd ITO conductive layer 82 arranges metallic reflector 5, metallic reflector 5 arranges non-conductive bonded layer 6, non-conductive bonded layer 6 arranges silicon substrate 7; 2nd ITO conductive layer 82 and the phase-contact surface of Second-Type conductive layer 3 are provided with the second electrode 30, and the second electrode 30 passes through SiO
2second electrode dielectric layer 301 separates with extension ray structure.
SiO is provided with between 72 son the level led 10 and the 71 son level led 10
2extension insulating barrier 9, and SiO
2be provided with the conductive channel 91 of filling full metal in extension insulating barrier 9, conductive channel 91 is formed with the 2nd ITO conductive layer 82 of the 71 son level led 10 and is connected, and is formed be connected with an ITO conductive layer 81 of the 72 sub level led 10.
The high-voltage LED manufacture method of described a kind of high-luminous-efficiency, mainly comprises the following steps:
One, as shown in figure 15, the upper surface extension successively from the bottom to top in epitaxial substrate 40: resilient coating 50, sacrifice layer 80, first type conductive layer 2, active area 1, Second-Type conductive layer 3.
Be specially the Sapphire Substrate that epitaxial substrate 40 adopts 4 inches, thickness is 400 μm.Resilient coating 50 adopts undoped GaN tri-or five compounds of group, and thickness is 2 μm.
Two, as shown in figure 16, the Second-Type conductive layer 3 on the epitaxial wafer surface of 4 inches adopts mask, ICP etches, form extension isolation channel 70, extension isolation channel 70 is 3 μm at level led 10 width of each son of non-series connection, and it is 24 μm that extension isolation channel 70 forms width at each son of series connection level led 10, and etch depth is to sacrifice layer 80, form the independent extension ray structure of several ten thousand 10mil*10mil sizes.
Three, as shown in figure 17, evaporation SiO in extension isolation channel 70
2material, forms extension insulating barrier 9.
Four, as shown in figure 18, forming density at extension insulating barrier 9 is 200/mm
2, diameter is the through hole 92 of the circle of 8 μm.
Five, as shown in figure 19, at through hole 92 and Second-Type conductive layer 3 surperficial evaporation ITO material, form conductive channel 91 and the 2nd ITO conductive layer 82; And form metallic reflector 5 on the 2nd ITO conductive layer 82 surface.
Six, as shown in figure 20, on metallic reflector 5 surface through the technique of mask, photoetching and etching metal, ITO, at the metal isolation channel 51 of the surperficial formation rule of metallic reflector 5, the width size of metal isolation channel 51 is 4 μm, and the degree of depth of metal isolation channel 51 is to extension insulating barrier 9 surface; Metal isolation channel 51 between the adjacent each son of non-series connection level led 10 overlaps in the vertical direction of ray structure with extension insulating barrier 9; Metal isolation channel 51 between each son of adjacent series connection level led 10 staggers with conductive channel 91, and overlaps in the vertical direction of ray structure with monolateral extension insulating barrier 9, forms metal isolation channel 51 distribution situation as shown in figure 21.
Seven, as shown in figure 22, adopt non-conductive bonding material that metallic reflector 5 and silicon substrate 7 are bonded together, and form non-conductive bonded layer 6, non-conductive bonded layer 6 is full of metal isolation channel 51 and forms insulation.
Eight, as shown in figure 23, adopt laser lift-off technique to remove epitaxial substrate 40, resilient coating 50 and sacrifice layer 80, expose the first type conductive layer 2.
Nine, first type conductive layer 2 adopts mask, photoetching process, expose the surface of the second light-emitting diode 10 first type conductive layer 2, comprise the region adjacent with the first light-emitting diode 10, scope is to comprising conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge; Expose the surface of the 3rd light-emitting diode 10 first type conductive layer 2 simultaneously, comprise the region adjacent with the second light-emitting diode 10, scope is until comprise conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge, successively until expose the surface of the 72 light-emitting diode 10 first type conductive layer 2 simultaneously, comprise the region adjacent with the 71 light-emitting diode 10, scope is until comprise conductive channel 91 region in extension insulating barrier 9, and the surface fair with conductive channel 91 edge.
Ten, as shown in Figure 24 and Figure 25, at the first exposed type conductive layer 2 evaporation the one ITO conductive layer 81 on the surface of each son level led 10, conductive channel 91 in the extension insulating barrier 9 between each son level led 10 is formed with single first type conductive layer 2 adjacent with it and is connected.
11, as shown in figure 26, adopt mask, photoetching, ICP etching, form the second electrode 30 and make region at an ITO conductive layer 81 of the 72 son level led 10, etch depth is to the contact-making surface of the 2nd ITO conductive layer 82 with Second-Type conductive layer 3.
12, as shown in figure 27, make on region at the second electrode 30 of the 72 son level led 10 and make the second electrode dielectric layer 301 and the second electrode 30 respectively.
13, as shown in figure 27, the first type conductive layer 2 of the first son level led 10 forms the first electrode 20.
14, as shown in figure 28, surrounding's cutting splitting of a large module of 72 level led 10 compositions of son, the high-voltage LED of the high-luminous-efficiency described in formation.
The foregoing is only preferred embodiment of the present utility model, not to the restriction of this case design, all equivalent variations done according to the design key of this case, all fall into the protection range of this case.
Claims (10)
1. a high-voltage LED for high-luminous-efficiency, is characterized in that: the son by n with independent ray structure is level led in series, and wherein, each son is level led all comprises independently active area and separated from each other by extension insulating barrier; Active area first contact-making surface is arranged the first type conductive layer, active area second contact-making surface arranges Second-Type conductive layer;
The first type conductive layer that first son is level led arranges the first electrode, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, and metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
The first type conductive layer that second son is level led arranges ITO conductive layer, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
Second son level led and first son level led between extension insulating barrier is set, and in extension insulating barrier, conductive channel is set, conductive channel is formed with the first son level led metallic reflector and is connected, and is formed with the second sub level led ITO conductive layer and be connected;
The first type conductive layer that 3rd son is level led arranges ITO conductive layer, Second-Type conductive layer arranges dielectric layer, in dielectric layer, conductive channel is set, dielectric layer arranges metallic reflector, metallic reflector forms ohmic contact by conductive channel and Second-Type conductive layer, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate; Be sequentially connected in series the ITO conductive layer arranged to the level led first type conductive layer of the n-th son, Second-Type conductive layer is arranged the second electrode, and the second electrode separated with extension ray structure lateral side regions by the second electrode dielectric layer.
2. a high-voltage LED for high-luminous-efficiency, is characterized in that: the son by n with independent ray structure is level led in series, and wherein, each son is level led all comprises independently active area and separated from each other by extension insulating barrier; Active area first contact-making surface is arranged the first type conductive layer, active area second contact-making surface arranges Second-Type conductive layer;
The first type conductive layer that first son is level led arranges the first electrode, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
The first level led type conductive layer of second son arranges an ITO conductive layer, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector is arranged non-conductive bonded layer, non-conductive bonded layer arranges substrate;
Second son level led and first son level led between extension insulating barrier is set, and in extension insulating barrier, conductive channel is set, conductive channel is formed with the first son level led the 2nd ITO conductive layer and is connected, and is formed with the second sub level led ITO conductive layer and be connected;
The first type conductive layer that 3rd son is level led arranges an ITO conductive layer, Second-Type conductive layer is arranged the 2nd ITO conductive layer, 2nd ITO conductive layer arranges metallic reflector, metallic reflector arranges non-conductive bonded layer, non-conductive bonded layer arranges substrate; Be sequentially connected in series the ITO conductive layer arranged to the level led first type conductive layer of the n-th son; 2nd ITO conductive layer arranges the second electrode, and the second electrode is separated with extension ray structure lateral side regions by the second electrode dielectric layer.
3. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, is characterized in that: the level led number n of son is 2-220.
4. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, is characterized in that: the level led shared non-conductive bonded layer of each son is same layer functional structure, and the level led common substrate of each son is same supporter.
5. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, is characterized in that: between each son is level led, extension dielectric width d is 2 μm≤d≤100 μm.
6. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, is characterized in that: the extension insulating barrier conductive channel arranged between each son is level led is regularly arranged, and its arranging density D is 1≤D≤800/mm
2.
7. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, it is characterized in that: between each son is level led, the figure of extension insulating barrier conductive channel comprises circle, square, triangular form, ellipse, rectangle or trapezoidal, and the length of side of single extension insulating barrier conductive channel or diameter d are 1≤d≤200 μm.
8. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1 or 2, is characterized in that: n series connection the level led spread geometry of son comprise 2*(n/2) matrix, 3*(n/3) matrix, 4*(n/4) matrix, 5*(n/5) matrix; Also non-matrix L-type, П type, Ш type is comprised.
9. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 1, is characterized in that: level led adjacent of each son and non-connected each independently between metallic reflector across non-conductive bonding material.
10. the high-voltage LED of a kind of high-luminous-efficiency as claimed in claim 2, is characterized in that: level led adjacent of each son and non-connected each independently between the 2nd ITO conductive layer across non-conductive bonding material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420699609.8U CN204243043U (en) | 2014-11-20 | 2014-11-20 | A kind of high-voltage LED of high-luminous-efficiency |
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| CN201420699609.8U CN204243043U (en) | 2014-11-20 | 2014-11-20 | A kind of high-voltage LED of high-luminous-efficiency |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377219A (en) * | 2014-11-20 | 2015-02-25 | 厦门乾照光电股份有限公司 | High-voltage LED with high light-emitting efficiency |
| WO2017185775A1 (en) * | 2016-04-27 | 2017-11-02 | 天津三安光电有限公司 | Light-emitting diode and manufacturing method therefor |
| WO2023136991A1 (en) * | 2022-01-13 | 2023-07-20 | Nanosys, Inc. | Light emitting diodes and method of making thereof by selectively growing active layers from trench separated areas |
-
2014
- 2014-11-20 CN CN201420699609.8U patent/CN204243043U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377219A (en) * | 2014-11-20 | 2015-02-25 | 厦门乾照光电股份有限公司 | High-voltage LED with high light-emitting efficiency |
| CN104377219B (en) * | 2014-11-20 | 2017-03-29 | 厦门乾照光电股份有限公司 | A kind of high-voltage LED of high-luminous-efficiency |
| WO2017185775A1 (en) * | 2016-04-27 | 2017-11-02 | 天津三安光电有限公司 | Light-emitting diode and manufacturing method therefor |
| WO2023136991A1 (en) * | 2022-01-13 | 2023-07-20 | Nanosys, Inc. | Light emitting diodes and method of making thereof by selectively growing active layers from trench separated areas |
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