CN104363010B - A kind of current-limiting protection circuit of open-drain output - Google Patents
A kind of current-limiting protection circuit of open-drain output Download PDFInfo
- Publication number
- CN104363010B CN104363010B CN201410625615.3A CN201410625615A CN104363010B CN 104363010 B CN104363010 B CN 104363010B CN 201410625615 A CN201410625615 A CN 201410625615A CN 104363010 B CN104363010 B CN 104363010B
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- drain terminal
- source
- output
- phase inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to analog power technical field,Specially a kind of current-limiting protection circuit of open-drain output,It can prevent the risk that the short circuit of output end and power supply causes chip reliability to decline,Eliminate potential safety hazard when using,It includes phase inverter I1 and the first NMOS tube N1,Phase inverter I1 input is driving input IN,Phase inverter I1 output end connects the first NMOS tube N1 grid end,First NMOS tube N1 source ground connection,It is characterized in that,It also includes the second NMOS tube N2,3rd NMOS tube N3,4th NMOS tube N4,Bias current Ibiasp,First NMOS tube N1 drain terminal connects the second NMOS tube N2 source,3rd NMOS tube N3 grid end,The N2 of second NMOS tube drain terminal is drive output OUT,Second NMOS tube N2 grid end connects the 4th NMOS tube N4 grid end and drain terminal,Bias current Ibiasp one end,Bias current Ibiasp other ends connection power vd D,4th NMOS tube N4 source connects the 3rd NMOS tube N3 drain terminal,3rd NMOS tube N3 source ground connection.
Description
Technical field
The present invention relates to analog power technical field, specially a kind of current-limiting protection circuit of open-drain output.
Background technology
For common open-drain output circuit as shown in figure 1, driving tube N1 is operated in linear zone, electric current is linear with output end OUT
Increase, open-drain output need outside to connect puller circuit, load the driving force, it is necessary to larger for adaptation is various, but protect in output
Problem is there is in shield, the output end OUT of the open-drain output circuit and the VDD of power supply have short-circuit possibility, cause chip can
Decline by property, there is certain potential safety hazard during use.
The content of the invention
In order to solve the above problems, the present invention is provided and sees a kind of current-limiting protection circuit of open-drain output, and it can be prevented
The short circuit of output end and power supply causes the risk that chip reliability declines, and eliminates potential safety hazard when using.
Its technical scheme is such：A kind of current-limiting protection circuit of open-drain output, it includes phase inverter I1 and first
NMOS tube N1, the phase inverter I1 input connect described first for driving input IN, the phase inverter I1 output end
NMOS tube N1 grid end, the source ground connection of the first NMOS tube N1, it is characterised in that it also includes the second NMOS tube N2, the
Three NMOS tube N3, the 4th NMOS tube N4, bias current Ibiasp, the drain terminal of the first NMOS tube N1 connect the 2nd NMOS
The grid end of pipe N2 source, the 3rd NMOS tube N3, the N2 of second NMOS tube drain terminal are drive output OUT, described the
Two NMOS tube N2 grid end connects grid end and drain terminal, bias current Ibiasp one end of the 4th NMOS tube N4, the biasing
The electric current Ibiasp other ends connection power vd D, the 4th NMOS tube N4 source connect the drain terminal of the 3rd NMOS tube N3,
The source ground connection of the 3rd NMOS tube N3.
It is further characterized by, and sets PMOS P1, the PMOS P1 grid end to connect at the driving input IN
The input of the phase inverter I1 is connect, the source of the PMOS P1 connects the drain terminal of the 4th NMOS tube N4, the PMOS
Pipe P1 drain terminal connects described bias current Ibiasp one end.
After structure using the present invention, meeting clamper is lived after output current increases to certain value, prevents output end and power supply
Short circuit cause chip reliability decline risk, eliminate use when potential safety hazard.
Brief description of the drawings
Fig. 1 is prior art circuits schematic diagram；
Fig. 2 is circuit diagram of the present invention；
Fig. 3 is circuit diagram after present invention addition PMOS；
Fig. 4 graphs of a relation of electric current and source-drain voltage between source and drain.
Embodiment
As shown in Figure 2, a kind of current-limiting protection circuit of open-drain output, it includes phase inverter I1 and the first NMOS tube N1, instead
Phase device I1 input connects the first NMOS tube N1 grid end, the first NMOS for driving input IN, phase inverter I1 output end
Pipe N1 source ground connection, it is characterised in that it also includes the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, biasing
Electric current Ibiasp, the first NMOS tube N1 the second NMOS tube N2 of drain terminal connection source, the 3rd NMOS tube N3 grid end, second
The N2 of NMOS tube drain terminal is that drive output OUT, the second NMOS tube N2 grid end connect the 4th NMOS tube N4 grid end and leakage
End, bias current Ibiasp one end, the bias current Ibiasp other ends connection power vd D, the 4th NMOS tube N4 source connection
3rd NMOS tube N3 drain terminal, the 3rd NMOS tube N3 source ground connection.
Circuit operation principle is as described below：When it is low level to drive input IN, by phase inverter I1 to the first NMOS
Pipe N1 grid end voltage is high level, and the first NMOS tube N1 is opened, and now drive output OUT such as outside pull-up abilities are stronger,
First NMOS tube N1 just has larger electric current, when threshold value electricity of the first NMOS tube N1 output voltage higher than the 3rd NMOS tube N3
The 3rd NMOS tube N3 will be opened during pressure, so that the 4th NMOS tube N4 pipes are also opened, the grid end of the 4th NMOS tube N4 pipes and leakage
The connected node voltage in end declines, and causes the second NMOS tube N2 pipes to enter saturation region from linear zone, the second NMOS tube N2 pipes
Source voltage terminal, which rises, will be limited to output current ability, so as to reach the stable operating point of a balance；As driving input IN
For high level when, the first NMOS tube N1 grid ends voltage is low level, the first NMOS tube normal turn-off.
It is that high level closes when being the first NMOS tube N1 shut-offs driving input IN as shown in figure 3, adding PMOS P1
Branch road where falling bias current Ibiasp, saves power consumption.
As shown in figure 4, electric current and source between the first NMOS tube N1 source and drain of in general open-drain output circuit in the prior art
Between leakage the output characteristics of voltage and the present invention the first NMOS tube N1 source and drain between the output characteristics of electric current and source-drain voltage pass
System's figure, it can be seen that after the circuit using the present invention, with the rise of source-drain voltage, source-drain voltage inconvenience, reach one
The stable operating point of balance.
Claims (1)
1. a kind of current-limiting protection circuit of open-drain output, it includes phase inverter I1 and the first NMOS tube N1, the phase inverter I1's
Input connects the grid end of the first NMOS tube N1 for driving input IN, phase inverter I1 output end, and described first
NMOS tube N1 source ground connection, it is characterised in that its also include the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4,
Bias current Ibiasp, the first NMOS tube N1 drain terminal connect the source of the second NMOS tube N2, the 3rd NMOS tube N3
Grid end, the N2 of second NMOS tube drain terminal is described in drive output OUT, the second NMOS tube N2 grid end connection
4th NMOS tube N4 grid end and drain terminal, bias current Ibiasp one end, the bias current Ibiasp other ends connect power supply
VDD, the 4th NMOS tube N4 source connect the drain terminal of the 3rd NMOS tube N3, and the source of the 3rd NMOS tube N3 connects
Ground；PMOS P1, the PMOS P1 grid end is set to connect the input of the phase inverter I1 at the driving input IN
End, the source of the PMOS P1 connect the drain terminal of the 4th NMOS tube N4, and the drain terminal connection of the PMOS P1 is described partially
Put electric current Ibiasp one end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410625615.3A CN104363010B (en) | 2014-11-10 | 2014-11-10 | A kind of current-limiting protection circuit of open-drain output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410625615.3A CN104363010B (en) | 2014-11-10 | 2014-11-10 | A kind of current-limiting protection circuit of open-drain output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104363010A CN104363010A (en) | 2015-02-18 |
| CN104363010B true CN104363010B (en) | 2017-11-24 |
Family
ID=52530241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410625615.3A Active CN104363010B (en) | 2014-11-10 | 2014-11-10 | A kind of current-limiting protection circuit of open-drain output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104363010B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222236B1 (en) * | 1999-04-30 | 2001-04-24 | Motorola, Inc. | Protection circuit and method for protecting a semiconductor device |
| CN100559715C (en) * | 2006-12-15 | 2009-11-11 | 烟台英迈格科技发展有限公司 | Short circuit, the overload protection arrangement of transistor output |
| CN103178701A (en) * | 2011-12-23 | 2013-06-26 | 国民技术股份有限公司 | Current-limiting device and current-limiting method |
| CN103488235A (en) * | 2013-09-25 | 2014-01-01 | 无锡中星微电子有限公司 | Current limiting circuit, voltage regulator and direct current-direct current (DC-DC) convertor |
-
2014
- 2014-11-10 CN CN201410625615.3A patent/CN104363010B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222236B1 (en) * | 1999-04-30 | 2001-04-24 | Motorola, Inc. | Protection circuit and method for protecting a semiconductor device |
| CN100559715C (en) * | 2006-12-15 | 2009-11-11 | 烟台英迈格科技发展有限公司 | Short circuit, the overload protection arrangement of transistor output |
| CN103178701A (en) * | 2011-12-23 | 2013-06-26 | 国民技术股份有限公司 | Current-limiting device and current-limiting method |
| CN103488235A (en) * | 2013-09-25 | 2014-01-01 | 无锡中星微电子有限公司 | Current limiting circuit, voltage regulator and direct current-direct current (DC-DC) convertor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104363010A (en) | 2015-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103647545A (en) | Delay unit circuit | |
| CN104137418B (en) | On-off circuit | |
| CN105577153A (en) | Semiconductor device | |
| CN105938815A (en) | Electrostatic protection circuit | |
| CN104135237B (en) | Gate driving circuit | |
| CN103141028A (en) | Level shift circuit | |
| WO2020113175A3 (en) | Cmos rf power limiter and esd protection circuits | |
| CN208939912U (en) | Control circuit | |
| CN105957863A (en) | Electrostatic protection circuit | |
| CN107004638A (en) | Semiconductor integrated circuit | |
| CN105703761B (en) | Input/output driving circuit | |
| CN102185286A (en) | High-power insulated gate bipolar transistor (IGBT) redundancy driving protection circuit | |
| CN106899011B (en) | Electrostatic discharge protective circuit | |
| CN107251434A (en) | The output driver prevented with reverse power supply | |
| CN104363010B (en) | A kind of current-limiting protection circuit of open-drain output | |
| US9859704B2 (en) | Node isolation for protection from electrostatic discharge (ESD) damage | |
| CN104883172A (en) | Analog switch circuit structure | |
| CN107579064A (en) | A kind of stacked ESD protection circuit | |
| CN208723866U (en) | A kind of power-down protection circuit for CMOS output | |
| CN102437558B (en) | Esd protection circuit | |
| CN103383579B (en) | Reference voltage source | |
| CN103795396A (en) | Circuit structure for eliminating short circuit currents | |
| CN103312137A (en) | Power-on overshoot suppression circuit applied to linear regulator | |
| CN103268133A (en) | Multi-working-voltage input-output pin unit circuit | |
| CN202435378U (en) | Bus interface output stage driver circuit with over-voltage, under-voltage and over-current protection functions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190111 Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Patentee after: Pu ran semiconductor (Shanghai) Co., Ltd. Address before: 214101 Ruiyun 716, 99 Furong Zhongsan Road, Xishan District, Wuxi City, Jiangsu Province Patentee before: Wuxi Puya Semiconductor Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Patentee after: Praran semiconductor (Shanghai) Co., Ltd Address before: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Patentee before: PUYA SEMICONDUCTOR (SHANGHAI) Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |