CN104363010A

CN104363010A - Open-drain output type current-limiting protection circuit

Info

Publication number: CN104363010A
Application number: CN201410625615.3A
Authority: CN
Inventors: 李兆桂
Original assignee: WUXI PUYA SEMICONDUCTOR CO Ltd
Current assignee: Praran semiconductor (Shanghai) Co., Ltd
Priority date: 2014-11-10
Filing date: 2014-11-10
Publication date: 2015-02-18
Anticipated expiration: 2034-11-10
Also published as: CN104363010B

Abstract

The invention relates to the technical field of simulation power supply, particularly to an open-drain output type current-limiting protection circuit. The open-drain output type current-limiting protection circuit has the advantages that the risk that short circuit occurs to an output end and a power supply so as to cause reliability of a chip to decrease is prevented, and potential safety hazard during utilization is eliminated. The open-drain output type current-limiting protection circuit comprises an inverter I1 and a first NMOS (n-channel metal oxide semiconductor) pipe N1. An input end of the inverter I1 is an input end IN. An output end of the inverter I1 is connected with a gate end of the first NMOS pipe N1. A source end of the first NMSO pipe N1 is grounded. The open-drain output type current-limiting protection circuit is characterized by further comprising a second NMOS pipe N2, a third NMOS pipe N3, a fourth NMOS pipe N4 and a bias current Ibiasp; a drain end of the first NMOS pipe N1 is connected with a source end of the second NMOS pipe N2 and a gate end of a third NMOS pipe N3; a drain end of the second NMOS pipe N2 is a drive output end OUT; a gate end of the second NMOS pipe N2 is connected with a gate end and a drain end of the fourth NMOS pipe N4 and one end of the bias current Ibiasp, and the other end of the bias current Ibiasp is connected with a power supply VDD; a source end of the fourth NMOS pipe N4 is connected with a drain end of the third NMOS pipe N3, and a source end of the third NMOS pipe N3 is grounded.

Description

A kind of current-limiting protection circuit opening Lou output

Technical field

The present invention relates to analog power technical field, be specially a kind of current-limiting protection circuit opening Lou output.

Background technology

Commonly open Lou that output circuit is as shown in Figure 1; driving tube N1 is operated in linear zone; electric current linearly increases with output OUT; opening Lou to export needs outside to connect puller circuit, for adapting to various load, needs larger driving force; but just have problems on output protection; the VDD of this output OUT and power supply of driving Lou output circuit has the possibility of short circuit, causes chip reliability to decline, has certain potential safety hazard in use procedure.

Summary of the invention

In order to solve the problem, the invention provides and see and a kind ofly open the current-limiting protection circuit Lou exported, its risk that the short circuit of output and power supply can be prevented to cause chip reliability declines, potential safety hazard during elimination use.

Its technical scheme is such: a kind of current-limiting protection circuit opening Lou output, it comprises inverter I1 and the first NMOS tube N1, the input of described reverser I1 is for driving input IN, the output of described inverter I1 connects the grid end of described first NMOS tube N1, the source ground connection of described first NMOS tube N1, it is characterized in that, it also comprises the second NMOS tube N2, 3rd NMOS tube N3, 4th NMOS tube N4, bias current Ibiasp, the drain terminal of described first NMOS tube N1 connects the source of described second NMOS tube N2, the grid end of the 3rd NMOS tube N3, the drain terminal of the N2 of described second NMOS tube is drive output OUT, the grid end of described second NMOS tube N2 connects grid end and the drain terminal of described 4th NMOS tube N4, bias current Ibiasp one end, the described bias current Ibiasp other end connects power vd D, the source of described 4th NMOS tube N4 connects the drain terminal of described 3rd NMOS tube N3, the source ground connection of described 3rd NMOS tube N3.

It is further characterized in that, described driving input IN place arranges PMOS P1, the grid end of described PMOS P1 connects the input of described reverser I1, the source of described PMOS P1 connects the drain terminal of described 4th NMOS tube N4, and the drain terminal of described PMOS P1 connects described bias current Ibiasp one end.

After adopting structure of the present invention, output current is increased to after certain value clamper to live, the risk preventing the short circuit of output and power supply to cause chip reliability to decline, potential safety hazard during elimination use.

Accompanying drawing explanation

Fig. 1 is prior art circuits schematic diagram;

Fig. 2 is circuit diagram of the present invention;

Fig. 3 is that the present invention adds circuit diagram after PMOS;

Fig. 4 is the graph of a relation of electric current and source-drain voltage between source and drain.

Embodiment

As shown in Figure 2, a kind of current-limiting protection circuit opening Lou output, it comprises inverter I1 and the first NMOS tube N1, the input of reverser I1 is for driving input IN, the output of inverter I1 connects the grid end of the first NMOS tube N1, the source ground connection of the first NMOS tube N1, it is characterized in that, it also comprises the second NMOS tube N2, 3rd NMOS tube N3, 4th NMOS tube N4, bias current Ibiasp, the drain terminal of the first NMOS tube N1 connects the source of the second NMOS tube N2, the grid end of the 3rd NMOS tube N3, the drain terminal of the N2 of the second NMOS tube is drive output OUT, the grid end of the second NMOS tube N2 connects grid end and the drain terminal of the 4th NMOS tube N4, bias current Ibiasp one end, the bias current Ibiasp other end connects power vd D, the source of the 4th NMOS tube N4 connects the drain terminal of the 3rd NMOS tube N3, the source ground connection of the 3rd NMOS tube N3.

Circuit working principle is as described below: when driving input IN to be low level, grid terminal voltage through inverter I1 to the first NMOS tube N1 is high level, first NMOS tube N1 opens, now drive output OUT is as stronger in outside pull-up ability, first NMOS tube N1 just has larger electric current, when threshold voltage higher than the 3rd NMOS tube N3 of the output voltage of the first NMOS tube N1, the 3rd NMOS tube N3 will open, thus the 4th NMOS tube N4 pipe is also opened, the node voltage that the grid end of the 4th NMOS tube N4 pipe is connected with drain terminal declines, the second NMOS tube N2 pipe is caused to enter into saturation region from linear zone, the source voltage terminal of the second NMOS tube N2 pipe rises and will be restricted to output current ability, thus reach the stable operating point of a balance, when driving input IN to be high level, the first NMOS tube N1 grid terminal voltage is low level, the first NMOS tube normal turn-off.

As shown in Figure 3, add PMOS P1, being that high level turns off bias current Ibiasp place branch road when that is the first NMOS tube N1 turns off driving input IN, saving power consumption.

As shown in Figure 4, for the graph of a relation of the output characteristic of electric current and source-drain voltage between the output characteristic of electric current and source-drain voltage between the first NMOS tube N1 source and drain driving Lou output circuit general in prior art and the first NMOS tube N1 source and drain of the present invention, can find out after adopting circuit of the present invention, along with the rising of source-drain voltage, source-drain voltage inconvenience, reaches the stable operating point of a balance.

Claims

1. open the current-limiting protection circuit Lou exported for one kind, it comprises inverter I1 and the first NMOS tube N1, the input of described reverser I1 is for driving input IN, the output of described inverter I1 connects the grid end of described first NMOS tube N1, the source ground connection of described first NMOS tube N1, it is characterized in that, it also comprises the second NMOS tube N2, 3rd NMOS tube N3, 4th NMOS tube N4, bias current Ibiasp, the drain terminal of described first NMOS tube N1 connects the source of described second NMOS tube N2, the grid end of the 3rd NMOS tube N3, the drain terminal of the N2 of described second NMOS tube is drive output OUT, the grid end of described second NMOS tube N2 connects grid end and the drain terminal of described 4th NMOS tube N4, bias current Ibiasp one end, the described bias current Ibiasp other end connects power vd D, the source of described 4th NMOS tube N4 connects the drain terminal of described 3rd NMOS tube N3, the source ground connection of described 3rd NMOS tube N3.

2. a kind of current-limiting protection circuit opening Lou output according to claim 1; it is characterized in that; described driving input IN place arranges PMOS P1; the grid end of described PMOS P1 connects the input of described reverser I1; the source of described PMOS P1 connects the drain terminal of described 4th NMOS tube N4, and the drain terminal of described PMOS P1 connects described bias current Ibiasp one end.