CN104346314A

CN104346314A - Monobus reception logic structure

Info

Publication number: CN104346314A
Application number: CN201310347693.7A
Authority: CN
Inventors: 鲍长君
Original assignee: SHANGHAI LONG CHENG AUTOMATION SYSTEM Co Ltd
Current assignee: SHANGHAI LONG CHENG AUTOMATION SYSTEM Co Ltd
Priority date: 2013-08-09
Filing date: 2013-08-09
Publication date: 2015-02-11
Anticipated expiration: 2033-08-09
Also published as: CN104346314B

Abstract

The invention discloses a monobus reception logic structure which comprises an edge triggering module, a clock generation module and a reset module, wherein the edge triggering module is respectively connected with the reset module and the clock generation module; the reset module is connected with the clock generation module; the edge triggering module is connected with a monobus signal input end and used for recognizing a digital string starting edge and enabling the clock generation module to start timing; the clock generation module is connected with a system clock and used for clock timing and outputting a preset chip selection clock signal, a preset digit clock signal and a preset frame reset signal according to a preset pulse width and a preset frame digit. The monobus reception logic structure has the technical effects that the function can be realized by a hardware programmable device, few resources are consumed by the hardware, the time delay is small, the processing speed is high, the real-time property is strong, software halt does not happen during pure-hardware execution, the reception bit rate is not influenced by the period of MCU machines and the reception of high-speed code rate can be realized.

Description

A kind of unibus receive logic structure

Technical field

The present invention relates to electronic applications, be specifically related to a kind of unibus receive logic structure.

Technical background

Traditional method based on MCU software programming sampling receives unibus signal, needs to consume cpu resource, and receive the limited speed of code check in the operation clock period of CPU, implementation effect depends on cpu performance completely.And the generic logic chip of the not ready-made maturation of simple DLC (digital logic circuit) or circuit can solve the ability of automatic reception high-speed data code string data.

Summary of the invention

For the deficiencies in the prior art, the technical scheme that the present invention will solve is to provide one, can be realized by hardware programmable device, hardware consumption resource is few, time delay is little, processing speed is fast, real-time, software crash can not occur in hardware execution, receive bit rate does not affect by the MCU machine cycle, can realize the unibus receive logic structure received high speed code check.

For solving the problems of the technologies described above, the technical solution used in the present invention is a kind of unibus receive logic structure, comprise edge-triggered module, Clock generation module and reseting module, described edge-triggered module is connected with reseting module, Clock generation module respectively, described reseting module is connected with Clock generation module, described edge-triggered model calling unibus signal input part, for identifying that number strings initial line edge and enable Clock generation module starts clock timing; Described reseting module is used for for providing reset signal when powering on and start and controlling its receiving end received frame reset signals enable of all the other signals; Described Clock generation module is connected with system clock, for clock timing, and according to the pulsewidth preset and framing bit number, exports pre-set sheet and selects clock signal, bit clock signal and frame reseting signal.

Preferably, described unibus receive logic structure comprises serioparallel exchange module, and described serioparallel exchange module is connected with Clock generation module, and the SPI signal for being exported by Clock generation module converts parallel port signal to and exports.

Preferably, described edge-triggered module is edge-triggered device, rest-set flip-flop, the high-speed sampling voting machine with reset function.

Preferably, described edge-triggered module is the programmable logic chip with reset function.

Preferably, described Clock generation module has enable and counter that is Protection Counter Functions.

Preferably, described Clock generation module has enable and programmable logic chip that is Protection Counter Functions.

The present invention has the ability of automatic reception high-speed data code string single bus data, coordinate inner clock generator the present invention with low-down delay, high speed code string (such as: unibus) data layout can also be turned to the SPI formatted output of standard in addition, realize the seamless link to the communication of SPI interface device.Be: consumption of natural resource is few that processing speed is fast, real-time with the good effect that traditional Measures compare has, hardware performs can not there is software crash, and receiving bit rate does not affect by the MCU machine cycle, can realize the reception to high speed code check.

Accompanying drawing explanation

Fig. 1 is unibus receive logic structure principle chart of the present invention

Fig. 2 is an embodiment of the present invention figure

Fig. 3 is unibus receive logic structure sequential chart of the present invention

Fig. 4 is unibus receive logic arrangement works process flow diagram of the present invention

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Bus receive logic structure principle chart as shown in Figure 1, comprise edge-triggered module, Clock generation module and reseting module, wherein edge-triggered module is connected with reseting module with Clock generation module respectively, Clock generation module is connected with reseting module, Clock generation module is connected with system clock, described edge-triggered model calling is to unibus signal input part, for identification data code string start edge and enable clock generator starts clock count, reseting module provides reset signal to the overall situation and controls its receiving end received frame reset signal enable of output signal at the beginning of system electrification, , Clock generation module start after edge-triggered module sends enable signal here counting, and according to preset pulsewidth and framing bit number, export pre-set sheet and select clock signal, bit clock signal and frame reseting signal.

Preferably, as Fig. 1 can connect a string and modular converter after Clock generation module, export after the SPI signal that Clock generation module exports by serioparallel exchange module converts parallel port signal to.

Fig. 2 is a rest-set flip-flop with reset function, a reseting module chip and has counter circuit connection layout that is enable and Protection Counter Functions.Fig. 3 is bus receive logic arrangement works sequential chart, and in figure, data_in is unibus input signal; Rst_n is reset and the enable signal of clock generation module; Clk_cs is the chip selection signal exporting SPI signal; Clk_bit is the bit clock letter exporting SPI signal; Data_out is the data-signal that SPI exports; Clk_rst is frame reseting signal.

The principle of work of structure of the present invention is described in further detail below in conjunction with Fig. 4 bus receive logic arrangement works process flow diagram, is powering on beginning, reseting module initialization edge-triggered module namely carries out reset and Clock generation module internal counter resets.Then system is in the state of wait-receiving mode serial data code.When first start edge of serial data code starts to cause level to change, edge-triggered module is triggered set, start the enable of Clock generation module simultaneously, Clock generation module starts counting under the ordering about of local clock, form according to presetting (comprises pulsewidth, the information such as framing bit number) produce chip selection signal and frame clock, produce bit clock isochronon signal each correct position of serial data code is simultaneously synchronous.Serial data code is converted to the SPI signal of standard by such realization.It is produce frame reseting signal that Clock generation module also has a function, its objective is that when a frame signal end of transmission (EOT) after, to notify that reseting module resets overall, so that wait-receiving mode next frame serial data code.Can also parallel port signal be become to export by serioparallel exchange SPI signal if necessary, equipment follow-up so just directly can read the information obtaining a complete frame.

Above specific embodiment only describes principal character and the innovative point of this programme.Those skilled in the art should understand, and this programme is not restricted to the described embodiments.Under the prerequisite not departing from the innovation point and protection domain, this programme also has various change, and these changes and improvements all will fall in the claimed scope of this programme.The claimed scope of this programme is limited by appending claims and equivalent thereof.

It should be noted that above-described embodiment is to illustrate instead of limiting the present invention, those skilled in the art can design many embodiment under the condition of scope not deviating from claims.Word " comprises " existence not getting rid of those elements different from the element listed in claim or step or step.Word "a" or "an" before element does not get rid of the existence of multiple this element, enumerating in several circuit claims, several in these devices can show by one, hardware branch is also same, only because some method describes in different dependent claims, do not illustrate that the combination of these methods can not be used for making a profit.

It should be noted that, in this article, the such as relational terms of the first and second grades is only used for an entity or operation and another entity or operational zone to separate, and not necessarily require or imply the relation or order that there is any this reality between these entities or operation, and, term " comprises ", " to comprise " or any other variant is intended to contain comprising of nonexcludability, thus make the process comprising a series of key element, method, article or equipment not only comprise those key elements, but also comprise those other key elements clearly listed, or also comprise for this process, method, article or the intrinsic key element of equipment, term " is connected ", " connection ", " be connected to " or other variants, not only comprise and two entities are directly connected, also comprise and being indirectly connected by having useful other entities improving effect.

Claims

1. a unibus receive logic structure, it is characterized in that: comprise edge-triggered module, Clock generation module and reseting module, described edge-triggered module is connected with reseting module, Clock generation module respectively, described reseting module is connected with Clock generation module, described edge-triggered model calling unibus signal input part, for identifying that number strings initial line edge and enable Clock generation module starts clock timing; Described reseting module is used for for providing reset signal when powering on and start and controlling its receiving end received frame reset signals enable of all the other signals; Described Clock generation module is connected with system clock, for clock timing, and according to the pulsewidth preset and framing bit number, exports pre-set sheet and selects clock signal, bit clock signal and frame reseting signal.

2. unibus receive logic structure according to claim 1, is characterized in that: comprise serioparallel exchange module, and described serioparallel exchange module is connected with Clock generation module, and the SPI signal for being exported by Clock generation module converts parallel port signal to and exports.

3. unibus receive logic structure according to claim 1, is characterized in that: described edge-triggered module is edge-triggered device, rest-set flip-flop, the high-speed sampling voting machine with reset function.

4. unibus receive logic structure according to claim 1, is characterized in that: described edge-triggered module is the programmable logic chip with reset function.

5. unibus receive logic structure according to claim 1, is characterized in that: Clock generation module has enable and counter that is Protection Counter Functions.

6. unibus receive logic structure according to claim 1, is characterized in that: Clock generation module has enable and programmable logic chip that is Protection Counter Functions.