CN104346314B

CN104346314B - A kind of monobus receives logical construction

Info

Publication number: CN104346314B
Application number: CN201310347693.7A
Authority: CN
Inventors: 鲍长君
Original assignee: SHANGHAI LONG CHENG AUTOMATION SYSTEM Co Ltd
Current assignee: SHANGHAI LONG CHENG AUTOMATION SYSTEM Co Ltd
Priority date: 2013-08-09
Filing date: 2013-08-09
Publication date: 2018-01-05
Anticipated expiration: 2033-08-09
Also published as: CN104346314A

Abstract

The invention discloses a kind of monobus to receive logical construction, including edge-triggered module, Clock generation module and reseting module, the edge-triggered module is connected with reseting module, Clock generation module respectively, the reseting module is connected with Clock generation module, the edge-triggered module connects monobus signal input part, starts clock timing for identifying digital string start edge and enabling Clock generation module；The Clock generation module is connected with system clock, for clock timing, and according to pulsewidth set in advance and framing bit number, exports pre-set piece and selects clock signal, bit clock signal and frame reseting signal.What the present invention obtained has the technical effect that：The function can be realized by hardware programmable device, hardware consumption resource is few, and time delay is small, and processing speed is fast, real-time, and pure hardware, which performs, will not occur software crash, and receive bit rate is not influenceed by the MCU machine cycles, it is possible to achieve the reception to high speed code check.

Description

A kind of monobus receives logical construction

Technical field

The present invention relates to electronic applications, and in particular to a kind of monobus receives logical construction.

Technical background

The traditional method based on MCU software programmings sampling receives monobus signal, it is necessary to consume cpu resource, receives The limited speed of code check depends entirely on cpu performance in CPU operation clock cycle, implementation effect.And simple Digital Logic Circuit, which does not have ready-made ripe generic logic chip or circuit, can solve the automatic energy for receiving high-speed data sequence data Power.

The content of the invention

In view of the shortcomings of the prior art, the invention solves technical scheme be to provide one kind, can be by hardware programmable What device was realized, hardware consumption resource is few, and time delay is small, and it is dead that processing speed is fast, real-time, software will not occur for hardware execution Machine, reception bit rate are not influenceed by the MCU machine cycles, it is possible to achieve receive logical construction to the monobus that high speed code check receives.

In order to solve the above technical problems, the technical solution adopted by the present invention, which is a kind of monobus, receives logical construction, including With reseting module, clock mould occurs for edge-triggered module, Clock generation module and reseting module, the edge-triggered module respectively Block is connected, and the reseting module is connected with Clock generation module, the edge-triggered module connection monobus signal input End, start clock timing for identifying digital string start edge and enabling Clock generation module；The reseting module is used for Reset signal is provided when establishing the beginning by cable and controls its receiving terminal that enables of remaining signal to receive frame reseting signal；Mould occurs for the clock Block is connected with system clock, for clock timing, and according to pulsewidth set in advance and framing bit number, exports pre-set Piece selects clock signal, bit clock signal and frame reseting signal.

Preferably, the monobus, which receives logical construction, includes serioparallel exchange module, the serioparallel exchange module It is connected with Clock generation module, the SPI signal for Clock generation module to be exported is converted into parallel port signal output.

Preferably, the edge-triggered module is the edge-triggered device, rest-set flip-flop, high speed for having reset function Sample voting machine.

Preferably, the edge-triggered module is the programmable logic chip for having reset function.

Preferably, the Clock generation module is the counter with enabled and Protection Counter Functions.

Preferably, the Clock generation module is the programmable logic chip with enabled and Protection Counter Functions.

The present invention has the automatic ability for receiving high-speed data sequence single bus data, coordinates the clock of inside to occur in addition The device present invention can also be postponed high speed sequence with low-down（Such as：Monobus）The SPI forms that data format turns to standard are defeated Go out, realize the seamless connection to be communicated to SPI interface device.The good effect that comparing with traditional method has is：Consume resource Few, processing speed is fast, real-time, and hardware, which performs, will not occur software crash, receives bit rate not by MCU machine cycle shadows Ring, it is possible to achieve the reception to high speed code check.

Brief description of the drawings

Fig. 1 is that monobus of the present invention receives logical construction schematic diagram

Fig. 2 is an embodiment of the present invention figure

Fig. 3 is that monobus of the present invention receives logical construction timing diagram

Fig. 4 is that invention monobus receives logical construction workflow diagram

Embodiment

The present invention is described in further detail with reference to the accompanying drawings and detailed description.

Bus as shown in Figure 1 receives logical construction schematic diagram, including edge-triggered module, Clock generation module and reset mould Block, wherein edge-triggered module are connected with Clock generation module and reseting module respectively, Clock generation module and reseting module It is connected, Clock generation module is connected with system clock, and the edge-triggered module is connected to monobus signal input part, uses Start clock count in identification data sequence start edge and enabled clock generator, reseting module is at the beginning of system electrification to complete Office provides reset signal and controls its receiving terminal that enables of output signal to receive frame reseting signal；, Clock generation module is at edge Trigger module starts counting up after sending enable signal, and pre-set according to pulsewidth set in advance and framing bit number, output Piece select clock signal, bit clock signal and frame reseting signal.

Preferably, as Fig. 1 can connect a serioparallel exchange module, serioparallel exchange mould behind Clock generation module Block exports after the SPI signal that Clock generation module exports is converted into parallel port signal.

Fig. 2 is a rest-set flip-flop with reset function, a reseting module chip and one with enabled and Protection Counter Functions Counter circuit connection figure.Fig. 3 is that bus receives logical construction working timing figure, and data_in is monobus input letter in figure Number;Rst_n is reset and the enable signal that module occurs for clock;Clk_cs is the chip selection signal of output SPI signal;Clk_bit is Export the bit clock letter of SPI signal；Data_out is the data-signal of SPI outputs；Clk_rst is frame reseting signal.

The work that structure of the present invention is described in further detail with reference to Fig. 4 buses reception logical construction workflow diagram is former Reason, at the beginning of upper electricity, reseting module initialization edge-triggered module carries out resetting and Clock generation module internal counter is clear Zero.Then system be in etc. serial data code to be received state.When first start edge of serial data code starts to cause level During change, edge-triggered module is triggered set, while starts the enabled of Clock generation module, and Clock generation module is when local Started counting up under the driving of clock, according to form set in advance（Including pulsewidth, the information such as framing bit number）When production chip selection signal is frame Clock, bit clock isochronon signal is synchronously produced simultaneously in the serial data code correct position of each.It is achieved in that serial data code It is converted into the SPI signal of standard.It is to produce frame reseting signal that Clock generation module, which also has One function, and the purpose is to when a frame It is global to notify that reseting module resets after the signal end of transmission, so as to etc. next frame serial data code to be received.If necessary also Can by SPI signal by serioparallel exchange into parallel port signal output, it is complete that so follow-up equipment can directly reads acquisition The information of one frame.

Embodiments above only describes the principal character and innovative point of this programme.Those skilled in the art should Solution, this programme are not restricted to the described embodiments.On the premise of the innovation point and protection domain is not departed from, this programme also has Various change, these changes and improvements are fallen within the claimed scope of this programme.The claimed scope of this programme by Appended claims and its equivalent limit.

It should be noted that above-described embodiment is to illustrate and not limit the present invention, those skilled in the art are by energy It is enough that many alternative embodiments are designed under conditions of without departing substantially from scope of the following claims.Word "comprising" be not excluded for those with The presence of the different element or step of the element or step listed in claim.Word "a" or "an" before element is not arranged Except the presence of multiple this elements, in several circuit claims are enumerated, several in these devices can be by one come table Existing, hardware branch is also same, merely because some methods are described in different dependent claims, does not illustrate these The combination of method can not be used for making a profit.

It should be noted that herein, the relational terms of the first and second grades be used merely to an entity or Person operates to be made a distinction with another entity or operation, and is not necessarily required or implied to exist between these entities or operation and appoint What this actual relation or order, moreover, term "comprising", " comprising " or any other variant be intended to it is non-exclusive Property includes, so that process, method, article or equipment comprising a series of elements not only include those key elements, and Also include those other elements for being expressly recited, or also include for this process, method, article or equipment inherently Key element, term " connected ", " connection ", " being connected to " or other variants, not only include two entities being joined directly together connecing, Including by being connected indirectly with other entities beneficial to improvement.

Claims

1. a kind of monobus receives logical construction, it is characterised in that：Including edge-triggered module, Clock generation module and reset mould Block, the edge-triggered module are connected with reseting module, Clock generation module respectively, and with clock mould occurs for the reseting module Block is connected, and the edge-triggered module connects monobus signal input part, for identify digital string start edge and it is enabled when Clock occurs module and starts clock timing；The reseting module is used to provide reset signal during the beginning above to establish by cable and control remaining signal Enable its receiving terminal receive frame reseting signal；The Clock generation module is connected with system clock, for clock timing, and According to pulsewidth set in advance and framing bit number, export pre-set piece and select clock signal, bit clock signal and frame to reset letter Number；

When first start edge of serial data code starts to cause level change, the edge-triggered module is triggered set, Start the enabled of the Clock generation module simultaneously, the Clock generation module starts counting up under the driving of local clock, root Chip selection signal is produced according to form set in advance.

2. monobus according to claim 1 receives logical construction, it is characterised in that：It is described including serioparallel exchange module Serioparallel exchange module is connected with Clock generation module, and the SPI signal for Clock generation module to be exported is converted into and message Number output.

3. monobus according to claim 1 receives logical construction, it is characterised in that：The edge-triggered module is that have Edge-triggered device, rest-set flip-flop, the high-speed sampling voting machine of reset function.

4. monobus according to claim 1 receives logical construction, it is characterised in that：The edge-triggered module is that have The programmable logic chip of reset function.

5. monobus according to claim 1 receives logical construction, it is characterised in that：Clock generation module is that have to enable With the counter of Protection Counter Functions.

6. monobus according to claim 1 receives logical construction, it is characterised in that：Clock generation module is that have to enable With the programmable logic chip of Protection Counter Functions.