CN101753543B - FF (foundation field) bus frame type recognizer - Google Patents
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Abstract
The invention relates to a FF (foundation field) bus frame type recognizer arranged in a data link layer of a FF field bus. The FF bus frame type recognizer comprises a frame controlled word coding and target address receiving module, an address matching module, and a conversion circuit, wherein the frame controlled word coding and target address receiving module is used for generating frame control information, an address matching result and relevant parameters of a protocol data unit of the data link layer based on data signals received from the field bus and sending the frame control information, the address matching result and the relevant parameters of the protocol data unit of the data link layer to an upper processing unit of the data link layer; the address matching module is used for carrying out address matching processing on received address table data in the data link layer and an address data available indicating signal received through the conversion circuit and outputting to the upper processing unit of the data link layer; and the conversion circuit is used for carrying out timing adjustment on the address data available indicating signal and sending the adjusted address data available indicating signal to the address matching module. The invention can extract the type information of a DLPDU (data link protocol data unit), can identify the long address or the short address of the DLPDU, can extract the address information of the DLPDU, and can be implemented in various modes of FPGA (field programmable gate array), CPLD (complex programmable logic device), IP (internet protocol) and the like.
Description
Technical field
The present invention relates to a kind of field bus technique, specifically a kind of FF bus frame type identifier that extracts FF bus data link layer data cell frame control information.
Background technology
The Protocol Control Information that generates on FF fieldbus (FOUNDATION Filedbus the is called for short FF) data link layer is realized the control to all kinds of link transmission activities on the bus.Link time synchronized of each equipment room etc. all realizes through data link layer on the detection of the link activity scheduling in the bus communication, the reception of data and transmission, active state and response, the bus.Data link layer protocol data unit (DLPDU) provides the Protocol Control Information of data link.Protocol Control Information is made up of three parts.First is a frame control information, indicates kind, address size, priority of data link layer protocol data unit etc.; Second portion is a data link address, comprises destination address and source address, and the data link layer protocol data unit that is not all kinds all has destination address and source address; Third part then indicates the parameter of such data link layer protocol data unit.The control information of data link layer protocol data unit is extracted by software and is realized that take too much resource, performance is lower in traditional design.
Summary of the invention
To the above-mentioned weak point that exists in the prior art, the technical problem that the present invention will solve provides a kind of FF bus frame type identifier that extracts frame control information, data link address and relevant parameter through hardware circuit.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is:
A kind of FF bus of the present invention frame type identifier; Be located in the FF fieldbus data link layer; Comprise: decoding of frame control word and destination address receiver module; With the relevant parameter that receives, be transmitted to the upper strata processing unit of data link layer from the control information of data-signal delta frame, matching addresses result and the data link layer protocol data unit of fieldbus; The matching addresses module is carried out the matching addresses processing with the address table data in the data link layer that receives and through the address date effective index signal that change-over circuit receives, and exports the upper strata processing unit of data link layer to, the result of indication matching addresses; Change-over circuit is used for the address date effective index signal is carried out the sequential adjustment, delivers to the matching addresses module, and the indication address date is effective.
Said frame control word decoding and destination address receiver module comprise:
Frame control word latch, the data-signal of reception fieldbus latchs the frame control word;
The counting comparison controller, the control signal of reception fieldbus is counted control signal, when reaching the address word joint number of decoding logic circuit output, produces and outputs signal to the matching addresses module;
Decoding logic circuit is deciphered the frame control word of frame control word latch output, exports the upper strata processing unit of data link layer to;
The destination address receiver, the data-signal of reception fieldbus extracts destination address, exports the matching addresses module to.
Said matching addresses module comprises: the address table data receiver module, and the address comparison module, request postpones processing module and four modules of state machine
The address table data receiver module receives the address table data in the data link layer, delivers to the address comparison module;
The address comparison module compares the frame control word decoding that receives and the destination address of destination address receiver module and the address table data of address table data receiver module, and calculated address match flag signal is delivered to the upper strata processing unit of data link layer;
Request postpones processing module, and the address table data effective index signal that receives is carried out delay process;
State machine, the signal of decoding of received frame control word and destination address receiver module generates control signal address table data reception module and address comparison module is controlled, and generates the upper strata processing unit that status signal is delivered to data link layer simultaneously;
Or door, the matching addresses marking signal of receiver address comparison module and address table end mark signal, generating tables look-up finishes the upper strata processing unit of letter output number to data link layer;
With door, the matching addresses marking signal of receiver address comparison module, address table end mark signal, the table look-up marking signal and the enable signal of tabling look-up generate the address table that the request signal of tabling look-up exports data link layer to.
Said change-over circuit comprises the 1st～3 trigger and XOR gate; Wherein the input port of the 1st trigger is connected to the effective index signal of address table data; Export the input port of the 2nd trigger to; The output of the 2nd trigger links to each other with the input port of the 3rd trigger, and the XOR gate input links to each other with the output of the 2nd trigger and the output of the 3rd trigger respectively, and output is connected to the matching addresses module.
The present invention has following beneficial effect and advantage:
1. kind of information that can extract real-time DLPDU;
2. can discern location longways or the short address of DLPDU;
3. can extract the address information of DLPDU;
4. can realize with multiple modes such as FPGA, CPLD, IP.
Description of drawings
Fig. 1 is a structured flowchart of the present invention;
Fig. 2 receives the structured flowchart of decoding and destination address receiver module for frame control word among the present invention;
Fig. 3 is that frame control word of the present invention receives decoding and the destination address receiver module adopts relatively control flow chart of data;
Fig. 4 is that the data that frame control word reception decoding of the present invention and destination address receiver module adopt compare control timing figure;
Fig. 5 changes circuit theory diagrams among the present invention;
The sequential chart that Fig. 6 adopts for change-over circuit among the present invention;
Fig. 7 is matching addresses module frame chart among the present invention;
Fig. 8 is the state machine transition diagram in the matching addresses module among the present invention;
Fig. 9 is the state machine state conversion timing sequence figure in the matching addresses module among the present invention;
Figure 10 is for using FF fieldbus model structure figure of the present invention.
Embodiment
FF bus frame type identifier of the present invention is located in the FF fieldbus data link layer, and is shown in figure 10, and FF fieldbus model structure has adopted three layers in the osi model: physical layer, data link layer and application layer have concealed the three～six layer.Wherein physical layer, data link layer adopt the IEC/ISA standard.Application layer has two sub-layer: fieldbus access sub-layer FAS and fieldbus information standard sublayer FMS, and will be from the data link to FAS, and the repertoire of FMS is integrated into communication stack (Communication Stack).
As shown in Figure 1; FF of the present invention (FOUNDATION Filedbus; Abbreviation FF) bus frame type identifier is made up of three main modular; Be respectively the decoding of frame control word and destination address receiver module, matching addresses module and change-over circuit; Wherein decoding of frame control word and destination address receiver module receive data-signal rcv_data, the data byte index signal rcv_bytesyn from fieldbus and receive effective index signal raf_syn; Delta frame control signal frame_cntrl, frame coded signal frame_code, receive broadcast frame marking signal rbmf, receive psa flag of frame signal rpsaf, receive node address flag of frame signal rnaf, receive NS address frame marking signal ns, receive HL address frame marking signal hl and receive frame control word marking signal rfcf; Be transmitted to the upper strata processing unit of data link layer; Extract destination address destaddr and destination address byte number addrbytes simultaneously, calculated address coupling enabling signal addrmatch_start delivers to the matching addresses module; The matching addresses module with the address table data tab_data in the data link layer that receives, local node sign node_id, Address Recognition mode enable signal arme, receive error flag signal ref and carry out address table through the address date effective index signal tab_wr that change-over circuit receives and search with matching addresses and handle; Output table look-up end signal tab_finish, matching addresses marking signal amof, marking signal ltaf and address table end mark signal etdf the upper strata processing unit of tabling look-up to data link layer; The result of indication matching addresses generates simultaneously and tables look-up request signal tab_drq to data link layer address table; Change-over circuit is used for address date effective index signal tab_wr is carried out the sequential adjustment, and calculated address table data index signal tab_bytesyn delivers to the matching addresses module, and the indication address date is effective.
As shown in Figure 2; Said frame control word decoding and destination address receiver module comprise frame control word latch, counting comparison controller, decoding logic circuit and destination address receiver; Frame control word latch wherein receives the data-signal rcv_data and the data byte index signal rcv_bytesyn of fieldbus, latchs the frame control word; Deliver to decoding logic circuit, and generation receives frame control word marking signal rfcf; The counting comparison controller; Receive the data byte index signal rcv_bytesyn and reception effective index signal raf_syn of fieldbus; The rcv_bytesyn signal is counted; Receive enable signal addrget_en according to count value delta frame control word latch enable signal fclatch_en and destination address; Deliver to frame control word latch and destination address receiver respectively, when count value reaches the destination address byte number addrbytes of decoding logic circuit output, produce matching addresses enabling signal addrmatch_start to the matching addresses module; Decoding logic circuit, the frame control word frame_cntrl that frame control word latch is exported deciphers, and exports all frame type information frame_code, rbmf, rpsaf, rnaf, ns and the hl upper strata processing unit to data link layer; The destination address receiver, the data-signal rcv_data and the data byte index signal rcv_bytesyn of reception fieldbus extract destination address, and destaddr is to the matching addresses module in output.
As shown in Figure 7; Said matching addresses module comprises: address table data receiver module, address comparison module, request postpone processing module, four modules of state machine and or door, with door; Address table data receiver module wherein; Receive the address table data tab_data in the data link layer, address table data is gone here and there and changed the back generate register signal shiftreg and deliver to the address comparison module; The address comparison module; The frame control word decoding that receives and the destination address destaddr of destination address receiver module and the address table data shiftreg of address table data receiver module are compared, and calculated address match flag signal amof delivers to the upper strata processing unit of data link layer; Request postpones processing module, and the address table data index signal tab_bytesyn that receives is carried out delay process, generates the enable signal tab_drq_en that tables look-up and delivers to and door; State machine, the signal of decoding of received frame control word and destination address receiver module generates control signal address table data reception module and address comparison module is controlled, and generates the upper strata processing unit that status signal is delivered to data link layer simultaneously; Or door, the matching addresses marking signal amof of receiver address comparison module and address table end mark signal etdf generate the upper strata processing unit of end signal tab_finish to data link layer of tabling look-up; With door; The matching addresses marking signal amof of receiver address comparison module, address table end mark signal etdf, table look-up the marking signal ltaf and the enable signal tab_drq_en that tables look-up generate the address table that the request signal tab_drq that tables look-up exports data link layer to.
As shown in Figure 5; Said change-over circuit comprises the 1st～3 trigger D1～D3 and XOR gate XOR1; Wherein the input port of the 1st trigger D1 is connected to the effective index signal of address table data, exports the input port of the 2nd trigger D2 to, and the output of the 2nd trigger D2 links to each other with the input port of the 3rd trigger D3; XOR gate XOR1 input links to each other with the output of the 2nd trigger D2 and the output of the 3rd trigger D3 respectively, and output is connected to the matching addresses module.
As shown in Figure 1; Frame control word decoding in the FF bus frame type identifier of the present invention and destination address receiver module are when receiving a new frame; Receive wherein the frame control word and to its decoding; After latching destination address, send matching addresses enabling signal addrmatch_start to the matching addresses module.The matching addresses module is then under Address Recognition mode enable (arme=1) situation; Through its inner state machine control; Destination address byte number addrbytes (representing the different address type) and destination address destaddr according to the decoding logic circuit output in decoding of frame control word and the destination address receiver module carry out the matching destination address operation; If address style is HL or NS, then need carry out table lookup operation.Acting as of signal between the decoding of frame control word and destination address receiver module and the matching addresses module: addrmatch_start is a pulse signal, and the indication matching addresses can be carried out, and after the destination address reception finishes, then can make this signal effective; Destaddr signal output destination address; The addrbytes signal is the destination address byte number, desirable 0,1,2,4.Handle for status signal; At the status signal of delivering to data link layer upper strata processing unit (frame_cntrl, frame_code, rmbf, rpsaf, rnaf, ns, hl, rfcf, tab_finish, amof, ltaf, etdf) that the present invention produced; Like address matching signal amof after relatively finishing; Its state keeps always, arrives up to next frame and just removes (utilizing the raf_syn pulse signal to remove gets final product); Receive fault processing for frame, if wrong (ref=1) took place to receive before destination address finishes receiving, then matching addresses should be carried out errored response (the halt address coupling is got back to idle condition); If after destination address is received, take place to receive wrong (ref=1), then matching addresses is left intact, although because frame receives mistake, data link layer still needs the information of matching addresses to carry out fault processing.Do not process for decoding of frame control word and destination address receiver module; For the matching addresses module,, otherwise be left intact if do not detect ref=1 before the addrmatch_start=1 then turn back to initial condition detecting.The main effect of change-over circuit is a shaping feature of accomplishing input signal.
The flow chart of counting comparison controller is as shown in Figure 3; The control section of said frame control word decoding and destination address receiver module is realized by the counting comparison controller; Its inside comprises control counter, and the back initial count value that resets is 0, when the clk rising edge; When detecting reception effective index signal (raf_syn=1), the count value of control counter is put 1 (carrying out the preparation that receives a new frame); When detecting data byte index signal effective (rcv_bytesyn=1), if this moment, count value was not more than addrbytes+2, then count value adds 1; Otherwise expression has been accomplished destination address and has been received, and does not add 1 operation.The counting comparison controller decides enable signal by control counter; When the count value of counting comparison controller is 1; Fclatch_en is effective for frame control word latch enable signal; Otherwise when the count value of counting comparison controller greater than 1 and when adding 1 smaller or equal to the address word joint number, it is effective that destination address receives enable signal addrget_en; Otherwise when the count value of counting comparison controller equaled the address word joint number and adds 2, addrmatch_start was effective for the matching addresses enabling signal, and matching addresses begins, otherwise end operation.When addrbytes was 2, sequential chart was as shown in Figure 4.
As shown in Figure 5, change-over circuit is made up of the 1st～3 trigger D1～D3 and an XOR gate XOR1 circuit.Because the 500kHz clock that the clock that the address table data effective index signal produces uses far above the matching addresses module; So when address table data is effective, can send read-write upset index signal; Be tab_wr, utilize change-over circuit to obtain a 500kHz clock address table data index signal signal tab_bytesyn by the tab_wr energizing signal.The sequential relationship of change-over circuit is as shown in Figure 6.
As shown in Figure 7, said matching addresses module is responsible for tabling look-up and compare operation, and control section is realized by state machine.Matching operation is according to address byte number addrbytes classification processing, if do not have destination address (addrbytes=0) then the nothing operation; If node_id type (addrbytes=1), then direct and node_id relatively gets final product; If HL or NS type (addrbytes=4 or 2) then must be carried out table lookup operation.
There are two counters address table data receiver module inside, address table data byte counter and continuous 0 byte counter, respectively recorder to byte number and the address table data of address table data in the number of appearance 0 byte continuously.At the clk rising edge, when detecting valid data indications (raf_syn=1), the count value of then putting address table data byte counter and continuous 0 byte counter is 0.When tabling look-up enable signal tabdataget_en effective (tabdataget_en=1); If during tab_bytesyn=1, the receiver address table data that then are shifted are to register signal shiftreg, and the count value of address table data byte counter adds 1; And judge whether address table data tab_data is 0; If be 0, the count value of then continuous 0 byte counter adds 1, otherwise the count value of continuous 0 byte counter of resetting is 0; When receiving a full address (count value of address table data byte counter equals addrbytes), the count value of then putting the address table data byte counter is 0.Address table end mark signal etdf judges that through the number of continuous 0 byte in the address table data receiver module statistics address table data when addrbytes=2, the count value of continuous 0 byte counter is at 3 o'clock, and etdf is changed to 1; When addrbytes=4, the count value of continuous 0 byte counter is 6 o'clock, and etdf is changed to 1.
Request postpones processing module and is used for control address table Data Receiving; If destination address is HL or NS type; Table lookup operation just can continue to carry out, but consider should be suitable the partial bus cycle of abdicating give other transaction, institute thinks that the matching addresses time-delay that joins request is machine-processed: behind the address table data tab_data of a byte of every processing; Must postpone several 500kHz cycles, just can send the new request of tabling look-up afterwards.The concrete realization postpones processing module inside in request and comprises a delay counter, is 1 o'clock whenever detect tab_bytesyn at the clk rising edge, and the value of delay counter is changed to initial value (can set initial value as required, initial value must greater than zero); If the count value of tab_bytesyn=0 and delay counter is greater than 0, then count value subtracts 1.The enable signal tab_drq_en that when the count value of counter is 0, just will table look-up puts 1.
The operation of address comparison module is divided into two kinds according to address style: node_id compares and the comparison of tabling look-up.For node_id relatively, at the clk rising edge, when detecting node_id and relatively enabling nodeid_en=1, just can compare.For the comparison of tabling look-up,,, just can compare if when the byte number of the address table data that receives equals destination address byte number (data link layer address table receive a sufficient address) at the clk rising edge.The address comparative result is that above-mentioned two comparative results are carried out or operate, and draws matching addresses marking signal amof at last.
Etdf&<ab&&tab_drq_en uses with door and realizes.Table look-up end signal by matching addresses marking signal amof and address table end mark signal etdf decision, and the generation expression formula is tab_finish=amof||etdf, uses valve to realize.
As shown in Figure 8, said control state machine has one of four states, is respectively: S0: initial condition (initialstate) is carried out initialization; S1: wait state (wait state) is waited for up to Address Recognition mode enable and reception data effective; S2: active state 1 (active statel), the comparison of tabling look-up; S3: active state 2 (active state2), disposable node_id relatively.The state exchange relation is: after resetting, get into initial condition S0; At the clk rising edge, if matching addresses mode enable signal arme is invalid, then state machine gets into initial condition S0 afterwards, and arme is effective, changes according to state machine current state currentstate completion status.When current state is S0, as detects the Address Recognition mode enable and receive data effectively (arme=1&&raf_syn=1), then the state of state machine jumps to S1.When current state is S1; When detect that matching addresses begins and the address word joint number be 0 or receive wrong or the Address Recognition pattern do not enable ((addrmatch_start=1&&addrbytes=0) || in the time of ref=1||arme=0), then next state is S0; If detect that matching addresses begins and address word joint number when equaling 1 (addrmatch_start=1&&addrbytes=1&&addrbytes＞0), then next state is S3;=1&&addrbytes＞0), then next state is S2.When current state was S2, if the Address Recognition pattern does not enable or address table finishes (arme=0||inner_tab_finish=1), then next state was S0; If detect the Address Recognition mode enable and receive data effectively (arme=1&&raf_syn=1), then next state is S1.When current state was S3, node_id is disposable relatively only to need a clock cycle, if detect the Address Recognition mode enable and receive data effectively (arme=1&&raf_syn=1), then next state is S1; Otherwise next state is S0.The control signal that state machine generates is determined by residing different conditions; When the state of state machine is S0, carry out initialization, ltaf is changed to 0 (the nothing request of tabling look-up); Tabdataget_en is changed to 0 (disable address table Data Receiving enables), and nodeid_en was changed to for 0 (forbidding that node_id relatively enables); When the state of state machine was S1, ltaf was changed to 0, and tabdataget_en is changed to 0, and nodeid_en is changed to 0; When the state of state machine was S2, tabdataget_en was changed to 1 (address table data receives and enables), and ltaf is changed to 1 (request of tabling look-up), and nodeid_en is changed to 0; When the state of state machine was S3, nodeid_en was changed to 1 (enabling node_id relatively enables), and tabdataget_en is changed to 0, and ltaf is changed to 0.To receive the destination address type is that the frame of NS is an example, and the initial value that request postpones the delay counter of processing module is 2, suppose that just the sequential relationship changed of the state machine of coupling is as shown in Figure 9 in second address.
Claims (4)
1. a FF bus frame type identifier is located in the FF fieldbus data link layer, it is characterized in that comprising:
Decoding of frame control word and destination address receiver module; With the data-signal from fieldbus (rcv_data) that receives, data byte index signal (rcv_bytesyn) and reception effective index signal (raf_syn); Delta frame control signal (frame_cntrl), frame coded signal (frame_code), receive broadcast frame marking signal (rbmf), receive psa flag of frame signal (rpsaf), receive node address flag of frame signal (rnaf), receive NS address frame marking signal (ns), receive HL address frame marking signal (hl) and receive frame control word marking signal (rfcf), be transmitted to the upper strata processing unit of data link layer;
The matching addresses module; Address table data in the data link layer that receives (tab_data), local node are identified (node_id), Address Recognition mode enable signal (arme), receive error flag signal (ref) and carry out the matching addresses processing through the address date effective index signal that change-over circuit receives; Output table look-up end signal (tab_finish), matching addresses marking signal (amof), the table look-up upper strata processing unit of marking signal (ltaf) and address table end mark signal (etdf) to data link layer are indicated the result of matching addresses;
Change-over circuit is used for the address date effective index signal is carried out the sequential adjustment, and calculated address table data index signals (tab_bytesyn) are delivered to the matching addresses module, and the indication address date is effective.
2. by the described FF bus of claim 1 frame type identifier, it is characterized in that: said frame control word decoding and destination address receiver module comprise:
Frame control word latch, the data-signal (rcv_data) and the data byte index signal (rcv_bytesyn) of reception fieldbus latch the frame control word;
The counting comparison controller; Receive the data byte index signal (rcv_bytesyn) of fieldbus and receive effective index signal (raf_syn); Data byte index signal (rcv_bytesyn) is counted; Receive enable signal (addrget_en) according to count value delta frame control word latch enable signal (fclatch_en) and destination address; Deliver to frame control word latch and destination address receiver respectively, when count value reaches the destination address byte number of decoding logic circuit output, produce matching addresses enabling signal (addrmatch_start) to the matching addresses module;
Decoding logic circuit is deciphered the frame control word of frame control word latch output, exports the upper strata processing unit of all frame type informations (frame_code, rbmf, rpsaf, rnaf, ns and hl) to data link layer;
The destination address receiver, the data-signal and the data byte index signal (rcv_bytesyn) of reception fieldbus are extracted destination address (destaddr), and output destination address (destaddr) is to the matching addresses module.
3. by the described FF bus of claim 1 frame type identifier, it is characterized in that: said matching addresses module comprises: the address table data receiver module, the address comparison module, request postpones processing module, state machine and or door and with six modules of door:
The address table data receiver module receives the address table data in the data link layer, address table data is gone here and there and changed the back generate register signal and deliver to the address comparison module;
The address comparison module compares the frame control word decoding that receives and the destination address of destination address receiver module and the address table data of address table data receiver module, and calculated address match flag signal is delivered to the upper strata processing unit of data link layer;
Request postpones processing module, and the address table data effective index signal that receives is carried out delay process;
State machine, the signal of decoding of received frame control word and destination address receiver module generates control signal address table data reception module and address comparison module is controlled, and generates the upper strata processing unit that status signal is delivered to data link layer simultaneously;
Or door, the matching addresses marking signal of receiver address comparison module and address table end mark signal generate the upper strata processing unit that the end signal of tabling look-up exports data link layer to;
With door, the matching addresses marking signal of receiver address comparison module, address table end mark signal, the table look-up marking signal and the enable signal of tabling look-up generate the address table that the request signal of tabling look-up exports data link layer to.
4. by the described FF bus of claim 1 frame type identifier; It is characterized in that: said change-over circuit comprises the 1st～3 trigger (D1～D3) and XOR gate (XOR1); Wherein the input port of the 1st trigger (D1) is connected to the effective index signal of address table data; Export the input port of the 2nd trigger (D2) to; The output of the 2nd trigger (D2) links to each other with the input port of the 3rd trigger (D3), and XOR gate (XOR1) input links to each other with the output of the 2nd trigger (D2) and the output of the 3rd trigger (D3) respectively, and output is connected to the matching addresses module.
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| CN107741733B (en) * | 2017-08-08 | 2020-09-18 | 研祥智能科技股份有限公司 | Fieldbus system and fieldbus identification method |
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| US5142236A (en) * | 1989-10-16 | 1992-08-25 | Marelli Autronica Spa | Switched-capacitor circuit having a full-wave-rectifying and integrating function |
| CN1549065A (en) * | 2003-05-23 | 2004-11-24 | 中国科学院沈阳自动化研究所 | Control architecture for foundation fieldbus to reduce bus traffic |
| CN101159650A (en) * | 2007-11-29 | 2008-04-09 | 中控科技集团有限公司 | Control system including FF protocol H1 network segment and interface arrangement and communication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142236A (en) * | 1989-10-16 | 1992-08-25 | Marelli Autronica Spa | Switched-capacitor circuit having a full-wave-rectifying and integrating function |
| CN1549065A (en) * | 2003-05-23 | 2004-11-24 | 中国科学院沈阳自动化研究所 | Control architecture for foundation fieldbus to reduce bus traffic |
| CN101159650A (en) * | 2007-11-29 | 2008-04-09 | 中控科技集团有限公司 | Control system including FF protocol H1 network segment and interface arrangement and communication method |
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