CN104332543B - A kind of light-emitting diode chip for backlight unit and preparation method thereof - Google Patents
A kind of light-emitting diode chip for backlight unit and preparation method thereof Download PDFInfo
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- CN104332543B CN104332543B CN201410597607.2A CN201410597607A CN104332543B CN 104332543 B CN104332543 B CN 104332543B CN 201410597607 A CN201410597607 A CN 201410597607A CN 104332543 B CN104332543 B CN 104332543B
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- 238000002360 preparation method Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000003466 welding Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical class [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Manufacturing & Machinery (AREA)
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- Led Devices (AREA)
Abstract
The invention discloses a kind of light-emitting diode chip for backlight unit and preparation method thereof, belong to technical field of semiconductors.The light-emitting diode chip for backlight unit includes substrate, and it is sequentially laminated on the N-type layer on substrate, multiple quantum well layer, P-type layer, transparency conducting layer, the light-emitting diode chip for backlight unit is provided with the groove that N-type layer is extended to from P-type layer, passivation layer is laminated with N-type layer in transparency conducting layer and groove, P-type layer and transparency conducting layer are provided with the first annular groove that P-type layer is extended to from transparency conducting layer, p-type pad is provided with first annular groove, N-type layer in groove is provided with the second annular groove, N-type pad is provided with second annular groove, p-type pad and N-type pad include bottom and the top layer being layered on bottom, the thickness of the bottom of p-type pad is less than the depth of first annular groove, the thickness of the bottom of N-type pad is less than the depth of the second annular groove.The present invention effectively prevent p-type pad and N-type Pad off.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode chip and a manufacturing method thereof.
Background
The light emitting diode is a semiconductor solid light emitting device, can directly convert electric energy into light energy, has the advantages of energy conservation, environmental protection and the like, and is widely applied to the fields of illumination, backlight sources, displays, car lights and the like.
The light emitting diode chip is a core component of the light emitting diode, and the light emitting diode chip can be obtained after being packaged by organic matters such as epoxy resin and the like. The conventional light emitting diode chip comprises a substrate, an N-type layer, a multi-quantum well layer, a P-type layer, a transparent conductive layer, a P-type pad arranged on the transparent conductive layer, an N-type pad arranged on the N-type layer, and a passivation layer laminated on the transparent conductive layer and the N-type layer.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
p type pad and N type pad generally adopt Cr as the bottom metal of pad, and Cr is the metal that the nature is comparatively active, takes place chemical reaction with the water in the atmospheric environment easily, and then causes P type pad and N type pad on the emitting diode chip to drop, and the dead lamp phenomenon appears in emitting diode, has reduced emitting diode's life.
Disclosure of Invention
In order to solve the problem that the P-type bonding pad and the N-type bonding pad on the light emitting diode chip fall off in the prior art, the embodiment of the invention provides a light emitting diode chip and a manufacturing method thereof. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode chip, where the light emitting diode chip includes a substrate, and an N-type layer, a multiple quantum well layer, a P-type layer, and a transparent conductive layer sequentially stacked on the substrate, where a groove extending from the P-type layer to the N-type layer is formed on the light emitting diode chip, a passivation layer is stacked on the transparent conductive layer and the N-type layer in the groove, a first annular groove extending from the transparent conductive layer to the P-type layer is formed on the P-type layer and the transparent conductive layer, a P-type pad is disposed in the first annular groove, a second annular groove is formed on the N-type layer in the groove, an N-type pad is disposed in the second annular groove, the P-type pad and the N-type pad both include a bottom layer and a top layer stacked on the bottom layer, and a thickness of the bottom layer of the P-type pad is smaller than a, the thickness of the bottom layer of the N-type bonding pad is smaller than the depth of the second annular groove.
Optionally, the depth of the first annular groove is 0.5-1000nm, and the depth of the second annular groove is 0.5-1000 nm.
Optionally, the difference between the diameter of the P-type pad and the outer ring diameter of the first annular groove is 1-50 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second annular groove is 1-50 μm.
Optionally, the bottom layer is a Cr layer, and the top layer includes a Pt layer and an Au layer sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises a Ti layer and an Al layer which are sequentially laminated on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Pt layer and an Au layer which are sequentially stacked on the bottom layer.
In another aspect, an embodiment of the present invention provides a method for manufacturing a light emitting diode chip, where the method includes:
sequentially growing an N-type layer, a multi-quantum well layer and a P-type layer on a substrate;
forming a groove extending from the P-type layer to the N-type layer;
forming a first annular groove on the P-type layer, and forming a second annular groove on the N-type layer in the groove;
depositing a transparent conducting layer on the P-type layer, and etching off the transparent conducting layer in the first annular groove;
a P-type pad is arranged in the first annular groove, an N-type pad is arranged in the second annular groove, the P-type pad and the N-type pad respectively comprise a bottom layer and a top layer stacked on the bottom layer, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular groove, and the thickness of the bottom layer of the N-type pad is smaller than the depth of the second annular groove;
depositing a passivation layer on the transparent conductive layer and the N-type layer in the groove.
Optionally, the depth of the first annular groove is 0.5-1000nm, and the depth of the second annular groove is 0.5-1000 nm.
Optionally, the difference between the diameter of the P-type pad and the outer ring diameter of the first annular groove is 1-50 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second annular groove is 1-50 μm.
Optionally, the bottom layer is a Cr layer, and the top layer includes a Pt layer and an Au layer sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises a Ti layer and an Al layer which are sequentially laminated on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Pt layer and an Au layer which are sequentially stacked on the bottom layer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
through being equipped with the first annular groove that extends to the P type layer from transparent conducting layer on P type layer and the transparent conducting layer, the thickness that is equipped with the bottom of P type pad and P type pad on the first annular groove is less than the degree of depth of first annular groove, be equipped with the second annular groove on the N type layer in the recess, the thickness that is equipped with the bottom of N type pad and N type pad on the second annular groove is less than the degree of depth of second annular groove, the bottom of the P type pad in the first annular groove and the bottom of the N type pad in the second annular groove and the water among the atmospheric environment have effectively been avoided taking place chemical reaction, prevent to cause P type pad and N type pad on the emitting diode chip to drop, and the dead lamp phenomenon of emitting diode appears, emitting diode's life has been improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a light emitting diode chip according to a second embodiment of the present invention;
fig. 3a to fig. 3f are schematic structural diagrams of a light emitting diode chip provided in a second embodiment of the present invention in a process of manufacturing the light emitting diode chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
The embodiment of the invention provides a light emitting diode chip which can be manufactured by the method provided by the second embodiment, and referring to fig. 1, the light emitting diode chip comprises a substrate 1, an N-type layer 2, a multiple quantum well layer 3, a P-type layer 4, a transparent conducting layer 5, a P-type pad 6, an N-type pad 7 and a passivation layer 8.
In this embodiment, an N-type layer 2, a multiple quantum well layer 3, and a P-type layer 4 are sequentially stacked on a substrate 1, a groove extending from the P-type layer 4 to the N-type layer 2 is provided on a light emitting diode chip, and a transparent conductive layer is stacked on the P-type layer 4. The P-type layer 4 and the transparent conducting layer 5 are provided with first annular grooves extending from the transparent conducting layer 5 to the P-type layer 4, a P-type welding disc 6 is arranged in each first annular groove, a second annular groove is arranged on the N-type layer 2 in each groove, an N-type welding disc 7 is arranged in each second annular groove, each P-type welding disc 6 and each N-type welding disc 7 comprise a bottom layer (indicated by a shaded part in the figure) and a top layer stacked on the bottom layer, the thickness of the bottom layer of each P-type welding disc 6 is smaller than the depth of the corresponding first annular groove, and the thickness of the bottom layer of each N-type welding disc 7 is smaller than the depth of the corresponding. A passivation layer 8 is laminated on the transparent conductive layer 5 and the N-type layer 2 in the groove.
Specifically, the materials and thicknesses of the layers of the light emitting diode chip may include, but are not limited to, the following forms: the substrate 1 may be sapphire and the thickness of the substrate 1 may be 400 μm. The N-type layer 2 may be an N-type GaN layer, and the thickness of the N-type layer 2 may be4 μm. The multiple quantum well layer 3 may include InGaN layers and GaN layers alternately formed, and the InGaN layers may have a thickness of 0.1 μm. The thickness of the GaN layer may be 0.1 μm. The transparent conductive layer 5 may be ITO (Indium Tin Oxides), and the thickness of the transparent conductive layer 5 may be 0.24 μm. The passivation layer 8 may be SiO2The thickness of the passivation layer 8 may be 0.24 μm.
Alternatively, the outer ring diameter of the first ring groove may be 30 to 110 μm, the inner ring diameter of the first ring groove may be 30 to 110 μm, and the difference between the outer ring diameter of the first ring groove and the inner ring diameter of the first ring groove may be 2 to 40 μm. The outer ring diameter of the second annular groove may be 30 to 110 μm, the inner ring diameter of the second annular groove may be 30 to 110 μm, and a difference between the outer ring diameter of the second annular groove and the inner ring diameter of the second annular groove may be 2 to 40 μm.
Experiments prove that the outer ring diameter of the first annular groove, the inner ring diameter of the first annular groove, the outer ring diameter of the second annular groove and the inner ring diameter of the second annular groove are 30-110 microns, the sizes of the first annular groove, the second annular groove and the second annular groove can be matched with the sizes of the P-type welding disk 6 and the N-type welding disk 7, the sizes of the P-type welding disk 6 and the N-type welding disk 7 are not exceeded while the P-type welding disk 6 and the N-type welding disk 7 are protected, and therefore the bottom layer of the P-type welding disk arranged in the first annular groove and the bottom layer of the N-type welding disk arranged in the second annular groove are prevented from being in contact with air.
Preferably, the outer ring diameter of the first ring groove may be 50 to 100 μm, the inner ring diameter of the first ring groove may be 50 to 100 μm, and the difference between the outer ring diameter of the first ring groove and the inner ring diameter of the first ring groove may be 10 to 20 μm. The outer ring diameter of the second ring groove may be 50 to 100 μm, the inner ring diameter of the second ring groove may be 50 to 100 μm, and the difference between the outer ring diameter of the second ring groove and the inner ring diameter of the second ring groove may be 10 to 20 μm.
Experiments prove that the outer ring diameter of the first annular groove, the inner ring diameter of the first annular groove, the outer ring diameter of the second annular groove and the inner ring diameter of the second annular groove are 50-100 microns, and the P-type welding disk 6 and the N-type welding disk 7 can be effectively protected as much as possible. The difference between the outer ring diameter of the first annular groove and the inner ring diameter of the first annular groove and the difference between the outer ring diameter of the second annular groove and the inner ring diameter of the second annular groove are 10-20 microns, so that on one hand, the area of the first annular groove and the area of the second annular groove can be ensured to be small, the subsequent routing is prevented from being influenced, on the other hand, a certain width is also ensured between the inner diameter and the outer diameter of the first annular groove and the second annular groove, and the P-type welding disk 6 and the N-type welding disk 7 can be protected.
Alternatively, the depth of the first annular groove may be 0.5 to 1000nm, and the depth of the second annular groove may be 0.5 to 1000 nm.
Preferably, the depth of the first annular groove may be 10 to 500nm, and the depth of the second annular groove may be 10 to 500 nm.
Experiments prove that the depth of the first annular groove and the depth of the second annular groove are 10-500nm, so that the first annular groove and the second annular groove can be ensured to have certain depths, the P-type welding disk 6 and the N-type welding disk 7 can be protected, the thickness of the P-type layer 4 can be matched with the other side of the first annular groove, electric leakage is avoided, and normal light emitting of the light emitting diode is ensured.
Alternatively, the difference between the diameter of the P-type pad 6 and the outer ring diameter of the first annular groove may be 1 to 50 μm, and the difference between the diameter of the N-type pad 7 and the outer ring diameter of the second annular groove may be 1 to 50 μm.
Preferably, the difference between the diameter of the P-type pad 6 and the outer ring diameter of the first annular groove may be 1 to 10 μm, and the difference between the diameter of the N-type pad 7 and the outer ring diameter of the second annular groove may be 1 to 10 μm.
Experiments prove that the difference between the diameter of the P-type bonding pad 6 and the outer ring diameter of the first annular groove and the difference between the diameter of the N-type bonding pad 7 and the outer ring diameter of the second annular groove are 1-10 mu m, and the P-type bonding pad 6 and the N-type bonding pad 7 have better corrosion resistance.
It should be noted that, when the difference between the diameter of the P-type bonding pad 6 and the outer ring diameter of the first ring groove is greater than 0, the portion of the bottom layer of the P-type bonding pad 6 located outside the first ring groove is easily chemically reacted with water in the atmospheric environment, but since the thickness of the bottom layer of the P-type bonding pad 6 is smaller than the depth of the first ring groove, the portion of the bottom layer of the P-type bonding pad 6 located inside the first ring groove is disconnected from the portion of the bottom layer of the P-type bonding pad 6 located outside the first ring groove, and the chemical reaction of the portion of the bottom layer of the P-type bonding pad 6 located outside the first ring groove with water in the atmospheric environment does not extend to the portion of the bottom layer of the P-type bonding pad 6 located inside the first ring groove, so that the P-type bonding pad 6 does not fall off.
Similarly, when the difference between the diameter of the N-type pad 7 and the outer ring diameter of the second annular groove is greater than 0, the portion of the bottom layer of the N-type pad 7 located outside the second annular groove is easily chemically reacted with water in the atmospheric environment, but since the thickness of the bottom layer of the N-type pad 7 is smaller than the depth of the second annular groove, the portion of the bottom layer of the N-type pad 7 located inside the second annular groove is disconnected from the portion of the bottom layer of the N-type pad 7 located outside the second annular groove, and the chemical reaction of the portion of the bottom layer of the N-type pad 7 located outside the second annular groove with water in the atmospheric environment does not extend to the portion of the bottom layer of the N-type pad 7 located inside the second annular groove, so that the N-type pad 7 does not fall off.
In one implementation manner of this embodiment, the bottom layer may be a Cr layer, and the top layer may include a Pt layer and an Au layer sequentially stacked on the bottom layer.
In another implementation manner of the embodiment, the bottom layer may be a Cr layer, and the top layer may include a Ti layer and an Al layer sequentially stacked on the bottom layer.
In yet another implementation of the embodiment, the bottom layer may be a Cr layer, and the top layer may include an Al layer, a Cr layer, a Ti layer, and an Al layer sequentially stacked on the bottom layer.
In yet another implementation of the embodiment, the bottom layer may be a Cr layer, and the top layer may include an Al layer, a Cr layer, a Pt layer, and an Au layer sequentially stacked on the bottom layer.
Through a high-temperature high-humidity reliability test of the light-emitting diode chip, under the same condition, the P-type bonding pad and the N-type bonding pad of the light-emitting diode chip provided by the embodiment of the invention have no oxidation corrosion phenomenon, while the P-type bonding pad is arranged on the transparent conducting layer and the N-type bonding pad is arranged on the light-emitting diode chip on the N-type layer, the oxidation corrosion phenomenon (such as a dead light of the light-emitting diode) occurs, so that the light-emitting diode chip provided by the embodiment of the invention has good stability and long service life.
According to the embodiment of the invention, the first annular groove extending from the transparent conducting layer to the P-type layer is arranged on the P-type layer and the transparent conducting layer, the P-type pad is arranged on the first annular groove, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular groove, the second annular groove is arranged on the N-type layer in the groove, the N-type pad is arranged on the second annular groove, and the thickness of the bottom layer of the N-type pad is smaller than the depth of the second annular groove, so that the bottom layer of the P-type pad in the first annular groove and the bottom layer of the N-type pad in the second annular groove are effectively prevented from chemically reacting with water in the atmospheric environment, the P-type pad and the N-type pad on the light-emitting diode chip are prevented from falling off, the phenomenon of light-emitting diode.
Example two
The embodiment of the present invention provides a method for manufacturing a light emitting diode chip, which can be used for manufacturing the light emitting diode chip provided in the first embodiment, and with reference to fig. 2, the method for manufacturing includes:
step 201: and sequentially growing an N-type layer, a multi-quantum well layer and a P-type layer on the substrate.
Fig. 3a is a schematic structural diagram of the led chip obtained after step 201 is performed. In this figure, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, and 4 denotes a P-type layer.
Specifically, the step 201 may include:
an N-type layer, a multiple quantum well layer, and a P-type layer were sequentially grown on the substrate using MOCVD (Metal Organic Chemical Vapor Deposition) equipment.
Specifically, the materials and thicknesses of the layers of the light emitting diode chip may include, but are not limited to, the following forms: the substrate may be sapphire and the thickness of the substrate may be 400 μm. The N-type layer may be an N-type GaN layer, and the thickness of the N-type layer may be 4 μm. The multiple quantum well layer may include InGaN layers and GaN layers alternately formed, and the InGaN layers may have a thickness of 0.1 μm. The thickness of the GaN layer may be 0.1 μm.
Step 202: and a groove extending from the P-type layer to the N-type layer is formed.
Fig. 3b is a schematic structural diagram of the led chip obtained after step 202 is performed. In this figure, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, and 4 denotes a P-type layer.
Specifically, this step 202 may include:
and forming a groove extending from the P-type layer to the N-type layer by adopting a photoetching mask technology and a dry etching technology.
Step 203: a first annular groove is formed in the P-type layer, and a second annular groove is formed in the N-type layer in the groove.
Fig. 3c is a schematic structural diagram of the led chip obtained after step 203 is performed. In this figure, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, and 4 denotes a P-type layer.
Specifically, the step 203 may include:
and forming a first annular groove on the P-type layer by adopting a photoetching mask technology and a dry etching technology, and forming a second annular groove on the N-type layer in the groove.
Alternatively, the outer ring diameter of the first ring groove may be 30 to 110 μm, the inner ring diameter of the first ring groove may be 30 to 110 μm, and the difference between the outer ring diameter of the first ring groove and the inner ring diameter of the first ring groove may be 2 to 40 μm. The outer ring diameter of the second annular groove may be 30 to 110 μm, the inner ring diameter of the second annular groove may be 30 to 110 μm, and a difference between the outer ring diameter of the second annular groove and the inner ring diameter of the second annular groove may be 2 to 40 μm.
Preferably, the outer ring diameter of the first ring groove may be 50 to 100 μm, the inner ring diameter of the first ring groove may be 50 to 100 μm, and the difference between the outer ring diameter of the first ring groove and the inner ring diameter of the first ring groove may be 10 to 20 μm. The outer ring diameter of the second ring groove may be 50 to 100 μm, the inner ring diameter of the second ring groove may be 50 to 100 μm, and the difference between the outer ring diameter of the second ring groove and the inner ring diameter of the second ring groove may be 10 to 20 μm.
Alternatively, the depth of the first annular groove may be 0.5 to 1000nm, and the depth of the second annular groove may be 0.5 to 1000 nm.
Preferably, the depth of the first annular groove may be 10 to 500nm, and the depth of the second annular groove may be 10 to 500 nm.
Step 204: and depositing a transparent conducting layer on the P-type layer, and etching off the transparent conducting layer in the first annular groove.
Fig. 3d is a schematic structural diagram of the led chip obtained after step 204 is performed. In this figure, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, 4 denotes a P-type layer, and 5 denotes a transparent conductive layer.
Specifically, this step 204 may include:
depositing a transparent conducting layer on the P-type layer and the N-type layer in the groove by adopting a magnetron sputtering technology;
and etching the transparent conducting layer in the first annular groove and the transparent conducting layer on the N-type layer in the groove by using hydrochloric acid.
It is understood that after the transparent conductive layer in the first annular groove is etched away, the first annular groove becomes a groove formed on the P-type layer and the transparent conductive layer and extending from the transparent conductive layer to the P-type layer.
Specifically, the transparent conductive layer may be ITO, and the thickness of the transparent conductive layer 5 may be 0.24 μm.
Step 205: the first annular groove is internally provided with a P-type bonding pad, the second annular groove is internally provided with an N-type bonding pad, the P-type bonding pad and the N-type bonding pad respectively comprise a bottom layer and a top layer stacked on the bottom layer, the thickness of the bottom layer of the P-type bonding pad is smaller than the depth of the first annular groove, and the thickness of the bottom layer of the N-type bonding pad is smaller than the depth of the second annular groove.
Fig. 3e is a schematic structural diagram of the led chip obtained after step 205 is performed. In the drawings, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, 4 denotes a P-type layer, 5 denotes a transparent conductive layer, 6 denotes a P-type pad (bottom layer is shaded), and 7 denotes an N-type pad (bottom layer is shaded).
Specifically, the step 205 may include:
the electron beam evaporation technology is adopted to arrange a P-type pad in the first annular groove, an N-type pad is arranged in the second annular groove, the P-type pad and the N-type pad both comprise a bottom layer and a top layer stacked on the bottom layer, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular groove, and the thickness of the bottom layer of the N-type pad is smaller than the depth of the second annular groove.
Alternatively, the difference between the diameter of the P-type pad and the outer ring diameter of the first ring groove may be 1-50 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second ring groove may be 1-50 μm.
Preferably, the difference between the diameter of the P-type pad and the outer ring diameter of the first ring-shaped groove may be 1-10 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second ring-shaped groove may be 1-10 μm.
In one implementation manner of this embodiment, the bottom layer may be a Cr layer, and the top layer may include a Pt layer and an Au layer sequentially stacked on the bottom layer.
In another implementation manner of this embodiment, the bottom layer may be a Cr layer, and the top layer may include a Ti layer and an Al layer sequentially stacked on the bottom layer.
In yet another implementation manner of the embodiment, the bottom layer may be a Cr layer, and the top layer may include an Al layer, a Cr layer, a Ti layer, and an Al layer sequentially stacked on the bottom layer.
In yet another implementation manner of the embodiment, the bottom layer may be a Cr layer, and the top layer may include an Al layer, a Cr layer, a Pt layer, and an Au layer sequentially stacked on the bottom layer.
Step 206: and depositing a passivation layer on the transparent conductive layer and the N-type layer in the groove.
Fig. 3f is a schematic structural diagram of the led chip obtained after step 205 is performed. In the drawings, 1 denotes a substrate, 2 denotes an N-type layer, 3 denotes a multiple quantum well layer, 4 denotes a P-type layer, 5 denotes a transparent conductive layer, 6 denotes a P-type pad (bottom layer is shaded), 7 denotes an N-type pad (bottom layer is shaded), and 8 denotes a passivation layer.
In particular, the passivation layer 8 may be SiO2The thickness of the passivation layer 8 may be 0.24 μm.
It should be noted that after the passivation layer is deposited on the transparent conductive layer and the N-type layer in the groove, the passivation layer covers the P-type pad and the N-type pad, and the passivation layer on the P-type pad and the N-type pad can be etched away by using a photolithography mask technique, so that the light emitting diode can be normally wired and emit light subsequently.
According to the embodiment of the invention, the first annular groove extending from the transparent conducting layer to the P-type layer is arranged on the P-type layer and the transparent conducting layer, the P-type pad is arranged on the first annular groove, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular groove, the second annular groove is arranged on the N-type layer in the groove, the N-type pad is arranged on the second annular groove, and the thickness of the bottom layer of the N-type pad is smaller than the depth of the second annular groove, so that the bottom layer of the P-type pad in the first annular groove and the bottom layer of the N-type pad in the second annular groove are effectively prevented from chemically reacting with water in the atmospheric environment, the P-type pad and the N-type pad on the light-emitting diode chip are prevented from falling off, the phenomenon of light-emitting diode.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A light emitting diode chip comprises a substrate, and an N-type layer, a multi-quantum well layer, a P-type layer and a transparent conducting layer which are sequentially stacked on the substrate, wherein a groove extending from the P-type layer to the N-type layer is formed in the light emitting diode chip, a passivation layer is stacked on the transparent conducting layer and the N-type layer in the groove, the light emitting diode chip is characterized in that a first annular groove extending from the transparent conducting layer to the P-type layer is formed in the P-type layer and the transparent conducting layer, a P-type pad is arranged in the first annular groove, a second annular groove is formed in the N-type layer in the groove, an N-type pad is arranged in the second annular groove, the P-type pad and the N-type pad both comprise a bottom layer and a top layer stacked on the bottom layer, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular, the thickness of the bottom layer of the N-type bonding pad is smaller than the depth of the second annular groove.
2. The light-emitting diode chip of claim 1, wherein the depth of the first annular groove is 0.5-1000nm, and the depth of the second annular groove is 0.5-1000 nm.
3. The light-emitting diode chip as claimed in claim 1 or 2, wherein the difference between the diameter of the P-type pad and the outer ring diameter of the first ring-shaped groove is 1-50 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second ring-shaped groove is 1-50 μm.
4. The light-emitting diode chip as claimed in claim 1 or 2, wherein said bottom layer is a Cr layer, and said top layer comprises a Pt layer and an Au layer sequentially stacked on said bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises a Ti layer and an Al layer which are sequentially laminated on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Pt layer and an Au layer which are sequentially stacked on the bottom layer.
5. A manufacturing method of a light emitting diode chip is characterized by comprising the following steps:
sequentially growing an N-type layer, a multi-quantum well layer and a P-type layer on a substrate;
forming a groove extending from the P-type layer to the N-type layer;
forming a first annular groove on the P-type layer, and forming a second annular groove on the N-type layer in the groove;
depositing a transparent conducting layer on the P-type layer, and etching off the transparent conducting layer in the first annular groove;
a P-type pad is arranged in the first annular groove, an N-type pad is arranged in the second annular groove, the P-type pad and the N-type pad respectively comprise a bottom layer and a top layer stacked on the bottom layer, the thickness of the bottom layer of the P-type pad is smaller than the depth of the first annular groove, and the thickness of the bottom layer of the N-type pad is smaller than the depth of the second annular groove;
depositing a passivation layer on the transparent conductive layer and the N-type layer in the groove.
6. The method of claim 5, wherein the first annular groove has a depth of 0.5-1000nm, and the second annular groove has a depth of 0.5-1000 nm.
7. The method as claimed in claim 5 or 6, wherein the difference between the diameter of the P-type pad and the outer ring diameter of the first ring-shaped groove is 1-50 μm, and the difference between the diameter of the N-type pad and the outer ring diameter of the second ring-shaped groove is 1-50 μm.
8. The manufacturing method according to claim 5 or 6, wherein the bottom layer is a Cr layer, and the top layer comprises a Pt layer and an Au layer which are sequentially laminated on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises a Ti layer and an Al layer which are sequentially laminated on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially stacked on the bottom layer; or,
the bottom layer is a Cr layer, and the top layer comprises an Al layer, a Cr layer, a Pt layer and an Au layer which are sequentially stacked on the bottom layer.
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| CN102945902A (en) * | 2012-12-11 | 2013-02-27 | 东南大学 | Light-emitting diode of photonic crystal structure and application thereof |
| CN103682023A (en) * | 2013-12-30 | 2014-03-26 | 杭州士兰明芯科技有限公司 | LED (Light Emitting Diode) structure and electrode formation method thereof |
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| CN101702420A (en) * | 2009-10-15 | 2010-05-05 | 厦门市三安光电科技有限公司 | Manufacturing method of film GaN base luminescent device with inversed N electrode distribution |
| CN102364707A (en) * | 2011-11-28 | 2012-02-29 | 江苏新广联科技股份有限公司 | Lighting emitting diode (LED) chip structure capable of improving current transmission clogging |
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