CN104282698B - Two-stage packaging method for image sensor - Google Patents

Two-stage packaging method for image sensor Download PDF

Info

Publication number
CN104282698B
CN104282698B CN201310311466.9A CN201310311466A CN104282698B CN 104282698 B CN104282698 B CN 104282698B CN 201310311466 A CN201310311466 A CN 201310311466A CN 104282698 B CN104282698 B CN 104282698B
Authority
CN
China
Prior art keywords
sensor chip
cis
adhesive
adhesive layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310311466.9A
Other languages
Chinese (zh)
Other versions
CN104282698A (en
Inventor
黄俊龙
杜修文
吴承昌
杨崇佑
王荣昌
杨若薇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tong Hsing Electronic Industries Ltd
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to CN201710971596.3A priority Critical patent/CN107742630B/en
Publication of CN104282698A publication Critical patent/CN104282698A/en
Application granted granted Critical
Publication of CN104282698B publication Critical patent/CN104282698B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention relates to a two-stage packaging method of an image sensor, which comprises the following steps: providing a substrate, fixedly arranging a sensor chip on the substrate, fixedly arranging a transparent plate on the sensor chip, electrically connecting the substrate and the sensor chip, forming a first adhesive layer and forming a second adhesive layer. The manufacturing method of the invention adopts a two-stage packaging mode, avoids the defects that the yield of the packaging and manufacturing process of the image sensor or the sensing sensitivity of the image sensor is influenced or the sensing sensitivity of the image sensor is caused by the displacement or damage of the sensor chip or the lead wire for electrical connection or the pollution of the sensor chip protected by the transparent plate body due to the excessive pressure generated when the sealing glue layer is formed in the packaging and manufacturing process of the image sensor, thereby improving the quality and the yield of the packaging and manufacturing process of the sensor and reducing the manufacturing cost of the sensor package.

Description

CIS two-stage method for packing
Technical field
The present invention is, on a kind of image sensor package method, to be encapsulated especially with regard to a kind of CIS two-stage Method.
Background technology
In known technology, in order to protect the lead of CIS chip and connection CIS chip and substrate, One layer of adhesive body (encapsulant) can be all manufactured on CIS chip and lead in model mode.
But known sealing manufacturing method, but often because the pressure that adhesive body is produced in model mode, makes image sense Survey device chip or lead produces displacement or fracture or sealing overflows into and polluted the sensor chip protected by transparent plate body, influence shadow As sensor chip normal function and cause the pollution of sensing area in CIS chip, CIS envelope is greatly reduced The yield of dress.
Therefore, how to develop it is a kind of can be effectively by the image sensor package method of low adhesive body model pressure, just It is turned into an important development problem of semiconductor today and CIS industry, research and development and manufacture.
The content of the invention
It is an object of the invention to provide a kind of CIS two-stage method for packing, it can be avoided because image sense Survey in device package fabrication process and produce excessive pressure when forming adhesive layer, cause sensor chip or the lead of electric connection Displacement or damage are produced, and influences the sensing sensitivity of the yield or CIS of CIS package fabrication process in itself Defect.
The object of the invention to solve the technical problems is realized using following technical scheme.According to present invention proposition CIS two-stage method for packing, it comprises the following steps：Substrate is provided, the substrate has：First surface；And second Surface, it is relative with the first surface；Fixed sensor chip on the substrate, its be by the sensor chip be fixedly arranged on this On one surface, and the sensor chip has sensing area；Fixed transparent plate body is on the sensor chip, the wherein transparent panel Body is combined by intermediate with the sensor chip, so that the transparent plate body and sensor chip chamber formation confined space, The intermediate is on the outside of the sensing area again and the sensing area is located among the confined space；It is electrically connected with the substrate and the sense Device chip is surveyed, it is to be electrically connected with the substrate and the sensor chip by multiple leads, and those leads are located in the middle of this The outside of thing；The first adhesive layer is formed, it is that the sensor on the outside of those leads and the intermediate is coated with the first adhesive body The first surface beyond chip upper surface and the sensor chip position, and first adhesive body is solidify to form first envelope Glue-line, wherein first adhesive layer are coated to a part for the transparent panel body side surface, and the height of the first adhesive layer upper surface Less than the height of the upper surface of the transparent plate body；And formed the second adhesive layer, its be with the second adhesive body be covered in this first Outside adhesive layer, and second adhesive body is set to solidify to form second adhesive layer, but second adhesive layer coats the transparent plate body The remainder of side, and the second adhesive layer upper surface and the transparent plate body upper surface is contour and copline.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing CIS two-stage method for packing, the wherein substrate are plastic base or ceramic substrate, and are had Multiple conductive connecting pins are fixedly arranged on the second surface.
Foregoing CIS two-stage method for packing, wherein the sensor chip are CMOS sensors chip or should The chip that CMOS sensor chip combination electronic circuits are formed.
Foregoing CIS two-stage method for packing, the wherein material of the intermediate are glass or plastics, and are somebody's turn to do The upper and lower ends of intermediate are touched by adhesive agent and the sensor chip and the transparent panel body phase respectively.
Foregoing CIS two-stage method for packing, the wherein intermediate are molded institute for liquid crystal polymer material pressing mold Formed, and the upper and lower ends of the intermediate are touched by adhesive agent and the sensor chip and the transparent panel body phase respectively.
Foregoing CIS two-stage method for packing, the wherein intermediate are that heat cure viscose or ultraviolet light solidification are glutinous Glue or the polyimides or amide resin for having adherence, and the transparent plate body is attached to this by the process for solidifying the intermediate Sensor chip.
Foregoing CIS two-stage method for packing, the wherein height of the confined space between 100um to 500um it Between.
Foregoing CIS two-stage method for packing, wherein first adhesive body are epoxy resin (Epoxy).
Foregoing CIS two-stage method for packing, wherein second adhesive body are heat cure adhesive body.
By above-mentioned technical proposal, CIS two-stage method for packing of the present invention at least has following advantages and beneficial Effect：
First, the influence that effectively reduction adhesive body model pressure is produced to CIS and lead；And
2nd, yield, quality and the yield of CIS package fabrication process are improved, and reduces manufacturing cost.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention, And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Fig. 1 is a kind of CIS two-stage method for packing flow chart of steps of the embodiment of the present invention；
Fig. 2A is a kind of substrate sectional view of the embodiment of the present invention；
Fig. 2 B are the sectional view that a kind of CIS chip of the embodiment of the present invention is fixedly arranged on substrate；
Fig. 2 C for structure fixed transparent plate body again as shown in Figure 2 B embodiment sectional view；
The embodiment sectional view that Fig. 2 D again connect CIS chip and electrical property of substrate for structure as that shown in fig. 2 c；
Fig. 2 E re-form the embodiment sectional view of one first adhesive layer for structure as shown in Figure 2 D；
Fig. 2 F are that a kind of structure as shown in Figure 2 E of the embodiment of the present invention re-forms one second adhesive layer, become image A kind of sectional view of CIS packaging body manufactured by sensor two-stage method for packing；And
Fig. 3 is another CIS manufactured by a kind of CIS two-stage method for packing of the embodiment of the present invention Packaging body sectional view.
10：Substrate
11：First surface 1：Second surface
13：Conductive connecting pin 20：Sensor chip
21：Sensing area 30：Transparent plate body
40：Intermediate 41：Adhesive agent
50：Confined space
H：The height of confined space
60：Lead 61：Joint
70：First adhesive layer 80：Second adhesive layer
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with Accompanying drawing and preferred embodiment, to according to CIS two-stage method for packing proposed by the present invention its embodiment, side Method, step, feature and its effect, are described in detail as after.
As shown in figure 1, a kind of CIS two-stage method for packing S100 of the present embodiment comprises the following steps：Base is provided Plate (step S10)；Fixed sensor chip is in (step S20) on substrate；Fixed transparent plate body is in (step on sensor chip S30)；It is electrically connected with substrate and sensor chip (step S40)；Form the first adhesive layer (step S50)；And form the second sealing Layer (step S60).
As shown in Figure 1, Figure 2 shown in A, Fig. 2 F and Fig. 3 there is provided substrate (step S10), wherein substrate 10 have first surface 11 and Second surface 12, second surface 12 is relative with first surface 11.Substrate 10 can be plastic base or ceramic substrate, and substrate 10 There can be multiple conductive connecting pins 13 to be fixedly arranged on second surface 12, those conductive connecting pins 13 can be as CIS chip 20 Or the purposes that the circuit on substrate 10 is connected with the exposed electrical of substrate 10.
As shown in Figure 1, Figure 2 shown in B, Fig. 2 F and Fig. 3, fixed sensor chip is in (step S20) on substrate, and it is by sensor Chip 20 is fixedly arranged on the first surface 11 of substrate 10.Sensor chip 20 and with sensing area 21, as sensor chip The 20 signal input area to be sensed.Sensor chip 20 can be CMOS sensors chip or CMOS sensor chips The chip formed with reference to electronic circuit.
As shown in Figure 1, Figure 2 shown in C, Fig. 2 F and Fig. 3, fixed transparent plate body is on sensor chip (step S30), and it is will be saturating Isotropic disk body 30 is combined by intermediate 40 with sensor chip 20, so as to form close between transparent plate body 30 and sensor chip 20 Close space 50.Wherein, intermediate 40 is around the outside of sensing area 21 and sensing area 21 is located among confined space 50.
As shown in Fig. 2 C to Fig. 3, transparent plate body 30 can be the material such as clear glass or transparent resin or transparent plastic institute Formed, the signal to be sensed of sensor chip 20 can penetrate transparent plate body 30 and sensed area 21 is received.When intermediate 40 Material is formed by glass or plastics or polyimides (Polyimide) or amide resin (Amide Resin), or by liquid crystal When the shaping of polymer (LCP, Liquid Crystal Polymer) material pressing mold is formed, the upper and lower ends of intermediate 40 are also divided Do not touched mutually with sensor chip 20 and transparent plate body 30 by adhesive agent 41.
As shown in figure 3, intermediate 40 can also be heat cure viscose (Heat Curable Adhesive) or UV-curing Change viscose (UV Curable Adhesive) or have the polyimides or amide resin of adherence, and by solidification intermediate 40 Process transparent plate body 30 is attached to sensor chip 20.Therefore when intermediate 40 is that heat cure viscose or ultraviolet light solidification are glutinous During glue, just it is not necessary to reuse adhesive agent 41, you can intermediate 40 with sensor chip 20 and transparent plate body 30 is mutually touched.
As shown in Fig. 2 C, Fig. 2 F and Fig. 3, the confined air that intermediate 40, transparent plate body 30 are surrounded with sensor chip 20 Between in 50, the vertical range between its transparent plate body 30 and sensor chip 20 is the height H of confined space, and the height of confined space Fixed transparent plate body can carried out when (step S30) on sensor chip by spending H, and the size by selection intermediate 40 is big It is small, the height H that user determines confined space according to the sensing demand of sensor chip 20 can be provided.
The height H of confined space 50 as shown in Fig. 2 C and Fig. 2 F, can select between 100um between 500um (um= Micron, 10-6Rice).
As shown in Figure 1, Figure 2 shown in D, Fig. 2 F and Fig. 3, it is by will be many to be electrically connected with substrate and sensor chip (step S40) The joint 61 at the individual two ends of lead 60 is respectively connecting to substrate 10 and sensor chip 20, so that substrate 10 and the phase of sensor chip 20 Mutually electrically connect, and those leads 60 and joint 61 are all located at the outside of intermediate 40, that is, those leads 60 and joint 61 are Outside confined space 50.Wherein, those leads 60 can be golden (Au) line, Jin Yuyin or gold and copper mixed material The electric lead of formation.
As shown in Figure 1, Figure 2 shown in E, Fig. 2 F and Fig. 3, the first adhesive layer (step S50) is formed, it is coated with the first adhesive body The upper surface of sensor chip 20 and the position of sensor chip 20 in those leads 60 and the outside of those joints 61 and intermediate 40 with Outer first surface 11, and the first adhesive body is solidify to form the first adhesive layer 70, wherein the first adhesive layer 70 can be coated to saturating A part for the side of isotropic disk body 30, and height of the height less than the transparent upper surface of plate body 30 of the upper surface of the first adhesive layer 70.
First adhesive body can be epoxy resin (Epoxy), and the first adhesive body can be in dispensing (dispensing) mode Insert to coat those leads 60, the joint 61 at the two ends of lead 60, the upper surface of sensor chip 20 in the outside of intermediate 40 and sense The first surface 11 surveyed beyond the position of device chip 20, and when inserting, the first adhesive body is still liquid colloidal material, and because Usage quantity is not required to be filled up to contour with transparent plate body 30, and the pressure that it is produced is also relatively small, more because also with flowable, So the influence to lead 60, the joint 61 at the two ends of lead 60 or sensor chip 20 is also smaller, and the first adhesive body solidifies After the first adhesive layer 70, effect of all components in the first adhesive layer 70 of protection is can reach again, all components refer to foregoing Those leads 60, the joint 61 at the two ends of lead 60, the upper surface of sensor chip 20 in the outside of intermediate 40 and sensor chip 20 First surface 11 beyond position.
As shown in Figure 1, Figure 2 shown in F and Fig. 3, the second adhesive layer (step S60) is formed, it is to be covered in the with the second adhesive body Outside one adhesive layer 70, and the second adhesive body is set to solidify to form the second adhesive layer 80, but the second adhesive layer 80 is coated to transparent panel The remainder of the side of body 30, the upper surface of the second adhesive layer 80 is and the upper surface of transparent plate body 30 is contour and copline.
As shown in Fig. 2 E, Fig. 2 F and Fig. 3, the side of the first adhesive layer 70 and the second adhesive layer 80 all can be with substrate 10 Side is trimmed.
Due to being solidify to form in the first adhesive body after the first adhesive layer 70, the second adhesive body is just covered in the first sealing Outside layer 70, all components that the first adhesive layer 70 is covered and protected just will not be because of the second adhesive layer (step S60) of formation The pressure of generation and it is impacted.
Second adhesive body can be heat cure adhesive body, and it can select different materials according to different application demands again Or color, it is light tight to avoid doing to reach when using CIS two-stage method for packing S100 in the present embodiment Sensing function is disturbed, black can be selected or the material or color of printing opacity is difficult.
In summary, the CIS two-stage method for packing S100 described in the present embodiment, due to the first adhesive layer 70 And second adhesive layer 80 be to be encapsulated with the two-stage, the bad shadow produced to lead 60 or sensor chip 20 by pressure is greatly reduced Ring, yield, quality and the yield of CIS package fabrication process can be improved, and reduce manufacturing cost.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification For the equivalent embodiment of equivalent variations, as long as being the technical spirit pair according to the present invention without departing from technical solution of the present invention content Any simple modification, equivalent variations and modification that above example is made, in the range of still falling within technical solution of the present invention.

Claims (9)

1. a kind of CIS two-stage method for packing, it is characterised in that it comprises the following steps：
Substrate is provided, the substrate has：First surface；And second surface, it is relative with the first surface；
Fixed sensor chip is on the substrate, and it is that the sensor chip is fixedly arranged on the first surface, and the sensing Device chip has sensing area；
Fixed transparent plate body is on the sensor chip, and wherein the transparent plate body is mutually tied by intermediate with the sensor chip Close, so that the transparent plate body and sensor chip chamber formation confined space, and the intermediate is on the outside of the sensing area and makes The sensing area is located among the confined space；
The substrate and the sensor chip are electrically connected with, it is to be electrically connected with the substrate and the sensor core by multiple leads Piece, and those leads are located at the outside of the intermediate；
First adhesive layer is formed with dispensing, it is that the sensor on the outside of those leads and the intermediate is coated with the first adhesive body The first surface beyond chip upper surface and the sensor chip position, and first adhesive body is solidify to form first envelope Glue-line, wherein first adhesive layer are coated to a part for the transparent panel body side surface, and the height of the first adhesive layer upper surface Less than the height of the upper surface of the transparent plate body；And
With mould model the second adhesive layer of formation, it is to be covered in the second adhesive body outside first adhesive layer, and make this Two adhesive bodies solidify to form the remainder that the relief of second adhesive layer second adhesive layer coats the transparent panel body side surface, and Make the upper surface of the second adhesive layer upper surface and the transparent plate body contour and copline.
2. CIS two-stage method for packing as claimed in claim 1, it is characterised in that the substrate be plastic base or Ceramic substrate, and be fixedly arranged on multiple conductive connecting pins on the second surface.
3. CIS two-stage method for packing as claimed in claim 1, it is characterised in that the sensor chip is CMOS The chip that sensor chip or the CMOS sensor chip combination electronic circuits are formed.
4. CIS two-stage method for packing as claimed in claim 1, it is characterised in that the material of the intermediate is glass Glass or plastics, and the upper and lower ends of the intermediate are close by adhesive agent and the sensor chip and the transparent panel body phase respectively Connect.
5. CIS two-stage method for packing as claimed in claim 1, it is characterised in that the intermediate is polymerizable mesogenic The shaping of thing material pressing mold is formed, and the intermediate upper and lower ends respectively by adhesive agent and the sensor chip and this is saturating Isotropic disk body phase is touched.
6. CIS two-stage method for packing as claimed in claim 1, it is characterised in that the intermediate is glutinous for heat cure Glue or ultraviolet light solidification viscose or the polyimides or amide resin that have adherence, and should by the process for solidifying the intermediate Transparent plate body is attached to the sensor chip.
7. the CIS two-stage method for packing as described in any one of claim 4-6 claim, it is characterised in that should The height of confined space is between 100um between 500um.
8. CIS two-stage method for packing as claimed in claim 1, it is characterised in that first adhesive body is epoxy Resin.
9. CIS two-stage method for packing as claimed in claim 1, it is characterised in that second adhesive body is thermosetting Change adhesive body.
CN201310311466.9A 2013-07-08 2013-07-23 Two-stage packaging method for image sensor Active CN104282698B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710971596.3A CN107742630B (en) 2013-07-08 2013-07-23 Image sensor packaging structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW102124442 2013-07-08
TW102124442A TW201503334A (en) 2013-07-08 2013-07-08 Two-stage packaging method of image sensors

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201710971596.3A Division CN107742630B (en) 2013-07-08 2013-07-23 Image sensor packaging structure

Publications (2)

Publication Number Publication Date
CN104282698A CN104282698A (en) 2015-01-14
CN104282698B true CN104282698B (en) 2017-10-20

Family

ID=52133071

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201710971596.3A Active CN107742630B (en) 2013-07-08 2013-07-23 Image sensor packaging structure
CN201310311466.9A Active CN104282698B (en) 2013-07-08 2013-07-23 Two-stage packaging method for image sensor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201710971596.3A Active CN107742630B (en) 2013-07-08 2013-07-23 Image sensor packaging structure

Country Status (5)

Country Link
US (1) US8969120B2 (en)
JP (1) JP5635661B1 (en)
KR (1) KR101467699B1 (en)
CN (2) CN107742630B (en)
TW (1) TW201503334A (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165794B1 (en) * 2014-07-31 2015-10-20 Himax Display, Inc. Partial glob-top encapsulation technique
FR3029687A1 (en) 2014-12-09 2016-06-10 Stmicroelectronics (Grenoble 2) Sas METHOD FOR MANUFACTURING ELECTRONIC DEVICES AND ELECTRONIC DEVICE WITH DOUBLE ENCAPSULATION RING
US9711425B2 (en) 2015-08-20 2017-07-18 Xintec Inc. Sensing module and method for forming the same
KR102185063B1 (en) 2015-08-31 2020-12-01 삼성전기주식회사 Sensing package and manufacturing method for the same
KR102152516B1 (en) * 2016-03-28 2020-09-04 닝보 써니 오포테크 코., 엘티디. Camera module and molded photosensitive assembly, manufacturing method thereof, and electronic device
CN107591420B (en) * 2016-07-06 2020-02-18 胜丽国际股份有限公司 Sensor package structure
US10692917B2 (en) * 2016-07-06 2020-06-23 Kingpak Technology Inc. Sensor package structure
EP3267485B1 (en) * 2016-07-06 2020-11-18 Kingpak Technology Inc. Sensor package structure
EP3267486B1 (en) * 2016-07-06 2020-12-30 Kingpak Technology Inc. Sensor package structure
CN107611147B (en) 2016-07-11 2020-02-18 胜丽国际股份有限公司 Multi-chip plastic ball array packaging structure
US10340250B2 (en) * 2017-08-15 2019-07-02 Kingpak Technology Inc. Stack type sensor package structure
CN109411487B (en) * 2017-08-15 2020-09-08 胜丽国际股份有限公司 Stacked sensor package structure
TWI640073B (en) * 2017-08-16 2018-11-01 勝麗國際股份有限公司 Sensor package structure
US11561330B2 (en) 2018-03-19 2023-01-24 Tdk Taiwan Corp. Photosensitive module having transparent plate and image sensor
US11081510B2 (en) 2018-03-19 2021-08-03 Tdk Taiwan Corp. Photosensitive module having transparent plate and image sensor
KR101967261B1 (en) 2018-05-28 2019-08-13 테라셈 주식회사 Image sensor package and manufacturing method thereof
JP2020036216A (en) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging apparatus and method of manufacturing the same
US11177301B2 (en) 2018-11-19 2021-11-16 UTAC Headquarters Pte. Ltd. Reliable semiconductor packages
TWI685922B (en) 2019-02-22 2020-02-21 勝麗國際股份有限公司 Chip-scale sensor package structure
CN111627866B (en) * 2019-02-27 2022-03-04 胜丽国际股份有限公司 Chip-level sensor packaging structure
CN111769125B (en) * 2019-04-02 2023-08-01 同欣电子工业股份有限公司 Sensor package structure
CN110021619A (en) * 2019-05-17 2019-07-16 积高电子(无锡)有限公司 Image sensor package structure and packaging method
CN110112163A (en) * 2019-05-17 2019-08-09 积高电子(无锡)有限公司 A kind of image sensor package structure and packaging method
KR102081612B1 (en) 2019-11-25 2020-05-15 테라셈 주식회사 Semiconductor package and method for manufacturing the same
KR102110143B1 (en) 2019-11-25 2020-05-13 테라셈 주식회사 Image sensor package and manufacturing method thereof
KR20210080718A (en) 2019-12-20 2021-07-01 삼성전자주식회사 Semiconductor aarckage
US20210246015A1 (en) * 2020-02-06 2021-08-12 Advanced Semiconductor Engineering, Inc. Sensor device package and method for manufacturing the same
TWI721815B (en) * 2020-03-10 2021-03-11 勝麗國際股份有限公司 Sensor package structure
TWI721837B (en) * 2020-03-26 2021-03-11 勝麗國際股份有限公司 Sensor package structure
US11869912B2 (en) * 2020-07-15 2024-01-09 Semiconductor Components Industries, Llc Method for defining a gap height within an image sensor package
CN115997288A (en) * 2020-09-07 2023-04-21 索尼半导体解决方案公司 Semiconductor device, method of manufacturing the same, and electronic apparatus
KR20220051470A (en) 2020-10-19 2022-04-26 삼성전자주식회사 Semiconductor package and method of fabricating the same
TWI769780B (en) * 2021-04-12 2022-07-01 勝麗國際股份有限公司 Sensor package structure
JP2022189647A (en) * 2021-06-11 2022-12-22 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device and electronic apparatus
US11798967B2 (en) * 2021-10-06 2023-10-24 Stmicroelectronics Asia Pacific Pte Ltd Image sensor package with transparent adhesive covering the optical sensing circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0951009A (en) * 1995-08-07 1997-02-18 Dainippon Printing Co Ltd Resin sealing of ic module, ic module, and ic card
CN1758422A (en) * 2004-10-09 2006-04-12 北京七星华创电子股份有限公司 Optically coupled packaging method for thick film printing circuit
CN1905144A (en) * 2005-05-27 2007-01-31 阿瓦戈科技通用Ip(新加坡)股份有限公司 Methods for packaging an image sensor and a packaged image sensor
CN101950751A (en) * 2009-07-10 2011-01-19 菱光科技股份有限公司 Image sensor and encapsulating method thereof
CN102589753A (en) * 2011-01-05 2012-07-18 飞思卡尔半导体公司 Pressure transducer and packaging method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6646316B2 (en) * 2001-01-24 2003-11-11 Kingpak Technology, Inc. Package structure of an image sensor and packaging
CN1212662C (en) * 2002-01-16 2005-07-27 翰立光电股份有限公司 Package structure of display element
US6472736B1 (en) * 2002-03-13 2002-10-29 Kingpak Technology Inc. Stacked structure for memory chips
TW586197B (en) * 2002-04-24 2004-05-01 Scientek Corp Image sensor semiconductor package
US20040113286A1 (en) * 2002-12-16 2004-06-17 Jackson Hsieh Image sensor package without a frame layer
US6933493B2 (en) * 2003-04-07 2005-08-23 Kingpak Technology Inc. Image sensor having a photosensitive chip mounted to a metal sheet
US6995462B2 (en) * 2003-09-17 2006-02-07 Micron Technology, Inc. Image sensor packages
JP2007311416A (en) * 2006-05-16 2007-11-29 Fujifilm Corp Solid-state imaging device
KR100818546B1 (en) 2006-07-31 2008-04-01 하나 마이크론(주) Image Sensor Package And Fabricating Method Thereof
TWI364823B (en) * 2006-11-03 2012-05-21 Siliconware Precision Industries Co Ltd Sensor type semiconductor package and fabrication method thereof
JP2008192769A (en) * 2007-02-02 2008-08-21 Sharp Corp Resin-sealed semiconductor photodetector and method of manufacturing the resin-sealed semiconductor photodetector, and electronic apparatus using the resin-sealed semiconductor photodetector
US7964945B2 (en) * 2007-09-28 2011-06-21 Samsung Electro-Mechanics Co., Ltd. Glass cap molding package, manufacturing method thereof and camera module
JP2009111130A (en) * 2007-10-30 2009-05-21 Fujifilm Corp Imaging apparatus and its manufacturing method
TW201104850A (en) * 2009-07-29 2011-02-01 Kingpak Tech Inc Image sensor package structure with large air cavity
TWI398949B (en) * 2009-07-29 2013-06-11 Kingpak Tech Inc Manufacturing method for molding image sensor package structure and image sensor package structure thereof
JP5658466B2 (en) * 2010-02-05 2015-01-28 キヤノン株式会社 Method for manufacturing solid-state imaging device
TWI414060B (en) * 2010-09-17 2013-11-01 Kingpak Tech Inc Manufacturing method of molded image sensor packaging structure with predetermined focal length and the structure using the same
KR20130083249A (en) * 2012-01-12 2013-07-22 삼성전자주식회사 Semiconductor apparatus, image sensor package using the same
KR101963809B1 (en) * 2012-04-25 2019-03-29 삼성전자주식회사 Image sensor package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0951009A (en) * 1995-08-07 1997-02-18 Dainippon Printing Co Ltd Resin sealing of ic module, ic module, and ic card
CN1758422A (en) * 2004-10-09 2006-04-12 北京七星华创电子股份有限公司 Optically coupled packaging method for thick film printing circuit
CN1905144A (en) * 2005-05-27 2007-01-31 阿瓦戈科技通用Ip(新加坡)股份有限公司 Methods for packaging an image sensor and a packaged image sensor
CN101950751A (en) * 2009-07-10 2011-01-19 菱光科技股份有限公司 Image sensor and encapsulating method thereof
CN102589753A (en) * 2011-01-05 2012-07-18 飞思卡尔半导体公司 Pressure transducer and packaging method thereof

Also Published As

Publication number Publication date
CN104282698A (en) 2015-01-14
KR101467699B1 (en) 2014-12-01
TW201503334A (en) 2015-01-16
US8969120B2 (en) 2015-03-03
JP5635661B1 (en) 2014-12-03
CN107742630A (en) 2018-02-27
US20150011038A1 (en) 2015-01-08
CN107742630B (en) 2020-05-19
JP2015019031A (en) 2015-01-29

Similar Documents

Publication Publication Date Title
CN104282698B (en) Two-stage packaging method for image sensor
TW445608B (en) Semiconductor package and manufacturing method thereof of lead frame without flashing
US7145253B1 (en) Encapsulated sensor device
US20020008315A1 (en) Semiconductor package and method of fabricating the same
TWI520234B (en) Manufacturing method of semiconductor device
CN104779221A (en) Fingerprint identification module packaging structure, method for preparing fingerprint identification module packaging structure as well as electronic equipment
US11355423B2 (en) Bottom package exposed die MEMS pressure sensor integrated circuit package design
CN105470212B (en) Encapsulation and its assemble method for semiconductor devices
CN105870024A (en) System-level packaging method
CN105977220A (en) Semiconductor package assembly
TWM550909U (en) Packaging structure of image sensor
US7541222B2 (en) Wire sweep resistant semiconductor package and manufacturing method therefor
KR20080005735A (en) Package on package and method for a manufacturing the same
CN110301042A (en) Semiconductor packages with wire bonding net
TW201312711A (en) Pre molded can package
CN204558444U (en) Fingerprint recognition module package structure and electronic equipment
CN102298724A (en) Gluing type whole-mount technology for electronic component of IC card
CN209169123U (en) A kind of encapsulating structure
CN209544354U (en) The encapsulating structure of imaging sensor
CN106897709A (en) Fingerprint recognition module and electronic installation
CN110112163A (en) A kind of image sensor package structure and packaging method
CN210668337U (en) Packaging structure of sensor and sensor
CN204361080U (en) Circuits System and chip package thereof
CN107399712A (en) The pressure sensor structure and preparation method of a kind of system in package
CN209525013U (en) A kind of encapsulating structure and temp probe of temperature sensor chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20161222

Address after: No. eighty-four Taiwan Hsinchu County China jhubei City, Taihe Road

Applicant after: KINGPAK TECHNOLOGY Inc.

Address before: Taiwan Hsinchu County Chinese jhubei City, Taihe Road No. 84

Applicant before: KINGPAK TECHNOLOGY INC.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230116

Address after: Taipei City, Taiwan Chinese Zhongzheng District Yanping Road No. 83 6 floor

Patentee after: TONG HSING ELECTRONIC INDUSTRIES, Ltd.

Address before: No. eighty-four Taiwan Hsinchu County China jhubei City, Taihe Road

Patentee before: KINGPAK TECHNOLOGY Inc.

TR01 Transfer of patent right