CN104216457B - A kind of high-order temperature compensation circuit of non-bandgap reference source - Google Patents

Abstract

The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind of high-order temperature compensation circuit of non-bandgap reference source.Of the present inventionly comprise electric current source generating circuit, low temperature compensation circuit, high temperature compensation circuit and reference source circuit; The output terminal of described electric current source generating circuit is connected with the first input end of reference source circuit, the first input end of low temperature compensation circuit, the first input end of high temperature compensation circuit respectively; The outside positive temperature voltage of second input termination first of low temperature compensation circuit, the first output terminal of its 3rd input termination reference source circuit, it exports the second input end of termination reference source circuit; The outside positive temperature voltage of second input termination second of high temperature compensation circuit, the first output terminal of its 3rd input termination reference source circuit, it exports the second input end of termination reference source circuit; Second output terminal output reference voltage of reference source circuit.The present invention has the reference voltage of less temperature coefficient; Because pipe work most of in integrated circuit is in subthreshold region, circuit integrity power consumption is reduced greatly.The present invention is particularly useful for high-order temperature compensation circuit.

Description

High-order temperature compensation circuit of non-band-gap reference source

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-order temperature compensation circuit of a non-band-gap reference source.

Background

Reference sources play an important role in applications such as analog-to-digital converters and power integrated circuits, and are used to provide an accurate and stable reference dc voltage. Insensitivity to temperature and noise, and extremely low quiescent current and operating voltage are design goals for future high performance circuits.

In order to reduce the voltage drift of the reference source in a wide temperature range, various high-order compensation techniques have been proposed, such as square term temperature compensation, exponential temperature compensation, piecewise linear compensation, temperature-dependent resistance ratio compensation, etc., and the basic concept thereof is to introduce an advanced digital function to offset the high-order temperature coefficient of the PN junction. For a subthreshold region MOS non-bandgap reference source, the main factor for limiting the temperature characteristic of the reference source is concentrated on the nonlinear temperature characteristic of mobility, and a compensation method aiming at the factor is rare, and particularly in a low temperature range, the compensation difficulty is large.

Disclosure of Invention

The invention aims to provide a high-order temperature compensation method suitable for a subthreshold region MOS non-bandgap reference source, which respectively performs high-temperature compensation and low-temperature compensation, reduces the influence of the nonlinear temperature characteristic of mobility on the reference source, and obtains a smaller temperature coefficient.

The invention has the technical scheme that the high-order temperature compensation circuit of the non-band-gap reference source is characterized by comprising a current source generating circuit, a low-temperature compensation circuit, a high-temperature compensation circuit and a reference source circuit; the output end of the current source generating circuit is respectively connected with the first input end of the reference source circuit, the first input end of the low-temperature compensation circuit and the first input end of the high-temperature compensation circuit; the second input end of the low-temperature compensation circuit is connected with the first external positive temperature voltage, the third input end of the low-temperature compensation circuit is connected with the first output end of the reference source circuit, and the output end of the low-temperature compensation circuit is connected with the second input end of the reference source circuit; the second input end of the high-temperature compensation circuit is connected with the second external positive temperature voltage, the third input end of the high-temperature compensation circuit is connected with the first output end of the reference source circuit, and the output end of the high-temperature compensation circuit is connected with the second input end of the reference source circuit; and a second output end of the reference source circuit outputs a reference voltage.

Specifically, the low-temperature compensation circuit is composed of PMOS transistors M8, M9, M12, M16, M17, M18, and NMOS transistors M10, M11, M13, M14, M15; wherein, the source of M8 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M10; the grid of M10 is connected with the first external positive temperature voltage, and the source is connected with the drain of M11; m11 having its gate connected to the first output terminal of the reference source circuit and its source connected to ground potential; the source of M9 is connected with the power voltage, the grid is connected with the grid of M8, and the drain is connected with the drain of M13; m13 with its gate connected to the gate of M14 and its source at ground potential; m14 has its gate and drain interconnected, its drain connected to the drain of M12, and its source at ground potential; the grid electrode of M12 is connected with the output end of the current source generating circuit, and the source electrode is connected with the power voltage; the gate of M15 is connected to the first output terminal of the reference source circuit, the drain is connected to the drain of M16, and the source is at ground potential; m16 has its gate connected to the interconnection of M9 drain and M13 drain, and its source connected to the drain of M17; the source of M17 is connected with the power voltage, and the grid is in short circuit with the drain; the source of M18 is connected with the power voltage, the grid is connected with the grid of M17, and the drain is the output end of the low temperature compensation circuit;

the high-temperature compensation circuit is composed of PMOS tubes M19, M20, M25, M26, M27 and M28, and NMOS tubes M21, M22, M23, M24 and M29; wherein, the source of M19 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M21; the grid of M21 is connected with the second external positive temperature voltage, and the source is connected with the drain of M22; m22 having its gate connected to the first output terminal of the reference source circuit and its source connected to ground potential; the source of M20 is connected with the power voltage, the grid is connected with the grid of M19, and the drain is connected with the drain of M23; m23 gate to drain interconnection, its source at ground potential; the source of M25 is connected with the power voltage, the grid is connected with the output end of the current source generating circuit, and the drain is connected with the drain of M24; m24 with its gate connected to the gate of M23 and its source at ground potential; the gate of M29 is connected to the first output terminal of the reference source circuit, the drain is connected to the drain of M28, and the source is at ground potential; m28 has its gate connected to the interconnection of M25 drain and M24 drain, and its source connected to the drain of M26; the source of M26 is connected with the power supply voltage, and the grid is connected with the drain; the source of M27 is connected to the power supply voltage, its gate is connected to the gate of M26, and its drain is used as the output end of the high temperature compensation circuit.

The high-order temperature compensation method for the sub-threshold region MOS non-band-gap reference source has the advantages that the high-order temperature compensation method for the sub-threshold region MOS non-band-gap reference source compensates the output voltage of the reference source in high and low temperature ranges respectively based on switch control, reduces the influence of the nonlinear temperature characteristic of mobility on the reference source, and accordingly obtains the reference voltage with a smaller temperature coefficient; because most of the tubes in the whole circuit work in a subthreshold region, the whole power consumption of the circuit is greatly reduced.

Drawings

FIG. 1 is a schematic diagram of a high-order temperature compensation method for a sub-threshold MOS non-bandgap reference source according to the present invention;

FIG. 2 is a schematic diagram illustrating an exemplary current source generating circuit according to the present invention;

FIG. 3 is a schematic diagram of an example of a reference source circuit that verifies the present invention;

FIG. 4 is a schematic diagram of a low temperature compensation circuit according to the present invention;

FIG. 5 is a schematic diagram of a high temperature compensation circuit according to the present invention;

FIG. 6 is a schematic diagram of the low temperature compensation current principle of the present invention;

FIG. 7 is a schematic diagram of the high temperature compensation current principle of the present invention;

FIG. 8 is a diagram of a reference source after high-order temperature compensation according to the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples

The framework schematic diagram of the high-order temperature compensation method suitable for the sub-threshold region MOS non-band-gap reference source is shown in FIG. 1 and comprises a current source generating circuit, a low-temperature compensation circuit, a high-temperature compensation circuit and a reference source circuit; wherein, the current source generates the first bias voltage V that the circuit produces_B1The first input end of the low-temperature compensation circuit, the first input end of the high-temperature compensation circuit and one input end of the reference source circuit are respectively connected; the second input end of the low-temperature compensation circuit is connected with an external positive temperature voltage V_PTAT(PTAT), the third input end is connected with an output end V of the reference source_B2The output end of the reference source circuit is connected with the other input end V of the reference source circuit_C(ii) a The second input end of the high-temperature compensation circuit is connected with an external positive temperature voltage V_PTAT1The third input terminal is connected with an output terminal V of the reference source_B2The output end of the reference source circuit is connected with the other input end V of the reference source circuit_C(ii) a The other output end of the reference source circuit outputs a reference voltage V_REF。

The low temperature compensation circuit is shown in fig. 4, and comprises 6 PMOS transistors: m8, M9, M12, M16, M17, M18, 5 NMOS transistors: m10, M11, M13, M14 and M15. The specific connection relationship is as follows: the source of M8 is connected with the power voltage VIN, the grid is interconnected with the drain, and the drain is connected with the drain of M10; gate of M10 is connected toExternal positive temperature voltage V_PTATThe source of the M11 is connected with the drain of the M11; m11 gate connected to external second bias voltage V_B2The source thereof is grounded potential VSS; the source of M9 is connected with the power voltage VIN, the grid is connected with the grid of M8, and the drain is connected with the drain of M13; m13 with its gate connected to the gate of M14 and its source at ground potential VIN; m14 has its gate and drain interconnected, its drain connected to the drain of M12, and its source at ground potential VIN; m12 gate connected to external first bias voltage V_B1The source of the diode is connected with a power supply voltage VIN; m15 gate connected to external second bias voltage V_B2The drain of the transistor is connected with the drain of M16, and the source of the transistor is grounded at VSS; m16 has its gate connected to the interconnection of M9 drain and M13 drain, and its source connected to the drain of M17; the source electrode of the M17 is connected with the power voltage VIN, and the grid electrode of the M17 is in short circuit with the drain electrode; m18 has its source connected to the power supply voltage VIN, its gate connected to the gate of M17, and its drain as the output V of the circuit_C。

The high temperature compensation circuit is shown in fig. 5, and comprises 6 PMOS transistors: m19, M20, M25, M26, M27, M28, 5 NMOS transistors: m21, M22, M23, M24 and M29. The specific connection relationship is as follows: the source of M19 is connected with the power voltage VIN, the grid is interconnected with the drain, and the drain is connected with the drain of M21; the grid of M21 is connected with an external positive temperature voltage V_PTAT1The source of the M22 is connected with the drain of the M22; m22 gate connected to external second bias voltage V_B2The source thereof is grounded potential VSS; the source of M20 is connected with the power voltage VIN, the grid is connected with the grid of M19, and the drain is connected with the drain of M23; m23, its gate and drain interconnected, its source at ground potential VSS; m25 has its source connected to the power supply voltage VIN and its gate connected to the external first bias voltage V_B1The drain electrode is connected with the drain electrode of the M24; m24 with its gate connected to the gate of M23 and its source at ground potential VSS; m29 gate connected to external second bias voltage V_B2The drain of the transistor is connected with the drain of M28, and the source of the transistor is grounded at VSS; m28 has its gate connected to the interconnection of M25 drain and M24 drain, and its source connected to the drain of M26; the source of M26 is connected with the power voltage VIN, and the grid is interconnected with the drain; the source of M27 is connected to the supply voltage VIN, its gate is connected to the gate of M26, and its drain is the output of the circuit.

A current source generating circuit in the inventionAn example of which is schematically shown in fig. 2, which generates a positive temperature current I ═ a μ_nT²Wherein A is a constant, mu_nIs the electron mobility, T is the absolute temperature, and then mirrored to the reference source circuit and the low temperature compensation circuit through the M7 transistor.

The circuit structure of the reference source circuit in the invention adopts a subthreshold region MOS non-bandgap reference source, and is shown in fig. 3 and comprises PMOS tubes M1, M2, M5 and M6, and NMOS tubes M3 and M4. In the circuit, M1 and M2 work in a saturation region, and the rest MOS tubes work in a subthreshold region. The output voltage V of the reference source can be obtained by formula derivation_REFComprises the following steps:

$V_{\mathrm{REF}}=V_{\mathrm{GS}4}+V_{\mathrm{GS}2}-V_{\mathrm{GS}1}=V_{\mathrm{THN}}+{\mathrm{nV}}_T\ln B+C\sqrt{\frac{{\mathrm{\μ}}_n}{{\mathrm{\μ}}_p}}T---\left(1\right)$

wherein, $B=\frac{{\mathrm{Aq}}^2{S}_5}{k^2{C}_{\mathrm{OX}}{S}_7{S}_4},$ $C=\sqrt{\frac{{2\mathrm{AS}}_6}{C_{\mathrm{OX}}{S}_1{S}_{22}}\·\frac{a}{a+1}}(1-\sqrt{\frac{S_1}{{\mathrm{aS}}_2}}),$ V_THNis the threshold voltage of the NMOS transistor, n is the subthreshold slope, μ_pIs the hole mobility, C_OXIs the capacitance per unit area of the gate oxide, V_TIs a thermal voltage, S_iDenotes a MOS transistor M_iK is Boltzmann constant, q is the electronic charge, and a is the current proportionality coefficient of M1 and M2.

The reference voltage is derived from the temperature by:

$\frac{{\∂V}_{\mathrm{REF}}}{\∂T}=-{\mathrm{\α}}_{\mathrm{VTH}}+\frac{\mathrm{nk}}{q}\ln B+0.95C\frac{1}{\sqrt[20]{T}}---\left(2\right)$

wherein, α_VTHIs a V_THNThe temperature coefficient of (a).

Since the above-mentioned positive temperature current source generating circuit and the reference source circuit can be implemented in various forms, and are not the protection content of the present invention, it is only for convenience of explanation of the principle of the present invention, and therefore, the present invention is not explained in detail.

From the above-mentioned reference voltage V_REFAs can be seen from the formula, theoretically, by controlling the temperature coefficient of the positive temperature current I and the width-to-length ratios of M1, M4, M5, M6, and M7, a reference source with a zero temperature coefficient can be obtained. In fact, the waveform of the reference output voltage is shown as a solid line in fig. 6 due to the influence of the nonlinear temperature term such as carrier mobility. The invention provides a high-order temperature compensation method which is used for reducing the temperature coefficient of reference voltage.

The low temperature compensation circuit of the present invention is shown in fig. 4, wherein M8 and M9 transistors, M13 and M14 transistors, and M17 and M18 transistors respectively form a current mirror, and the gates of M11 and M15 transistors are biased by a bias voltage V_B2The grid of the M12 tube is biased by a voltage V_B1Controlling, the leakage currents are respectively:

$I_{11}=\frac{S_{11}}{S_4}{I}_4=A\frac{S_{11}{S}_5}{S_4{S}_7}{\mathrm{\μ}}_n{T}^2---\left(3\right)$

$I_{15}=\frac{S_{15}}{S_4}{I}_4=A\frac{S_{15}{S}_5}{S_4{S}_7}{\mathrm{\μ}}_n{T}^2---\left(4\right)$

$I_{12}=\frac{S_{12}}{S_7}I=A\frac{S_{12}}{S_7}{\mathrm{\μ}}_n{T}^2---\left(5\right)$

wherein, I_iIs a MOS transistor M_iThe leakage current of (2). From the above formula, when the M11, M12 and M15 transistors all work in the region required by their respective mirror images, the current they pass is completely determined by the mirror image current, then I₁₁、I₁₅、I₁₂Are all positive temperature currents.

When the temperature is below a certain value, i.e. T_L0When, V_PTATMuch less than the threshold voltage of M10, resulting in M10 turning off, M11 with zero drain voltage, no current on this branch, and M11 cannot mirror the current. The gate voltage of M16 is pulled down to zero by M13 so that M16 is turned on and in the linear region, thus ensuring that M15 can completely mirror the output. The working temperature range of the low-temperature compensation circuit designed by the invention is at the lowest temperature point T_L0Upper, V_PTATNot much less than the threshold voltage of M10, so M10 works in the subthreshold region from the beginning, i.e., there is no T_L0The M10 is not turned off at this temperature point, i.e. the operating temperature range of the low temperature compensation circuit designed by the present invention.

With increasing temperature, V_PTATGradually increasing, the source voltage of M10 gradually increases, and the drain voltage of M11 gradually increases, so that the drain current of M11 gradually increases, and finally stabilizes at a certain value, as follows:

$I_{11}=A\frac{S_{11}{S}_5}{S_4{S}_7}{\mathrm{\μ}}_n{T}^2---\left(6\right)$

leakage current I of M11₁₁The leakage current of M9 obtained by mirroring with a current mirror composed of M8 and M9 is

$I_9=\frac{S_9}{S_8}{I}_{11}=A\frac{S_9{S}_{11}{S}_5}{S_8{S}_4{S}_7}{\mathrm{\μ}}_n{T}^2---\left(7\right)$

In the above process, the drain current of M11 is continuously increased, so that the gate voltage of M16 is gradually increased, and the drain voltage of M15 is gradually decreased. When T is reached_L1At this temperature, the drain potential of M15 reaches the critical point of achieving complete mirroring, and the drain current of M18 can be obtained by mirroring as follows:

$I_{18}=\frac{S_{18}}{S_{17}}{I}_{15}=A\frac{S_{18}{S}_{15}{S}_5}{S_{17}{S}_4{S}_7}{\mathrm{\μ}}_n{T}^2---\left(8\right)$

from the above formula, I₁₈V flowing into reference source for positive temperature current_CThe node changes the magnitude of the tail current, and the current change trend is shown in fig. 5.

The temperature continues to rise, the gate voltage of M16 continues to rise, the drain voltage of M15 continues to fall, and the temperature is mirroredGradually decreases so that the output reference passes T_L1After this point, it gradually decreased.

When the temperature is as high as TL2, M16 is turned off, the drain voltage of M15 is zero, and M15 has no current flowing through, and finally the compensation is withdrawn.

Correspondingly, when the temperature is below T_L1While M15 can realize a full mirror current, the current flowing through M15 is proportional to mu_nT². Thus, as the temperature rises, the reference source V is fed_CCurrent I of node₁₈Increasing the temperature coefficient of the difference between the grid source voltages of the M2 tube and the M1 tube, wherein the reference voltage is larger than the value before compensation; when the temperature is higher than T_L1And is less than T_L2When, with increasing temperature, I₁₈The current is gradually reduced, so that the temperature coefficient of the difference between the grid-source voltages of the M2 tube and the M1 tube is reduced until the T_L2Temperature point, I₁₈The current is reduced to zero and the reference voltage returns to the value before compensation. The temperature coefficient of the compensated reference voltage is significantly reduced as shown by the dashed line in fig. 8.

Similarly, the principle of the high temperature compensation method is similar to that of the low temperature compensation method, wherein V_PTAT1Temperature point of action and V in low-temperature compensation method_PTATThe points of action are different. When the temperature is lower than T_HAt this time, the gate voltage of M28 is high, and the current of the branch where it is located is zero; the grid voltage of M28 is gradually reduced along with the temperature rise, the branch has current flowing through, and the current is gradually increased along with the temperature rise, the current flows into V in the reference source after being mirrored_CThe trend of the change of the drain current of the node, M27, is shown in fig. 7. The reference voltage after high temperature compensation is shown as a dotted line in fig. 8.

The invention carries out high-order temperature compensation on the MOS non-band-gap reference source in the subthreshold region based on switch control, realizes excellent temperature coefficient, and greatly reduces the whole power consumption of the circuit because most MOS tubes work in the subthreshold region in the whole circuit.

Claims (1)

1. A high-order temperature compensation circuit of a non-band-gap reference source is characterized by comprising a current source generating circuit, a low-temperature compensation circuit, a high-temperature compensation circuit and a reference source circuit; the output end of the current source generating circuit is respectively connected with the first input end of the reference source circuit, the first input end of the low-temperature compensation circuit and the first input end of the high-temperature compensation circuit; the second input end of the low-temperature compensation circuit is connected with the first external positive temperature voltage, the third input end of the low-temperature compensation circuit is connected with the first output end of the reference source circuit, and the output end of the low-temperature compensation circuit is connected with the second input end of the reference source circuit; the second input end of the high-temperature compensation circuit is connected with the second external positive temperature voltage, the third input end of the high-temperature compensation circuit is connected with the first output end of the reference source circuit, and the output end of the high-temperature compensation circuit is connected with the second input end of the reference source circuit; a second output end of the reference source circuit outputs a reference voltage;

the low-temperature compensation circuit is composed of PMOS tubes M8, M9, M12, M16, M17 and M18, and NMOS tubes M10, M11, M13, M14 and M15; wherein, the source of M8 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M10; the grid of M10 is connected with the first external positive temperature voltage, and the source is connected with the drain of M11; m11 having its gate connected to the first output terminal of the reference source circuit and its source connected to ground potential; the source of M9 is connected with the power voltage, the grid is connected with the grid of M8, and the drain is connected with the drain of M13; m13 with its gate connected to the gate of M14 and its source at ground potential; m14 has its gate and drain interconnected, its drain connected to the drain of M12, and its source at ground potential; the grid electrode of M12 is connected with the output end of the current source generating circuit, and the source electrode is connected with the power voltage; the gate of M15 is connected to the first output terminal of the reference source circuit, the drain is connected to the drain of M16, and the source is at ground potential; m16 has its gate connected to the interconnection of M9 drain and M13 drain, and its source connected to the drain of M17; the source of M17 is connected with the power voltage, and the grid is in short circuit with the drain; the source of M18 is connected with the power voltage, the grid is connected with the grid of M17, and the drain is the output end of the low temperature compensation circuit;

the high-temperature compensation circuit is composed of PMOS tubes M19, M20, M25, M26, M27 and M28, and NMOS tubes M21, M22, M23, M24 and M29; wherein, the source of M19 is connected with the power voltage, the grid is interconnected with the drain, and the drain is connected with the drain of M21; the grid of M21 is connected with the second external positive temperature voltage, and the source is connected with the drain of M22; m22 having its gate connected to the first output terminal of the reference source circuit and its source connected to ground potential; the source of M20 is connected with the power voltage, the grid is connected with the grid of M19, and the drain is connected with the drain of M23; m23 gate to drain interconnection, its source at ground potential; the source of M25 is connected with the power voltage, the grid is connected with the output end of the current source generating circuit, and the drain is connected with the drain of M24; m24 with its gate connected to the gate of M23 and its source at ground potential; the gate of M29 is connected to the first output terminal of the reference source circuit, the drain is connected to the drain of M28, and the source is at ground potential; m28 has its gate connected to the interconnection of M25 drain and M24 drain, and its source connected to the drain of M26; the source of M26 is connected with the power supply voltage, and the grid is connected with the drain; the source of M27 is connected to the power supply voltage, its gate is connected to the gate of M26, and its drain is used as the output end of the high temperature compensation circuit.