CN104183640A - 用于esd保护的dddmos器件结构 - Google Patents

用于esd保护的dddmos器件结构 Download PDF

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CN104183640A
CN104183640A CN201310196161.8A CN201310196161A CN104183640A CN 104183640 A CN104183640 A CN 104183640A CN 201310196161 A CN201310196161 A CN 201310196161A CN 104183640 A CN104183640 A CN 104183640A
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injection region
trap
dddmos
inject
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CN104183640B (zh
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苏庆
邓樟鹏
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

本发明公开了一种DDDMOS结构，包括：形成于P阱中的P+注入区、N-注入区和场氧，形成于P阱上方的多晶硅栅，N+注入区形成于所述N-注入区上部；其中，所述N+注入区的下方的N-注入区中形成有N型泄放区，所述N-注入区下方的P阱中形成有P型泄放区。本发明还提供了一种DDDMOS结构的制造方法。本发明的DDDMOS结构其与现有DDDMOS结构相比较能提高ESD电流泄放能力。

Description

用于ESD保护的DDDMOS器件结构
技术领域
本发明涉及集成电路制造领域，特别是涉及一种用于ESD保护的DDDMOS器件结构。
背景技术
高耐压能力和兼容CMOS工艺，DDDMOS（高压双扩散漏MOS）大量应用于LCD驱动电路，电源芯片管理电路等对高压电路。DDDMOS耐压一般较5V高，比传统LDMOS要低，因此其ESD保护一般考虑采用DDDMOS。为了耐高压，DDD注入一般较淡而且深，N+注入却较浓而且浅，这种结构在泄放ESD电流时容易让ESD电流集中从DDD区表面泄放，造成电流密度过大，让DDDMOS泄放ESD电流能力急剧下降。图1所示为常用ESD DDDMOS结构示意图，为了改善DDDMOS泄放ESD电流的能力，一般在drain端增加ESD Implant工艺；如图2、图3所示，改进的这种结构可以极大程度的提高DDDMOS泄放ESD电流的能力，不过这种结构也降低了DDDMOS的耐压和HCI可靠性，限制了DDDMOS的应用；另外这种结构需要额外的增加一块掩膜板，增加了工艺的复杂度和成本。
发明内容
本发明要解决的技术问题是提供一种DDDMOS结构，其与现有DDDMOS结构相比较能提高ESD电流泄放能力。本发明还提供了一种DDDMOS结构的制造方法。
为解决上述技术问题，本发明的DDDMOS结构，包括：形成于P阱中的P+注入区、N-注入区和场氧，形成于P阱上方的多晶硅栅，N+注入区形成于所述N-注入区上部；其中，所述N+注入区的下方的N-注入区中形成有N型泄放区，所述N-注入区下方的P阱中形成有P型泄放区。
所述N-注入区，注入浓度小于1E14/cm2，注入能量大于100Kev。
所述N型泄放区杂质浓度大于所述N-注入区杂质浓度小于所述N+注入区杂质浓度。
一种所述DDDMOS器件的制造方法,包括：
1）在硅衬底上注入形成P阱；
2）制作场氧；
3）在P阱中注入形成N-注入区；
4）在N-注入区下方P阱中注入形成P型泄放区；
5）在N+注入区下方的N-注入区中注入形成N型泄放区；
6）制作多晶硅栅；
7）在N-注入区中注入形成N+注入区；
8）在P阱中注入形成P+注入区。
其中，步骤3）注入形成N-注入区时，注入浓度小于1E14/cm2，注入能量大于100Kev。
其中，步骤4）注入形成P型泄放区时，P型泄放区位于N-/P阱结处，注入角度α范围为：0°≤α≤15°。
其中，步骤5）注入形成N型泄放区时，注入角度为α1，0°≤α1≤60°，注入浓度和注入能量介于N-和N+之间。
当有ESD电流进入本发明结构时，击穿先发生在P型泄放区，使得ESD电流流向从表面横向改变为主要从纵向流过，N型泄放区极大地降低了DDD结构中的ESD电流密度，大幅提升其的泄放ESD电流的能力。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明：
图1是一种现有DDDMOS结构示意图。
图2是一种现有DDDMOS结构示意图。
图3是一种现有DDDMOS结构示意图。
图4是本发明实施例的结构示意图。
附图标记说明
Pwell是P阱
P+是P+注入区
N-是N-注入区
N+是N+注入区
S是多晶硅栅
O是场氧
A是N型泄放区
B是P型泄放区
α是注入角度
具体实施方式
如图4所示，形成于P阱Pwell中的P+注入区P+、N-注入区N-和场氧O，形成于P阱Pwell上方的多晶硅栅S，N+注入区N+形成于所述N-注入区N-上部；其中，所述N+注入区N+的下方的N-注入区N-中形成有N型泄放区A，所述N-注入区N-下方的P阱Pwell中形成有P型泄放区B；所述N-注入区N-浓度为小于1E14/cm2；所述N型泄放区A杂质浓度大于所述N-注入区N-杂质浓度小于所述N+注入区N+杂质浓度。
一种所述DDDMOS器件的制造方法,包括：
1）在硅衬底上注入形成P阱和制作场氧；
2）在P阱中注入形成N-注入区和P+注入区，注入形成N-注入区时浓度为小于1E14/cm2，能量为大于100Kev；
3）在N-注入区下方P阱中注入形成P型泄放区，注入形成P型泄放区，P型泄放区位于N-/P阱结处，注入角度范围为：0°≤α≤15°。
4）在N+注入区下方的N-注入区中注入形成N型泄放区，注入形成N型泄放区时，注入角度范围为：0°≤α1≤60°；
5）制作多晶硅栅；
6）在N-注入区中注入形成N+注入区；
7）在P阱中注入形成P+注入区。
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (7)

1.一种用于ESD保护的DDDMOS器件结构，包括：形成于P阱中的P+注入区、N-注入区和场氧，形成于P阱上方的多晶硅栅，N+注入区形成于所述N-注入区上部；其特征是：所述N+注入区的下方的N-注入区中形成有N型泄放区，所述N-注入区下方的P阱中形成有P型泄放区。
2.如权利要求1所述用于ESD保护的DDDMOS器件结构，其特征是：所述N-注入区注入浓度小于1E14/cm2，注入能量大于100Kev。
3.如权利要求1所述用于ESD保护的DDDMOS器件结构，其特征是：所述N型泄放区杂质浓度大于所述N-注入区杂质浓度小于所述N+注入区杂质浓度。
4.一种如权利要求所述DDDMOS器件的制造方法，其特征是,包括：
1）在硅衬底上注入形成P阱；
2）制作场氧；
3）在P阱中注入形成N-注入区；
4）在N-注入区下方P阱中注入形成P型泄放区；
5）在N+注入区下方的N-注入区中注入形成N型泄放区；
6）制作多晶硅栅；
7）在N-注入区中注入形成N+注入区；
8）在P阱中注入形成P+注入区。
5.如权利要求4所述DDDMOS器件的制造方法，其特征是：步骤2）注入形成N-注入区时，注入浓度小于1E14/cm2，注入能量大于100Kev。
6.如权利要求4所述DDDMOS器件的制造方法，其特征是：步骤3）注入形成P型泄放区，P型泄放区位于N-/P阱结处，注入角度α范围为：0°≤α≤15°”。
7.如权利要求4所述DDDMOS器件的制造方法，其特征是：步骤5）注入形成N型泄放区时，注入角度为α1，0°≤α1≤60°，注入浓度和注入能量介于N-和N+之间。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040603A (en) * 1999-04-30 2000-03-21 Worldwide Semiconductor Manufacturing Corporation Electrostatic discharge protection circuit employing MOSFETs having double ESD implantations
US20010010954A1 (en) * 2000-01-21 2001-08-02 Geeng-Lih Lin Method of forming an ESD protection device
US20050205926A1 (en) * 2004-03-16 2005-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. High-voltage MOS transistor and method for fabricating the same
CN101022130A (zh) * 2006-02-13 2007-08-22 台湾积体电路制造股份有限公司 高电压金属氧化物半导体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040603A (en) * 1999-04-30 2000-03-21 Worldwide Semiconductor Manufacturing Corporation Electrostatic discharge protection circuit employing MOSFETs having double ESD implantations
US20010010954A1 (en) * 2000-01-21 2001-08-02 Geeng-Lih Lin Method of forming an ESD protection device
US20050205926A1 (en) * 2004-03-16 2005-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. High-voltage MOS transistor and method for fabricating the same
CN101022130A (zh) * 2006-02-13 2007-08-22 台湾积体电路制造股份有限公司 高电压金属氧化物半导体装置

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