CN104167923B - Dynamic fast response circuit of switching power supply and method thereof - Google Patents

Dynamic fast response circuit of switching power supply and method thereof Download PDF

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Publication number
CN104167923B
CN104167923B CN201410384974.4A CN201410384974A CN104167923B CN 104167923 B CN104167923 B CN 104167923B CN 201410384974 A CN201410384974 A CN 201410384974A CN 104167923 B CN104167923 B CN 104167923B
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voltage
module
terminal voltage
output
power supply
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CN104167923A (en
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唐盛斌
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Mornsun Guangzhou Science and Technology Ltd
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Mornsun Guangzhou Science and Technology Ltd
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Priority to PCT/CN2015/084179 priority patent/WO2016019788A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a dynamic fast response method of a switching power supply. According to the method, a green frequency reducing working mode can be used both in an ACDC power supply controller and a DCDC power supply controller to increase working efficiency and reduce no-load standby power consumption, and meanwhile the dynamic response speed can be greatly improved. The method includes the following steps that falling fast responding is conducted, when the voltage of an FB end is detected to be increased rapidly suddenly, a falling dynamic response signal is sent out, current is rapidly provided for the FB end, and after the voltage of the FB end is increased to the first preset value, current is stopped being provided to the FB end; overshoot fast responding is conducted, after the voltage of the FB end is detected to be decreased rapidly suddenly, an overshoot dynamic response signal is sent out, the current at the FB end is extracted rapidly, and after the voltage of the FB end is decreased to the second preset value, the current at the FB end is stopped being extracted; steady state judgment is conducted, whether a voltage loop of the switching power supply enters a steady state or not is judged, if yes, the falling dynamic response signal or the overshoot dynamic response signal is allowed to be output, and if not, the falling dynamic response signal or the overshoot dynamic response signal is not allowed to be output.

Description

A kind of dynamic fast response circuit of Switching Power Supply and its method
Technical field
The present invention relates to the controller of secondary side feedback Switching Power Supply, particularly to the dynamic sound of switch power source output voltage Should.
Background technology
With the continuous development of switch power technology, Switching Power Supply has become the main power supply of electrical appliance, and uses Transformer is realized electrical equipment and is isolated to improve security.Fig. 1 is the inverse-excitation type switch power-supply that conventional secondary side feedback controls, resistance R1 It is output voltage sampling resistor with R2, as the input signal of TL431, this signal is through by TL431 and optocoupler for their partial pressure The trsanscondutance amplifier of composition is transferred to the FB input of controller after amplifying, and (the FB input of controller, also known as the electricity of controller Pressure feedback input end, together simply referred to as FB end below).So the voltage V of FB portFBReflect electric power output voltage VOUTBig Little, frequently referred to voltage feedback loop, and because being to sense fed-back output voltage from the secondary of transformer, can be described as secondary again Voltage feedback loop.Controller is according to VFBSize modulations GATE output dutycycle size to control output voltage, work as output Voltage VOUTWhen higher, optocoupler extracts more electric currents from FB pin, makes VFBDecline, the dutycycle of GATE output diminishes, output electricity Pressure VOUTIt is gradually reduced；When output voltage is less than normal, optocoupler extracts less electric current from FB pin, makes VFBIncrease, GATE output Dutycycle becomes big, output voltage VOUTIt is gradually increased.Therefore output voltage stabilization is made in setting by the continuous adjustment of loop Value.It is sampled voltage direct from output end because this secondary controls, output voltage precision can be made very high, so a large amount of use In the application high to output voltage required precision.
Quickly consumed in current energy resources, the awareness of saving energy of people is constantly strengthened, how to be designed and manufactured efficiently The green power supply product of energy-conservation becomes the problem that we constantly study, and is also therefore pregnant with various optimization frequency reducing control mode Switching Power Supply.Although light load reduction switching frequency considerably improves efficiency and the stand-by power consumption of Switching Power Supply, by The dynamic response loading suddenly under light load or Light Condition is made to become very poor in reducing of frequency, output voltage occurs big Width falls.Particularly in the DCDC power supply of relatively high power, due to the restriction to output capacitance for the small size, if frequency is very when unloaded Low unexpected loading can lead to output voltage to drop into unacceptable stage.After light load or unloaded frequency reducing, Switching Power Supply is dynamic The reason response is deteriorated mainly due to two aspects：First reason is exactly the bandwidth of control loop.It is known that will make to open Close power supply loop stability and can switch noise inhibiting effectively, the closed-loop bandwidth of control loop should be less than switching frequency 1/10th, thus the frequency reducing control model of light load further limit control loop bandwidth so that dynamic response ratio not The difference of frequency reducing situation.Second reason is the Slew Rate restriction of compensator compensating electric capacity.As shown in figure 1, the FB end of controller is Big output current is limited, if because the quiescent bias current of optocoupler is excessive, the biasing circuit on optocoupler major-minor both sides all can disappear Consume larger power consumption.Thus effective bias current that FB provides limits compensating electric capacity CC1Slew Rate size so that dynamically ringing Seasonable CC1The change Slew Rate of electric capacity not leads to dynamic response time delay greatly, and the overshoot of output voltage and owe punching amplitude are big.Especially It is the Switching Power Supply for light load operation under the green mode of operation of frequency reducing, so that loop stability, compensating electric capacity CC1 Value is bigger than the situation of non-frequency reducing.Although the light working method loading green frequency reducing obtains widely should in ACDC control chip With, but exactly because the reason dynamic response is poor, in the controller of DCDC electrical isolation converter, it is hardly visible green The mode of operation of frequency reducing.
Content of the invention
The invention aims to solving above-mentioned technical barrier, no matter provide a kind of be ACDC switch power controller Or the power-supply controller of electric of DCDC, all can increase operating efficiency using green frequency reducing mode of operation and reduce no-load standby work( Consumption, can make dynamic responding speed have the dynamic fast response method of the Switching Power Supply being greatly improved simultaneously.
Corresponding to this, no matter another object of the present invention be to provide a kind of be ACDC switch power controller or The power-supply controller of electric of DCDC, all can increase operating efficiency using green using frequency reducing mode of operation and reduce no-load standby work( Consumption, can make dynamic responding speed have the dynamic fast response circuit of the Switching Power Supply being greatly improved simultaneously.
For method, the dynamic fast response method of Switching Power Supply of the present invention, comprise the steps, fall quick response Step, falls dynamic response signal detecting to send when FB terminal voltage quickly increases suddenly, provides electric current to FB end rapidly, plus The climbing speed of fast FB terminal voltage, and stop providing electric current, this FB end to FB end after FB terminal voltage rises to the first preset value First preset value of voltage corresponds to the FB terminal voltage value under stable state when Switching Power Supply is fully loaded with or is heavily loaded；Overshoot quick response step Suddenly, send overshoot dynamic response signal, the rapid electric current extracting FB end when the quickly reduction suddenly of FB terminal voltage is detected, accelerate The fall off rate of FB terminal voltage, and stop extracting the electric current at FB end after FB terminal voltage drops to the second preset value, this FB end electricity FB terminal voltage value under stable state when second preset value of pressure corresponds to the light load of Switching Power Supply or zero load；Stable state judges step, sentences Whether the voltage loop of disconnected Switching Power Supply enters stable state, if FB terminal voltage never has appearance greatly within the time that counter specifies It is believed that FB terminal voltage kept stable, also voltage loop comes into stable state, then allow output for the fluctuation up and down of amplitude Fall dynamic response signal or overshoot dynamic response signal；If FB terminal voltage occurs significantly within the time that counter specifies Fluctuate up and down, also voltage loop is introduced into stable state, then do not allow output to fall dynamic response signal or overshoot dynamic response Signal.
Preferably, described fall quick response step, including：A first little positive pressure drop (Δ will be moved on FB terminal voltage V1) generate FB terminal voltage and add the voltage after the upper shifting of the first positive pressure drop (VFB+ Δ V1), and the voltage after moving on this (VFB+ Δ V1) sends first voltage sampling module to；Voltage after moving on the control of clock is periodically sampled, and The voltage that sampling is obtained temporarily preserves, when the next sampling period samples refreshing again, the voltage quilt of Sampling hold It is sent to first and compare latch module；The voltage of Sampling hold is compared with FB terminal voltage, comparative result exports to stable state Judge module, and comparative result latches by latch and judged, if FB terminal voltage is higher than the voltage of Sampling hold, And voltage loop is under lower state, then export logic "Yes" signal, represent that the output voltage of Switching Power Supply falls suddenly ?；Otherwise export logic "No" signal, represent that the output voltage of Switching Power Supply does not fall suddenly；Receive logic "Yes" signal Dynamic response signal is fallen in output afterwards, and control is fallen quick response module and carried out quick response in setting time, and is falling The setting time of the quick response that falls module produces reset signal after terminating and makes latch reset；Receive and fall dynamic response signal Afterwards, output current flows out from FB end, makes FB terminal voltage be charged to rapidly the first preset value, so that dutycycle increases sharply；? After FB terminal voltage rises to the first preset value, stop output current at once, allow voltage loop voluntarily to adjust.
Preferably, described overshoot quick response step, including：FB terminal voltage VFB is moved down a second little positive pressure drop (Δ V2) generates the voltage (VFB- Δ V2) after the moving down of the FB terminal voltage positive pressure drop that subtracts the second, and voltage after moving down this (VFB- Δ V2) sends second voltage sampling module to；Periodically sample the voltage after moving down in the control of clock, and The voltage that sampling is obtained temporarily preserves, when the next sampling period samples refreshing again, the voltage quilt of Sampling hold It is sent to second and compare latch module；The voltage of Sampling hold is compared with FB terminal voltage, comparative result exports to stable state Judge module, and comparative result latches by latch and judged, if FB terminal voltage is lower than the voltage of Sampling hold, and And voltage loop is under lower state, then export logic "Yes" signal, represent that the output voltage of Switching Power Supply increased suddenly； Otherwise export logic "No" signal, represent that the output voltage of Switching Power Supply does not increase suddenly；After receiving logic "Yes" signal Output overshoot dynamic response signal, controls overshoot quick response module to carry out quick response in setting time, and in overshoot The setting time of quick response module produces reset signal after terminating and makes latch reset；After receiving overshoot dynamic response signal, Extract electric current from FB end rapidly, make FB terminal voltage quickly fall to the second preset value, so that dutycycle reduces rapidly；At FB end After voltage drops to the second preset value, stop at once extracting electric current, allow voltage loop voluntarily to adjust.
For circuit, the dynamic fast response circuit of Switching Power Supply of the present invention, including：Fall quick response module, Detect to send when FB terminal voltage quickly increases suddenly and fall dynamic response signal, provide electric current to FB end rapidly, accelerate FB end The climbing speed of voltage, and stop providing electric current to FB end after FB terminal voltage rises to the first preset value, this FB terminal voltage First preset value corresponds to the FB terminal voltage value under stable state when Switching Power Supply is fully loaded with or is heavily loaded；Overshoot quick response module, in inspection Measure and when FB terminal voltage quickly reduces suddenly, send overshoot dynamic response signal, the rapid electric current extracting FB end, accelerate FB end electricity The fall off rate of pressure, and stop extracting the electric current at FB end after FB terminal voltage drops to the second preset value, the of this FB terminal voltage FB terminal voltage value under stable state when two preset values correspond to the light load of Switching Power Supply or zero load；Stable state judge module, judges switch Whether the voltage loop of power supply enters stable state, if FB terminal voltage never has appearance significantly within the time that counter specifies It is believed that FB terminal voltage kept stable, also voltage loop comes into stable state for fluctuation up and down, then allow output to fall dynamic State response signal or overshoot dynamic response signal；If the appearance of FB terminal voltage is significantly upper and lower within the time that counter specifies Fluctuation, also voltage loop is introduced into stable state, then do not allow output to fall dynamic response signal or overshoot dynamic response signal.
Preferably, described fall quick response module, including：Shifting formwork block on level is little by moving one in FB terminal voltage First positive pressure drop (Δ V1) generates FB terminal voltage and adds the voltage after the upper shifting of the first positive pressure drop (VFB+ Δ V1), and on this Voltage (VFB+ Δ V1) after shifting sends first voltage sampling module to；First voltage sampling module, in the control next week of clock Voltage after moving in the sampling of phase property ground, and the voltage that sampling is obtained temporarily preserves, when the next sampling period again Secondary sampling refreshes, and the voltage of Sampling hold is sent to first and compares latch module；First compares latch module, by Sampling hold Voltage be compared with FB terminal voltage, comparative result exports to stable state judge module, and comparative result is latched by latch Get off to be judged, if FB terminal voltage is higher than the voltage of Sampling hold, and voltage loop is under lower state, then output is patrolled Collect "Yes" signal, represent that the output voltage of Switching Power Supply falls suddenly；Otherwise export logic "No" signal, represent Switching Power Supply Output voltage do not fall suddenly；First control impulse generator, exports one fixed width after receiving logic "Yes" signal Low level effective signal, control is fallen dynamic response module and is carried out quick response in setting time, and quickly rings falling Producing reset signal after answering the setting time of module to terminate makes latch reset；Fall quick response module, receive and fall dynamically After response signal, output current flows out from FB port, makes the voltage of FB port be charged to rapidly the first preset value, so that duty Ratio increases sharply；After FB terminal voltage rises to the first preset value, stop output current at once, allow voltage loop voluntarily to adjust.
Preferably, described fall quick response module, also include control clock module, for exporting clock signal, described Shifting formwork block on level, including the first current source, the first P-channel metal-oxide-semiconductor, the second P-channel metal-oxide-semiconductor, first resistor, a described P The source electrode of channel MOS tube is connected with the source electrode common-battery source of the second P-channel metal-oxide-semiconductor, the drain electrode of the first P-channel metal-oxide-semiconductor, a P ditch The grid of the grid of road metal-oxide-semiconductor and the second P-channel metal-oxide-semiconductor is grounded through the first current source, and the drain electrode of the second P-channel metal-oxide-semiconductor is through electricity Resistance connects FB end；Described first voltage sampling module, including the first monostable flipflop, the first transmission gate, the first not gate, the first electricity Hold, the input termination of described first monostable flipflop controls clock module, the output end of the first monostable flipflop and first The Reverse Turning Control end of transmission gate connects, and the output end of the first monostable flipflop also connects the forward direction of the first transmission gate through the first not gate Control end, the input of the first transmission gate is connected with the drain electrode of the second P-channel metal-oxide-semiconductor of shifting formwork block on level, the first transmission gate Output end through the first capacity earth；Described first compares latch module, including first comparator, the first NAND gate, a RS Trigger, the just termination FB end of described first comparator, the negative terminal of first comparator connects the first biography of first voltage sampling module The output end of defeated door, the output end of first comparator connects the S end of the first rest-set flip-flop through the first NAND gate；Described first control arteries and veins Rush generator, including the first counter, the second NAND gate, the 3rd NAND gate, the CP termination of described first counter controls clock Module, the Clr termination first of the first counter compares the output end of the first rest-set flip-flop of latch module, the first counter End and the output end of the first rest-set flip-flop export through the second NAND gate, the output end of the second NAND gate, the first rest-set flip-flop defeated The R end going out end and controlling clock module also to connect the first rest-set flip-flop through the 3rd NAND gate；Described fall quick response module, including Second not gate, the 3rd P-channel metal-oxide-semiconductor, the 4th P-channel metal-oxide-semiconductor, the 3rd N-channel MOS pipe, the grid of described 3rd P-channel metal-oxide-semiconductor Pole is connect and is connected with the output end of the second NAND gate, and the output end of the second NAND gate also connects the 3rd N-channel MOS pipe through the second not gate Grid, the source electrode of the 3rd P-channel metal-oxide-semiconductor connects power supply, the drain electrode of the 3rd P-channel metal-oxide-semiconductor respectively with FB end and the 4th P-channel MOS The source electrode of pipe connects, and the grid of the 4th P-channel metal-oxide-semiconductor connects voltage signal, the drain electrode of the 4th P-channel metal-oxide-semiconductor and the 3rd N-channel The drain electrode of metal-oxide-semiconductor connects, the source ground of the 3rd N-channel MOS pipe.
Preferably, described overshoot quick response module, including：Level moves down module, by FB terminal voltage move down one little Second positive pressure drop (Δ V2) generates the voltage (VFB- Δ V2) after the moving down of the FB terminal voltage positive pressure drop that subtracts the second, and under this Voltage (VFB- Δ V2) after shifting sends second voltage sampling module to；Second voltage sampling module, in the control next week of clock The sampling of phase property ground move down after voltage, and the voltage that sampling is obtained temporarily preserves, when the next sampling period again Secondary sampling refreshes, and the voltage of Sampling hold is sent to second and compares latch module；Second compares latch module, by Sampling hold Voltage be compared with FB terminal voltage, comparative result exports to stable state judge module, and comparative result is latched by latch Get off to be judged, if the voltage of the voltage ratio Sampling hold of FB port is low, and voltage loop is under lower state, then defeated Go out logic "Yes" signal, represent that the output voltage of Switching Power Supply increased suddenly；Otherwise export logic "No" signal, represent switch The output voltage of power supply does not increase suddenly；Second control impulse generator, exported impulsion after receiving logic "Yes" signal State response signal, controls overshoot quick response module to carry out quick response in setting time, and in overshoot quick response mould The setting time of block produces reset signal after terminating and makes latch reset；Overshoot quick response module, receives overshoot dynamic response After signal, extract electric current from FB end rapidly, make FB terminal voltage quickly fall to the second preset value, so that dutycycle subtracts rapidly Little；After FB terminal voltage quickly falls to the second preset value, stop at once extracting electric current, allow voltage loop voluntarily to adjust.
Preferably, described overshoot quick response module, also includes controlling clock module, for exporting clock signal, described Level moves down module, including the second current source, the first N-channel MOS pipe, the second N-channel MOS pipe, second resistance, described second electricity Stream source is connected with the grid of the drain electrode, the grid of the first N-channel MOS pipe and the second N-channel MOS pipe of the first N-channel MOS pipe respectively Connect, the source electrode common ground connection of the source electrode of the first N-channel MOS pipe and the second N-channel MOS pipe, the drain electrode warp of the second N-channel MOS pipe Second resistance connects FB end；Described second voltage sampling module, including the second monostable flipflop, the second transmission gate, the 3rd not gate, Second electric capacity, the input termination of described second monostable flipflop controls clock module, the output end of the second monostable flipflop It is connected with the Reverse Turning Control end of the second transmission gate, the output end of the second monostable flipflop also connects the second transmission through the 3rd not gate The positive control end of door, the input of the second transmission gate is connected with the drain electrode of the second N-channel MOS pipe, the output of the second transmission gate End is through the second capacity earth；Described second compares latch module, including the second comparator, the 4th NAND gate, the second rest-set flip-flop, The output end just terminating the second transmission gate of described second comparator, the negative terminal of the second comparator connects FB end, the second comparator Output end connects the S end of the second rest-set flip-flop through the 4th NAND gate；Described second control impulse generator, including the second counter, 5th NAND gate, the 6th NAND gate, described second counter CP termination control clock module, the Clr end of the second counter with The output end of the second rest-set flip-flop connects, the second counterEnd is defeated through the 5th NAND gate with the output end of the second rest-set flip-flop Go out, the output end of the 5th NAND gate, the output end of the second rest-set flip-flop and clock signal also meet the 2nd RS through the 6th NAND gate and touch Send out the R end of device；Described overshoot quick response module, including the 4th not gate, the 4th N-channel MOS pipe, described second control pulse is sent out The output end of the 5th NAND gate of raw device is connected with the grid of the 4th N-channel MOS pipe through the 4th not gate, and described FB end is through diode Drain electrode with the 4th N-channel MOS pipe is connected, the source ground of the 4th N-channel MOS pipe.
Preferably, described fall quick response module or overshoot quick response module, described stable state judge module, including the Three counters, the 3rd rest-set flip-flop, nor gate, the CP termination of described 3rd counter controls clock module, the 3rd counter End is connected with the S end of the 3rd rest-set flip-flop, and described first compares the output end of first comparator of latch module and second compares The output end of the second comparator of latch module through nor gate respectively with the Clr end of the 3rd counter and the R of the 3rd rest-set flip-flop End connects, and the S end through the first NAND gate and the first rest-set flip-flop connects with the output end of first comparator at the Q end of the 3rd rest-set flip-flop Connect, the output end that the second comparator of latch module is also compared at the Q end of the 3rd rest-set flip-flop with second connects through the second NAND gate The S end of two rest-set flip-flops.
Brief description
Fig. 1 is the application circuit of the inverse-excitation type switch power-supply of secondary side feedback control of prior art；
Fig. 2 is the circuit block diagram of the dynamic fast response circuit of Switching Power Supply of the present invention；
Fig. 3 is the circuit theory diagrams of the dynamic fast response circuit of Switching Power Supply of the present invention；
Fig. 4 is the circuit theory diagrams of the monostable flipflop of dynamic fast response circuit of Switching Power Supply of the present invention.
Specific embodiment
In following specific descriptions, only for more fully understanding that present disclosure describes some of the present invention and show Exemplary embodiment.As those skilled in the art will appreciate, can be in a variety of ways to reality as described herein Apply example to be changed, and all these change is all without departing from the spirit or scope of the present invention.Therefore, accompanying drawing and description are illustrative , rather than determinate.
Refer to Fig. 2, a kind of dynamic fast response circuit of the Switching Power Supply providing for the present invention, it has falls quickly Response and the function of overshoot quick response, so include two-way detection and corresponding respond module circuit.The first via is fallen quickly Response circuit includes：Shifting formwork block 11, voltage sample module 12 on level, compare latch module 13, control impulse generator 14, fall The quick response that falls module 15, on level, the input port of shifting formwork block 11 is connected with the FB end of controller；Shifting formwork block 11 on level Output signal sends voltage sample module 12 to；The output signal of voltage sample module 12 sends to and compares latch module 13；Than It is respectively transmitted to controlling impulse generator 14 and stable state judge module 50 compared with the output signal of latch module 13, receive it simultaneously again Feedback signal；Fall quick response module 15 to be fallen under the control signal effect controlling impulse generator 14 to send Quick response, it is realized by the connected FB terminal voltage that increases sharply.
Second passes by and rushes fast response circuit and include：Level moves down module 21, voltage sample module 22, compares latch module 23rd, impulse generator 24, overshoot quick response module 25 are controlled.Also include improving the stable state judge module of antijamming capability simultaneously 50.Passing by second rushes on dynamic response branch road, and the FB end of input port and controller that level moves down module 21 is connected；Level The output signal moving down module 21 sends voltage sample module 22 to；The output signal of voltage sample module 22 sends to and compares lock Storing module 23；The output signal of relatively latch module 23 is respectively transmitted to control impulse generator 24 and stable state judge module 50, Receive their feedback signal simultaneously again；Overshoot quick response module 25 is made in the control signal controlling impulse generator 24 to send With under carry out overshooting quick response, it is reduced connected FB terminal voltage and is realized by rapid.
The operation principle of the present invention is：Fall on quick response branch road at first, on level, shifting formwork block 11 is electric by FB end One little positive pressure drop Δ V1 generation FB terminal voltage VFB is moved on pressure VFB and adds voltage (the VFB+ Δ after the upper shifting of positive pressure drop Δ V1 ), V1 and the voltage (VFB+ Δ V1) after moving on this send voltage sample module 12 to.Voltage sample module 12 is in clock Control periodically sample the voltage after upper shifting, and the voltage that sampling is obtained temporarily preserves, when the next one Sampling period samples refreshing again, and the voltage of Sampling hold is sent to and compares latch module 13.Relatively latch module 13 will be adopted The voltage that sample preserves is compared with FB terminal voltage, and comparative result exports to stable state judge module 50, and comparative result is locked Storage latches, if FB terminal voltage is higher than the voltage of Sampling hold, and voltage loop is under lower state, i.e. output is patrolled Collect "Yes" (high or low level) signal, represent that the output voltage of Switching Power Supply falls suddenly；Otherwise output logic "No" letter Number, represent that the output voltage of Switching Power Supply does not fall suddenly.Impulse generator 14 is controlled to receive meeting after logic "Yes" signal Dynamic response signal is fallen in output, and control is fallen quick response module 15 and carried out quick response in setting time, and is falling The setting time of the quick response that falls module 15 produces reset signal after terminating and makes latch reset.Fall quick response module 15 to exist Receive after falling dynamic response signal, output current flows out from FB end, make FB terminal voltage VFB be charged to rapidly corresponding fully loaded or weight FB terminal voltage value during load state, so that dutycycle increases sharply, after FB terminal voltage VFB rapidly rises to preset value, at once Stop output current, allow voltage loop voluntarily to adjust.
The quick response operation principle fallen from above-mentioned output voltage is it can easily be seen that voltage sample module 12 is actually protected Deposit is the upper shifting voltage (VFB+ Δ V1) of firm FB terminal voltage VFB soon in the past, if current FB terminal voltage VFB ' voltage ratio The upper shifting voltage (VFB+ Δ V1) of FB terminal voltage VFB just having preserved is also big, illustrates that current FB terminal voltage rises rapidly, side Reflect that the output voltage of Switching Power Supply falls suddenly.So by detecting uprushing of FB terminal voltage, can determine whether that Switching Power Supply is defeated Go out the generation that voltage falls suddenly this event, after rapid raising dutycycle, contain the trend that output voltage falls immediately, significantly Reduce the amplitude fallen.Because FB terminal voltage VFB rises to behind heavily loaded area, loop voluntarily adjusts output voltage, will not cause volume Outer output overshoot voltage.
Article 2 overshoot quick response branch road on, level move down module 21 by FB terminal voltage VFB move down one little just Pressure drop Δ V2 generates the voltage (VFB- Δ V2) after FB terminal voltage VFB subtracts the moving down of positive pressure drop Δ V2, and after this is moved down Voltage (VFB- Δ V2) send voltage sample module 22 to.Voltage sample module 22 is periodically sampled in the control of clock Voltage after moving down, and the voltage that sampling is obtained temporarily preserves, when the next sampling period samples refreshing again, The voltage that Sampling hold gets off is sent to and compares latch module 23.Relatively latch module 23 is by the voltage of Sampling hold and FB end Mouthful voltage be compared, comparative result exports to stable state judge module 50, and comparative result by latch latch into Row judges, if FB terminal voltage is lower than the voltage of Sampling hold, and voltage loop is under lower state, that is, export logic "Yes" (high or low level) signal, represents that the output voltage of Switching Power Supply increased suddenly；Otherwise export logic "No" signal, represent The output voltage of Switching Power Supply does not increase suddenly.Output overshoot after controlling impulse generator 24 to receive logic "Yes" signal Dynamic response signal, controls overshoot quick response module 25 to carry out quick response in setting time, and quickly rings in overshoot Producing reset signal after answering the setting time of module 25 to terminate makes rest-set flip-flop reset.Overshoot quick response module is receiving overshoot After dynamic response signal, extract electric current from FB end rapidly, when making FB terminal voltage quickly fall to corresponding light load or Light Condition VFB magnitude of voltage so that dutycycle reduces rapidly；After FB terminal voltage VFB quickly falls to preset value, stop at once taking out Electricity, allows voltage loop voluntarily to adjust.
Quickly ring operation principle from what above-mentioned output voltage overshooted it can easily be seen that voltage sample module 2 is actually firm FB terminal voltage VFB that collection preserves move down voltage (VFB- Δ V2), if current FB terminal voltage VFB ' voltage ratio just gathered guarantor FB terminal voltage VFB deposited to move down voltage (VFB- Δ V2) also little, illustrate that current FB terminal voltage declines rapidly, side is reflected The output voltage going out Switching Power Supply increases suddenly.So by the anticlimax detecting FB terminal voltage, can determine whether Switching Power Supply output electricity Pressure increases suddenly the generation of this event, contains, after rapid reduction dutycycle, the trend that output voltage rises immediately, greatly reduces The amplitude of overshoot.Because FB terminal voltage VFB drops to behind light load region, loop voluntarily adjusts output voltage, is not in duty Than the situation being limited too small for a long time.
Meanwhile, the present invention is additionally provided with stable state judge module, and its operation principle is：In duration section n microsecond (time root Set according to needs) in stablize judge module 50 and be all not received by from comparing latch module 13 and compare latch module 23 institute The useful signal sending, then stable state judge module 50 just export effective high level, represent that FB terminal voltage VFB comes into stable shape State.After only FB terminal voltage VFB is judged entrance stable state, output voltage is just allowed to fall dynamic response signal or voltage mistake Impulsion state response signal, can reach raising interference free performance.For example, although VFB becomes quick in Switching Power Supply start-up course Change, but because it could not reach stable state always, will not occurrence dynamics response action.And for example, there is output voltage After falling quick response This move, VFB may be electrically charged too high, again can be VFB through the regulation of feedback voltage loop Voltage subtract, if not having stable state judge module, the at this moment unexpected reduction of VFB may be mistaken as switch power source output voltage Suddenly increase, lead to the mistake that output voltage overshoots quick response to occur.From but regardless of be ACDC switch power controller or The power-supply controller of electric of DCDC, under the frequency reducing mode of operation of light load, all can ensure the stability of circuit loop work, and dynamically Response quickly, therefore completely can increase operating efficiency using green frequency reducing mode of operation and reduce no-load standby power losses, simultaneously Dynamic responding speed can be made to be greatly enhanced.
Additionally, in order to provide a kind of understanding more intuitive to present invention, illustrating in following embodiment description The design of some design parameters, such as " Δ V1=100mV ", the effective low level of output, are also realized corresponding using OR gate Logical relation, these are intended merely to strengthen perceptual knowledge, are not intended as the restriction of the present invention.Because it is well known that design parameter Design according to practical application depending on, the circuit of realizing of logical relation is also diversified.
As shown in figure 3, being the circuit block diagram of the embodiment of the present invention, it includes：Shifting formwork block 11, voltage sample module on level 12nd, compare latch module 13, control impulse generator 14, fall quick response module 15, level moves down module 21, voltage sample Module 22, compare latch module 23, control impulse generator 24, overshoot quick response module 25, control clock module 30, stable state Judge module 50.
Wherein, shifting formwork block 11 on level, including current source Iref1, P-channel metal-oxide-semiconductor MP1, P-channel metal-oxide-semiconductor MP2, resistance R1, the source electrode of metal-oxide-semiconductor MP1 is connected with the source electrode common-battery source of metal-oxide-semiconductor MP2, the drain electrode of metal-oxide-semiconductor MP1, the grid of metal-oxide-semiconductor MP1 and The grid of metal-oxide-semiconductor MP2 is grounded through current source Iref1, and the drain electrode of metal-oxide-semiconductor MP2 connects FB end through resistance R1.
On level, the function of shifting formwork block 11 is, will move a little voltage drop Δ V1 in FB terminal voltage, produce one new Voltage V1=VFB+ Δ V1, flows through resistance R1 with the electric current I1 that a p-type current mirror Iref1 produces, then the pressure drop of resistance R1 For Δ V1=I1*R1, so that moving voltage V1=VFB+I1*R1 in the output of upper shifting formwork block.
Level moves down module 21, including current source Iref2, N-channel MOS pipe MN1, N-channel MOS pipe MN2, resistance R2, electricity Stream source Iref2 is connected with the grid of the drain electrode, the grid of metal-oxide-semiconductor MN1 and metal-oxide-semiconductor MN2 of metal-oxide-semiconductor MN1 respectively, the source of metal-oxide-semiconductor MN1 Pole and the source electrode common ground connection of metal-oxide-semiconductor MN2, the drain electrode of metal-oxide-semiconductor MN2 connects FB end through resistance R2.
The function that level moves down module 21 is that FB terminal voltage is moved down a little voltage drop Δ V2, produces a new electricity Pressure V2=VFB- Δ V2, flows through resistance R2 using the electric current I2 that a N-type current mirror Iref2 produces, then the pressure drop of resistance R2 is Δ V2=I2*R2, so that move down module output to move down voltage V2=VFB-I2*R2.
Voltage sample module 12, including monostable flipflop D1, transmission gate G1, not gate N1, electric capacity Cs1, monostable trigger The input termination of device D1 controls clock module 30, and the output end of monostable flipflop D1 is connected with the Reverse Turning Control end of transmission gate G1 Connect, the output end of monostable flipflop D1 also connects the positive control end of transmission gate G1 through not gate N1, the input of transmission gate G1 with On level, the drain electrode of the metal-oxide-semiconductor MP2 of shifting formwork block 11 connects, and the output end of transmission gate G1 is grounded through electric capacity Cs1.
Voltage sample module 22, including monostable flipflop D2, transmission gate G2, not gate N3, electric capacity Cs2, monostable trigger The input termination of device D2 controls clock module 30, and the output end of monostable flipflop D2 is connected with the Reverse Turning Control end of transmission gate G2 Connect, the output end of monostable flipflop D2 also connects the positive control end of transmission gate G2 through not gate N3, the input of transmission gate G2 with The drain electrode that level moves down the metal-oxide-semiconductor MN2 of module 21 connects, and the output end of transmission gate G2 is grounded through electric capacity Cs2.
The function of voltage sample module 12 and voltage sample module 22 is all the later voltage of Sampling hold displacement, and they divide Voltage V1 is moved on other Sampling hold and moves down voltage V2.Monostable in the falling edge of the clock signal clk controlling clock module 30 State trigger (internal circuit of monostable flipflop is as shown in Figure 4) exports low level pulse signal Pulse, in this burst pulse Control lower transmission gate G1, G2 in the conduction state, sampling capacitance CS1、CS2Upper voltage be charged or discharged shifting voltage V1 or under Move voltage V2.After low level pulse signal Pulse returns to high level, transmission gate G1, G2 turn off, and enter the sampling holding stage, Sampling capacitance C within this stageS1、CS2Preserve the voltage sampling, until next cycle resampling refreshes.It can easily be seen that In the sampling holding stage, the voltage on sampling capacitance was actually the voltage in a upper sampling period, and compared in latch module Voltage ratio was relatively equivalent to the comparison of current FB terminal voltage VFB and FB terminal voltage VFB in a upper sampling period.
Relatively latch module 13, including comparator C1, NAND gate A1, rest-set flip-flop RS1, the anode (in figure of comparator C1 Mark "+" end) connecing FB end, the negative terminal (in figure mark "-" end) of comparator C1 connects the output end of the transmission gate G1 of voltage sample module 12, The output end of comparator C1 connects the S end of rest-set flip-flop RS1 through NAND gate A1.
Relatively latch module 23, including comparator C2, NAND gate A4, rest-set flip-flop RS2, the anode (in figure of comparator C2 Mark "+" end) and connect voltage sample module 22 transmission gate G2 output end, the negative terminal (in figure mark "-" end) of comparator C2 connects FB end, The output end of comparator C2 connects the S end of rest-set flip-flop RS2 through NAND gate A4.
Relatively latch module 13 and the function of comparing latch module 23 are all by current VFB voltage and voltage sample module The later voltage of displacement preserving is compared, and with rest-set flip-flop, comparative result is latched, and by its comparative result (Set1 Or Set2) be respectively transmitted to control impulse generator 14 and control impulse generator 24.Due to comparing latch module 13 and comparing The course of work of latch module 23 is essentially identical, now taking compare latch module 13 as a example to illustrate that its course of work is, if currently FB terminal voltage VFB voltage ratio Sampling hold voltage VS1Height, then comparator C1 output high level, if now in stable state judge module 50 Rest-set flip-flop RS3 output Stable=" 1 " (expression stable state), then NAND gate A1 output low level, latch mould will be compared Rest-set flip-flop RS1 in block 13 is set to " 1 ", i.e. Set1=" 1 ", notifies to control impulse generator 14 to produce fast-response control arteries and veins Rush signal；If current VFB is not than VS1Greatly, Set1 is always maintained at " 0 " state.
Control impulse generator 14, including counter J1, NAND gate A2, NAND gate A3, the CP termination of counter J1 controls Clock module 30, the Clr termination of counter J1 compares the output end of the rest-set flip-flop RS1 of latch module 13, counter J1'sEnd Export through NAND gate A2 with the output end of rest-set flip-flop RS1, the output end of NAND gate A2, the output end of rest-set flip-flop RS1 and control Clock module 30 processed also connects the R end of rest-set flip-flop RS1 through NAND gate A3；
Control impulse generator 24, including counter J2, NAND gate A5, NAND gate A6, the CP termination of counter J2 controls Clock module 30, the Clr termination of counter J2 compares the output end of the rest-set flip-flop RS2 of latch module 23, counter J2'sEnd Export through NAND gate A5 with the output end of rest-set flip-flop RS2, the output end of NAND gate A5, the output end of rest-set flip-flop RS2 and control Clock module 30 processed also connects the R end of rest-set flip-flop RS2 through NAND gate A6；
The effect controlling impulse generator 14,24 is all to produce when receiving the comparative result comparing latch module 13,23 Lively state response signal, that is, control what impulse generator 14 produced the Low level effective of one fixed width to fall dynamic response signal, Impulse generator 24 is controlled to produce the overshoot dynamic response signal of the Low level effective of one fixed width, to control dynamic response respectively Module 15,25 quick response within the time of regulation, and produce after response terminates reset signal make to compare latch module 13, Rest-set flip-flop in 23 resets.The course of work due to controlling impulse generator 14,24 is essentially identical, now to control pulse generation Its course of work to be described as a example device 14：Under original state, Set1=" 0 ", Pulse1=" 1 ", Q_=" 1 ", Rset1=" 1 ". When controlling impulse generator 14 to receive effective control signal Set1=" 1 ", control signal Pusle1 is changed into effective electricity at once Flat " 0 ", due to controlling counter J1 asynchronous resetting end Clr=" 1 " in impulse generator 14, counter J1 starts counting up.Treat Counter J1 counts after terminating, and counter J1 exportsPulse1 is restored to inactive level " 1 ".When control clock CLK=" 1 " after the rising edge clock signal arrival of module 30, output reset signal Rset1=" 0 ", make to compare latch module 13 In rest-set flip-flop RS1 reset, Set1=" 0 ", counter J1 be also cleared,Rset1 is restored to inactive level “1”.So after effective control signal output finishes, being returned to original state.
Stable state judge module 50, including counter J3, rest-set flip-flop RS3, nor gate U1, the CP termination of counter J3 controls Clock module 30, counter J3'sEnd is connected with the S end of rest-set flip-flop RS3, compares the output of the comparator C1 of latch module 13 The output end of end and the comparator C2 comparing latch module 23 connects Clr end and the rest-set flip-flop of counter J3 respectively through nor gate U1 The R end of RS3, the Q end of rest-set flip-flop RS3 meets RS with the output end of the comparator C1 comparing latch module 13 through NAND gate A1 and touches Send out the S end of device RS1, the Q end of rest-set flip-flop RS3 is also connect through NAND gate A4 with the output end of the comparator C2 comparing latch module 23 The S end of rest-set flip-flop RS2.
The effect of stable state judge module 50 is whether the voltage loop judging Switching Power Supply enters stable state, and principle is to count In the time that device specifies, FB terminal voltage never has and fluctuation up and down significantly then it is assumed that FB terminal voltage VFB keeps substantially Stable, voltage loop comes into stable state.As long as larger fluctuation in FB terminal voltage, compare latch module 13 or compare Comparator in latch module 23 will export high level, and counter asynchronous resetting after being coupled by nor gate, RS also can be by Reset.So only FB terminal voltage big fluctuation within the stipulated time (being determined by timer), there is no reset signal Produce, after rolling counters forward, rest-set flip-flop is set to " 1 ", i.e. Stable=" 1 ", expression judged result is stable state.
Fall quick response module 15, including not gate N2, P-channel metal-oxide-semiconductor MP3, P-channel metal-oxide-semiconductor MP4, N-channel MOS pipe The grid of MN3, metal-oxide-semiconductor MP3 is connect and is connected with the output end of NAND gate A2 controlling impulse generator 14, the output end of NAND gate A2 Also connect the grid of metal-oxide-semiconductor MN3 through not gate N2, the source electrode of metal-oxide-semiconductor MP3 connects power supply, the drain electrode of metal-oxide-semiconductor MP3 respectively with FB end and MOS The source electrode of pipe MP4 connects, and the grid of metal-oxide-semiconductor MP4 meets voltage signal Vref, and the drain electrode of metal-oxide-semiconductor MP4 is connected with the drain electrode of metal-oxide-semiconductor MN3 Connect, the source ground of metal-oxide-semiconductor MN3.
Fall quick response module 15, its effect is to provide rapidly electricity when the quickly increase suddenly of FB terminal voltage is detected Stream accelerate FB terminal voltage VFB climbing speed, and FB terminal voltage VFB rise to preset value after no longer rise, this preset value pair Should in Switching Power Supply be fully loaded with or heavily loaded when stable state under FB terminal voltage VFB.Its operation principle is, in dynamic response signal Pulse1 In the presence of=" 0 ", P-channel metal-oxide-semiconductor MP3 and N-channel MOS pipe MN3 conducting, because the voltage of now VFB is also not up to clamped Voltage (Vref+VSG4) (wherein VSG4It is the source gate voltage of MP4), the obstructed overcurrent of metal-oxide-semiconductor MP4, metal-oxide-semiconductor MP3 flows through after opening High current charges directly to FB end, so that FB terminal voltage VFB is improved rapidly.But FB terminal voltage VFB exceedes (Vref+VSG4) when, electric current The metal-oxide-semiconductor MP4 being played clamped effect is released so that FB terminal voltage VFB by clamped in (Vref+VSG4) nearby it is impossible to again Rise higher.
Overshoot quick response module 25, including not gate N4, N-channel MOS pipe MN4, controls the NAND gate of impulse generator 24 The output end of A5 is connected with the grid of metal-oxide-semiconductor MN4 through not gate N4, and FB end is connected with the drain electrode of metal-oxide-semiconductor MN4 through diode D1, MOS The source ground of pipe MN4；
Overshoot quick response module 25, its effect is to extract rapidly electricity when the quickly reduction suddenly of FB terminal voltage is detected Stream accelerate FB terminal voltage VFB fall off rate, and FB terminal voltage VFB drop to preset value after no longer decline, this preset value pair Should in the light load of Switching Power Supply or unloaded when stable state under FB terminal voltage VFB.Its operation principle is, in dynamic response signal In the presence of Pulse2=" 0 ", metal-oxide-semiconductor MN4 turns on, and extracts high current so that FB terminal voltage VFB declines rapidly from FB end.But It is due to the presence of diode D1 forward voltage drop VD1, FB terminal voltage VFB minimum voltage is more than VD1.If thinking VFB minimum voltage more Higher, can connect again one with diode D1 diode in the same direction.
The announcement of book and teaching according to the above description, those skilled in the art in the invention can also be to above-mentioned embodiment party Formula is changed and is changed.Therefore, the invention is not limited in specific embodiment disclosed and described above, to the present invention's In the scope of the claims that some modifications and changes should also be as fall into the present invention.Although additionally, using in this specification Some specific terms, but these terms are merely for convenience of description, do not constitute any restriction to the present invention.

Claims (9)

1. a kind of dynamic fast response method of Switching Power Supply, comprises the steps,
Fall quick response step, fall dynamic response signal detecting to send when FB terminal voltage quickly increases suddenly, rapidly There is provided electric current to FB end, accelerate the climbing speed of FB terminal voltage, and stop to FB after FB terminal voltage rises to the first preset value End provides electric current, and the first preset value of this FB terminal voltage corresponds to the FB terminal voltage under stable state when Switching Power Supply is fully loaded with or is heavily loaded Value；
Overshoot quick response step, sends overshoot dynamic response signal detecting, rapidly when FB terminal voltage quickly reduces suddenly Extract the electric current at FB end, accelerate the fall off rate of FB terminal voltage, and stop extracting after FB terminal voltage drops to the second preset value The electric current at FB end, the FB terminal voltage under stable state when the second preset value of this FB terminal voltage corresponds to the light load of Switching Power Supply or zero load Value；
Stable state judges step, judges whether the voltage loop of Switching Power Supply enters stable state,
If FB terminal voltage never has and fluctuation up and down significantly it is believed that FB terminal voltage base within the time that counter specifies This holding is stable, and also voltage loop comes into stable state, then dynamic response signal is fallen in permission output or overshoot is dynamically rung Induction signal；
If significantly fluctuating up and down occurs in FB terminal voltage within the time that counter specifies, also voltage loop is introduced into stablizing shape State, then do not allow output to fall dynamic response signal or overshoot dynamic response signal.
2. the dynamic fast response method of Switching Power Supply according to claim 1, is characterized in that：Described fall quick response Step, including：
Add the first little positive pressure drop (Δ V1) generation FB terminal voltage is moved on FB terminal voltage after the upper shifting of the first positive pressure drop Voltage (VFB+ Δ V1), and the voltage (VFB+ Δ V1) after moving on this is sent to first voltage sampling module；
Voltage after moving on the control of clock is periodically sampled, and the voltage that sampling is obtained temporarily preserves, When the next sampling period samples refreshing again, the voltage of Sampling hold is sent to first and compares latch module；
The voltage of Sampling hold is compared with FB terminal voltage, comparative result exports to stable state judge module, and compares knot Fruit is latched by latch and is judged, if FB terminal voltage is higher than the voltage of Sampling hold, and voltage loop is in stable state Under state, then export logic "Yes" signal, represent that the output voltage of Switching Power Supply falls suddenly；Otherwise output logic "No" letter Number, represent that the output voltage of Switching Power Supply does not fall suddenly；
After receiving logic "Yes" signal, dynamic response signal is fallen in output, controls and falls quick response module in setting time Carry out quick response, and produce reset signal after the setting time falling quick response module terminates making latch reset；
Receive after falling dynamic response signal, output current flows out from FB end, makes FB terminal voltage be charged to rapidly the first preset value, So that dutycycle increases sharply；After FB terminal voltage rises to the first preset value, stop output current at once, allow voltage loop Voluntarily adjust.
3. the dynamic fast response method of Switching Power Supply according to claim 1, is characterized in that：Described overshoot quick response Step, including：
FB terminal voltage (VFB) is moved down second little positive pressure drop (Δ V2) and generates moving down of the FB terminal voltage positive pressure drop that subtracts the second Voltage (VFB- Δ V2) afterwards, and this, the voltage (VFB- Δ V2) after moving down sends second voltage sampling module to；
Periodically sample the voltage after moving down in the control of clock, and the voltage that sampling is obtained temporarily preserve, When the next sampling period samples refreshing again, the voltage of Sampling hold is sent to second and compares latch module；
The voltage of Sampling hold is compared with FB terminal voltage, comparative result exports to stable state judge module, and compares knot Fruit is latched by latch and is judged, if FB terminal voltage is lower than the voltage of Sampling hold, and voltage loop is in stable state Under state, then export logic "Yes" signal, represent that the output voltage of Switching Power Supply increased suddenly；Otherwise output logic "No" letter Number, represent that the output voltage of Switching Power Supply does not increase suddenly；
Receive output overshoot dynamic response signal after logic "Yes" signal, control overshoot quick response module in setting time Carry out quick response, and produce reset signal after the setting time of overshoot quick response module terminates making latch reset；
After receiving overshoot dynamic response signal, extract electric current from FB end rapidly, make FB terminal voltage quickly fall to the second preset value, So that dutycycle reduces rapidly；After FB terminal voltage drops to the second preset value, stop at once extracting electric current, allow voltage loop Voluntarily adjust.
4. a kind of dynamic fast response circuit of Switching Power Supply, is characterized in that：Including：
Fall quick response module, fall dynamic response signal detecting to send when FB terminal voltage quickly increases suddenly, rapidly There is provided electric current to FB end, accelerate the climbing speed of FB terminal voltage, and stop to FB after FB terminal voltage rises to the first preset value End provides electric current, and the first preset value of this FB terminal voltage corresponds to the FB terminal voltage under stable state when Switching Power Supply is fully loaded with or is heavily loaded Value；
Overshoot quick response module, sends overshoot dynamic response signal detecting, rapidly when FB terminal voltage quickly reduces suddenly Extract the electric current at FB end, accelerate the fall off rate of FB terminal voltage, and stop extracting after FB terminal voltage drops to the second preset value The electric current at FB end, the FB terminal voltage under stable state when the second preset value of this FB terminal voltage corresponds to the light load of Switching Power Supply or zero load Value；
Stable state judge module, judges whether the voltage loop of Switching Power Supply enters stable state,
If FB terminal voltage never has and fluctuation up and down significantly it is believed that FB terminal voltage base within the time that counter specifies This holding is stable, and also voltage loop comes into stable state, then dynamic response signal is fallen in permission output or overshoot is dynamically rung Induction signal；
If significantly fluctuating up and down occurs in FB terminal voltage within the time that counter specifies, also voltage loop is introduced into stablizing shape State, then do not allow output to fall dynamic response signal or overshoot dynamic response signal.
5. the dynamic fast response circuit of Switching Power Supply according to claim 4, is characterized in that：Described fall quick response Module, including：
Shifting formwork block on level, adds the first malleation by moving the first little positive pressure drop (Δ V1) generation FB terminal voltage in FB terminal voltage Voltage (VFB+ Δ V1) after the upper shifting of fall, and the voltage (VFB+ Δ V1) after moving on this is sent to first voltage sampling Module；
First voltage sampling module, the voltage after moving on the control of clock is periodically sampled, and sampling is obtained Voltage temporarily preserves, and when the next sampling period samples refreshing again, the voltage of Sampling hold is sent to the first ratio Compared with latch module；
First compares latch module, and the voltage of Sampling hold is compared with FB terminal voltage, and comparative result exports to be sentenced to stable state Disconnected module, and comparative result latches by latch and judged, if FB terminal voltage is higher than the voltage of Sampling hold, and Voltage loop is under lower state, then export logic "Yes" signal, represents that the output voltage of Switching Power Supply falls suddenly；No Then export logic "No" signal, represent that the output voltage of Switching Power Supply does not fall suddenly；
First control impulse generator, exports the Low level effective signal of one fixed width, controls after receiving logic "Yes" signal Fall dynamic response module and carry out quick response in setting time, and terminate in the setting time falling quick response module Producing reset signal afterwards makes latch reset；
Fall quick response module, receive after falling dynamic response signal, output current flows out from FB port, makes the electricity of FB port Pressure is charged to rapidly the first preset value, so that dutycycle increases sharply；After FB terminal voltage rises to the first preset value, at once Stop output current, allow voltage loop voluntarily to adjust.
6. the dynamic fast response circuit of Switching Power Supply according to claim 5, is characterized in that：Also include controlling clock mould Block, for exporting clock signal,
Shifting formwork block on described level, including the first current source, the first P-channel metal-oxide-semiconductor, the second P-channel metal-oxide-semiconductor, first resistor, institute The source electrode common-battery source of the source electrode and the second P-channel metal-oxide-semiconductor of stating the first P-channel metal-oxide-semiconductor is connected, the drain electrode of the first P-channel metal-oxide-semiconductor, The grid of the grid of the first P-channel metal-oxide-semiconductor and the second P-channel metal-oxide-semiconductor is grounded through the first current source, the leakage of the second P-channel metal-oxide-semiconductor Pole connects FB end through first resistor；
Described first voltage sampling module, including the first monostable flipflop, the first transmission gate, the first not gate, the first electric capacity, institute The input termination stating the first monostable flipflop controls clock module, the output end of the first monostable flipflop and the first transmission gate Reverse Turning Control end connect, the output end of the first monostable flipflop also connects the positive control of the first transmission gate through the first not gate End, the input of the first transmission gate is connected with the drain electrode of the second P-channel metal-oxide-semiconductor of shifting formwork block on level, the first transmission gate defeated Go out end through the first capacity earth；
Described first compares latch module, and including first comparator, the first NAND gate, the first rest-set flip-flop, described first compares The just termination FB end of device, the negative terminal of first comparator connects the output end of the first transmission gate of first voltage sampling module, the first ratio Connect the S end of the first rest-set flip-flop compared with the output end of device through the first NAND gate；
Described first control impulse generator, including the first counter, the second NAND gate, the 3rd NAND gate, described first counting The CP termination of device controls clock module, and the Clr termination first of the first counter compares the defeated of the first rest-set flip-flop of latch module Go out end, the first counterEnd is exported through the second NAND gate with the output end of the first rest-set flip-flop, the output of the second NAND gate End, the output end of the first rest-set flip-flop and the R end controlling clock module also to connect the first rest-set flip-flop through the 3rd NAND gate；
Described fall quick response module, including the second not gate, the 3rd P-channel metal-oxide-semiconductor, the 4th P-channel metal-oxide-semiconductor, the 3rd N-channel Metal-oxide-semiconductor, the grid of described 3rd P-channel metal-oxide-semiconductor is connect and is connected with the output end of the second NAND gate, and the output end of the second NAND gate is also Connect the grid of the 3rd N-channel MOS pipe through the second not gate, the source electrode of the 3rd P-channel metal-oxide-semiconductor connects power supply, the 3rd P-channel metal-oxide-semiconductor Drain electrode is connected with the source electrode at FB end and the 4th P-channel metal-oxide-semiconductor respectively, and the grid of the 4th P-channel metal-oxide-semiconductor connects voltage signal, the 4th P The drain electrode of channel MOS tube is connected with the drain electrode of the 3rd N-channel MOS pipe, the source ground of the 3rd N-channel MOS pipe.
7. the dynamic fast response circuit of Switching Power Supply according to claim 4, is characterized in that：Described overshoot quick response Module, including：
Level moves down module, FB terminal voltage is moved down second little positive pressure drop (Δ V2) and generates the FB terminal voltage malleation that subtracts the second Fall move down after voltage (VFB- Δ V2), and this voltage (VFB- Δ V2) after moving down send to second voltage sampling Module；
Second voltage sampling module, periodically samples the voltage after moving down in the control of clock, and sampling is obtained Voltage temporarily preserves, and when the next sampling period samples refreshing again, the voltage of Sampling hold is sent to the second ratio Compared with latch module；
Second compares latch module, and the voltage of Sampling hold is compared with FB terminal voltage, and comparative result exports to be sentenced to stable state Disconnected module, and comparative result latches by latch and judged, if the voltage of the voltage ratio Sampling hold of FB port is low, And voltage loop is under lower state, then export logic "Yes" signal, represent that the output voltage of Switching Power Supply increases suddenly ?；Otherwise export logic "No" signal, represent that the output voltage of Switching Power Supply does not increase suddenly；
Second control impulse generator, receives output overshoot dynamic response signal after logic "Yes" signal, controls overshoot quick Respond module carries out quick response in setting time, and produces multiple after the setting time of overshoot quick response module terminates Position signal makes latch reset；
Overshoot quick response module, after receiving overshoot dynamic response signal, extracts electric current from FB end rapidly, makes FB terminal voltage rapid Drop to the second preset value, so that dutycycle reduces rapidly；After FB terminal voltage quickly falls to the second preset value, stop at once Only extract electric current, allow voltage loop voluntarily to adjust.
8. the dynamic fast response circuit of Switching Power Supply according to claim 7, is characterized in that：Also include controlling clock mould Block, for exporting clock signal,
Described level moves down module, including the second current source, the first N-channel MOS pipe, the second N-channel MOS pipe, second resistance, institute State the second current source respectively with the drain electrode of the first N-channel MOS pipe, the grid of the first N-channel MOS pipe and the second N-channel MOS pipe Grid connects, the source electrode common ground connection of the source electrode of the first N-channel MOS pipe and the second N-channel MOS pipe, the second N-channel MOS pipe Drain electrode connects FB end through second resistance；
Described second voltage sampling module, including the second monostable flipflop, the second transmission gate, the 3rd not gate, the second electric capacity, institute The input termination stating the second monostable flipflop controls clock module, the output end of the second monostable flipflop and the second transmission gate Reverse Turning Control end connect, the output end of the second monostable flipflop also connects the positive control of the second transmission gate through the 3rd not gate End, the input of the second transmission gate is connected with the drain electrode of the second N-channel MOS pipe, and the output end of the second transmission gate is through the second electric capacity Ground connection；
Described second compares latch module, and including the second comparator, the 4th NAND gate, the second rest-set flip-flop, described second compares The output end just terminating the second transmission gate of device, the negative terminal of the second comparator connects FB end, and the output end of the second comparator is through the 4th NAND gate connects the S end of the second rest-set flip-flop；
Described second control impulse generator, including the second counter, the 5th NAND gate, the 6th NAND gate, described second counting The CP termination of device controls clock module, and the Clr end of the second counter is connected with the output end of the second rest-set flip-flop, the second counter 'sEnd and the output end of the second rest-set flip-flop export through the 5th NAND gate, the output end of the 5th NAND gate, the second rest-set flip-flop Output end and clock signal also connect the R end of the second rest-set flip-flop through the 6th NAND gate；
Described overshoot quick response module, including the 4th not gate, the 4th N-channel MOS pipe, described second control impulse generator The output end of the 5th NAND gate is connected with the grid of the 4th N-channel MOS pipe through the 4th not gate, and described FB end is through diode and the 4th The drain electrode of N-channel MOS pipe connects, the source ground of the 4th N-channel MOS pipe.
9. the dynamic fast response circuit of Switching Power Supply according to claim 6, is characterized in that：
Described stable state judge module, including the 3rd counter, the 3rd rest-set flip-flop, nor gate, the CP end of described 3rd counter Connect control clock module, the 3rd counterEnd is connected with the S end of the 3rd rest-set flip-flop, and described first compares latch module The output end of first comparator and second compare the output end of the second comparator of latch module through nor gate respectively with the 3rd meter The R end of the number Clr end of devices and the 3rd rest-set flip-flop connects, and the Q end of the 3rd rest-set flip-flop and the output end of first comparator are through the One NAND gate is connected with the S end of the first rest-set flip-flop, and the second ratio of latch module is also compared at the Q end of the 3rd rest-set flip-flop with second Connect the S end of the second rest-set flip-flop compared with the output end of device through the second NAND gate.
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