CN115065221B

CN115065221B - Synchronous rectification dynamic accelerating circuit, control circuit and switching power supply

Info

Publication number: CN115065221B
Application number: CN202210978218.9A
Authority: CN
Inventors: 王梁; 徐炜
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2022-08-16
Filing date: 2022-08-16
Publication date: 2022-11-04
Anticipated expiration: 2042-08-16
Also published as: CN115065221A

Abstract

The application relates to a synchronous rectification dynamic accelerating circuit, a control circuit and a switching power supply, which relate to the technical field of integrated circuits, and the dynamic accelerating circuit comprises: the device comprises a sampling module, a detection module and a control module. Under the condition that the secondary side of the switching power supply is turned off, based on the comparison result of the first sampling voltage and the second sampling voltage of the target voltage capable of representing the output voltage of the switching power supply, whether the target voltage is in a ringing state or not can be determined, after the ringing state that the target voltage is not in the ringing state or the ringing state of the target voltage is waited for is finished, the third sampling voltage of the target voltage and the second sampling voltage of the sampling hold are compared, whether the output voltage drops or not can be determined, whether the target voltage is in the ringing state or not can be determined accurately, then the stable moment of the output voltage can be obtained accurately, and the timeliness and the accuracy of sampling of the output voltage are guaranteed.

Description

Synchronous rectification dynamic accelerating circuit, control circuit and switching power supply

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to a synchronous rectification dynamic accelerating circuit, a control circuit and a switching power supply.

Background

A switching power supply designed based on a Primary Side modulation (PSR) technology has the characteristics of small volume, low cost, good stability and the like, and is widely applied to, for example, chargers for digital products such as notebooks, mobile phones, digital cameras and the like, auxiliary power supplies for computers (Personal computers, PCs), light-emitting diode (LED) drives and the like.

For the switching power supply, during the process of the load jump from light load to heavy load, a large drop occurs in the output voltage. The recovery of the output voltage has a relatively long process due to the poor dynamic response of the PSR. Under the condition, the occurrence of the drop needs to be accurately detected, so that the primary side can quickly respond, the secondary side energy is supplemented to stabilize the output voltage, and the normal operation of a system where the switching power supply is located is ensured.

In the related art, the following scheme is generally adopted to detect whether the fall occurs: and sampling the drain-source voltage Vds of the secondary rectifier tube, comparing the sampling result with a preset reference voltage, and determining whether the system is powered off (namely whether output voltage drop occurs) according to the comparison result. The reference voltage is set based on the output voltage in the system stable state, so that the scheme can only detect one fixed output voltage, if the output voltage in the system stable state changes, the reference voltage set in the chip needs to be reset, and otherwise, the detection result is not accurate any more. Therefore, the application range of the current scheme is greatly limited. On this basis, before the detection, it is further determined whether the system is in a light load or no-load state, because the light load or no-load state occurs when the secondary side of the switching power supply is turned off, the system is in a ringing stage for a period of time, vds is unstable, which results in low Vds sampling precision and affects the accuracy of the detection result. The current practice is to count a fixed time after the secondary side-field rectifier is turned off to mask out the ringing phase. In practical situations, the durations of the ringing phases of different systems are usually different, that is, the durations of the ringing phases are uncertain, in this case, the time point at which the fixed timing ends is not necessarily the time point at which the ringing ends, for example, when the time of the ringing phase is shorter than the fixed timing, the detection of the output voltage drop is not timely enough, which affects the accuracy of the detection result; when the ringing period is longer than the fixed time, vds in the ringing period may be sampled, which may cause system misjudgment and affect system reliability.

Disclosure of Invention

It is an object of the embodiments of the present invention to provide a synchronous rectification dynamic accelerating circuit, a control circuit and a switching power supply, so as to overcome the above technical problems.

According to a first aspect of the present application, there is provided a synchronous rectification dynamic acceleration circuit, comprising: sampling module, detection module and control module, wherein:

the sampling module is used for outputting a first sampling voltage and a second sampling voltage which can represent the target voltage of the output voltage of the switching power supply under the condition that the secondary side of the switching power supply is turned off; after the detection module determines that the target voltage is not in a ringing state or waits for the end of ringing of the target voltage, stopping outputting the first sampling voltage and the second sampling voltage, and outputting a third sampling voltage of the target voltage;

the detection module is used for judging whether the target voltage is in a ringing state or not based on a comparison result of the first sampling voltage and the second sampling voltage, comparing the third sampling voltage with the second sampling voltage sampled and held at the moment that the sampling module stops outputting the second sampling voltage after the target voltage is determined not to be in the ringing state or the ringing of the target voltage is finished, and outputting a voltage drop signal when the third sampling voltage is reduced to be smaller than the second sampling voltage sampled and held;

the control module is used for controlling a secondary rectifier tube of the switching power supply to generate short-circuit pulse according to the voltage drop signal so as to increase the output voltage.

Optionally, the detection module includes:

the ringing detection submodule is used for comparing the first sampling voltage with the second sampling voltage and determining that the target voltage is not in a ringing state or the ringing is finished under the condition that the first sampling voltage is greater than the second sampling voltage and the duration time exceeds a preset time threshold;

and the output drop detection submodule is used for comparing the third sampling voltage with the second sampling voltage sampled and held at the moment that the sampling module stops outputting the second sampling voltage under the condition that the target voltage is not in a ringing state or the ringing is finished and the sampling module stops outputting the first sampling voltage and the second sampling voltage and outputting the third sampling voltage of the target voltage, and outputting a voltage drop signal when the third sampling voltage is smaller than the second sampling voltage sampled and held.

Optionally, the control module includes: the device comprises a wakeup unit, a control logic unit, a NAND logic unit and an inverter; wherein, the first and the second end of the pipe are connected with each other,

the wake-up unit is used for sending a wake-up signal with fixed conduction frequency and fixed conduction time so as to enable a secondary rectifier tube of the switching power supply to generate short-circuit pulses;

the control logic unit is provided with an input end I, an input end II, an output end I and an output end II, wherein the input end I is respectively connected with the ringing detection submodule and the output drop detection submodule;

the output end of the NAND logic unit is connected with the input end of the phase inverter, and the output end of the phase inverter is the output end of the control module.

Optionally, the sampling module includes a plurality of voltage dividing resistors connected in series between the output end of the target voltage and ground, a second switch, a third switch, a fourth switch, a first output end, a second output end, and a clamping circuit;

sequentially determining a second voltage division node, a third voltage division node and a fourth voltage division node from a voltage division circuit in which a plurality of voltage division resistors which are sequentially connected in series are located, wherein voltages at the second voltage division node, the third voltage division node and the fourth voltage division node are sequentially increased progressively, the voltage at the second voltage division node is greater than zero, and the voltage at the fourth voltage division node is smaller than a target voltage;

the fourth switch is connected with the second voltage division node and the second output terminal so as to enable the second output terminal to output the second sampling voltage under the closed condition;

the third switch is connected with the third voltage division node and the first output end so as to enable the first output end to output the first sampling voltage under the closed condition;

the second switch is connected with the fourth voltage division node and the first output end so as to enable the first output end to output the third sampling voltage under the closed condition;

the clamp circuit is connected with the output end of the target voltage through at least one divider resistor in the divider circuit, and the voltage at the connection position of the clamp circuit and the divider circuit is greater than or equal to the voltage at the fourth voltage dividing node.

Optionally, the sampling module is further configured to stop outputting the third sampling voltage based on the voltage drop signal output by the detection module, and output a fourth sampling voltage of the target voltage;

the detection module further comprises:

the primary side response detection submodule is used for comparing the fourth sampling voltage with a second sampling voltage sampled and held at the moment that the sampling module stops outputting the second sampling voltage, and outputting a primary side response signal when the fourth sampling voltage is increased to be greater than the second sampling voltage sampled and held due to the fact that the primary side of the switching power supply is started; the primary side of the switching power supply is opened based on short-circuit pulses generated by a secondary rectifier tube, and the short-circuit pulses generated by the secondary rectifier tube are controlled by wake-up signals with fixed conduction frequency and fixed conduction time;

and the control module is also used for switching off the dynamic acceleration circuit according to the primary side response signal or when the fixed on-time timing is finished.

Optionally, the control module includes: the device comprises a wake-up unit, a control logic unit, a NAND logic unit and an inverter; wherein, the first and the second end of the pipe are connected with each other,

the wake-up unit is used for sending out a wake-up signal;

the control logic unit is provided with an input end I, an input end II, an output end I, an output end II and an output end III, wherein the input end I is respectively connected with the ringing detection submodule, the output drop detection submodule and the primary side response detection submodule;

Optionally, the sampling module includes a plurality of voltage dividing resistors connected in series between an output terminal of the target voltage and ground, and a first switch, a second switch, a third switch, a fourth switch, a first output terminal, and a second output terminal;

sequentially determining a first voltage division node, a second voltage division node, a third voltage division node and a fourth voltage division node from a voltage division circuit in which a plurality of voltage division resistors which are sequentially connected in series are located, wherein the voltages of the first voltage division node, the second voltage division node, the third voltage division node and the fourth voltage division node are sequentially increased in an increasing mode, the voltage of the first voltage division node is larger than zero, and the voltage of the fourth voltage division node is smaller than a target voltage;

the first switch is connected with the first voltage division node and the first output end so as to enable the first output end to output the fourth sampling voltage under the closed condition;

the second switch is connected with the fourth voltage division node and the first output end so as to enable the first output end to output a third sampling voltage under the closed condition;

Optionally, the ringing detection submodule includes a first comparator, a first sample-and-hold circuit, a current source, an MOS transistor, a first capacitor, a schmitt trigger, and a D trigger; the current source is connected with the MOS tube in series and then grounded;

the in-phase end and the inverting end of the first comparator are respectively coupled with the second output end and the first output end, and the output end of the first comparator is connected with the grid electrode of the MOS tube; the input end of the first sampling holding circuit is connected with the second output end, and the output end of the first sampling holding circuit is connected with the in-phase end of the first comparator;

the first end of the first capacitor is connected to the connection node of the current source and the MOS tube, and the second end of the first capacitor is grounded;

the input end of the Schmitt trigger is connected with the first end of the first capacitor, the output end of the Schmitt trigger is connected with the input end of the D trigger, and the output end of the D trigger is connected with the output drop detection submodule.

Optionally, the output drop detection submodule includes a second sample-and-hold circuit, a second comparator and an and-gate circuit;

the input end of the second sampling holding circuit is connected with the second output end, the output end of the second sampling holding circuit is connected with the in-phase end of the second comparator, the inverting end of the second comparator is connected with the first output end, the output end of the second comparator is connected with one input end of the AND gate circuit, the other input end of the AND gate circuit is connected with a drop detection starting signal sent by the ringing detection submodule when the target voltage is determined not to be in the ringing state, and the output end of the AND gate circuit is connected with the control module.

Optionally, the primary side response detection submodule includes a third sample-and-hold circuit and a third comparator; the input end of the third sampling and holding circuit is connected with the second output end, the output end of the third sampling and holding circuit is connected with the in-phase end of the third comparator, the inverting end of the third comparator is connected with the first output end, and the output end of the third comparator is connected with the control module.

Optionally, the ring detection submodule includes a first sample-and-hold circuit and a first comparator, the output drop detection submodule includes a second sample-and-hold circuit and a second comparator, and the primary side response detection submodule includes a third sample-and-hold circuit and a third comparator, where the first comparator, the second comparator and the third comparator multiplex the same comparator, and the first sample-and-hold circuit, the second sample-and-hold circuit and the third sample-and-hold circuit multiplex the same sample-and-hold circuit.

Optionally, the dynamic acceleration circuit further includes: the timing module is connected with the sampling module and the control module; wherein:

the timing module is used for starting timing when the secondary side of the switching power supply is turned off and outputting a first timing end signal to the control module after timing a first preset time;

the control module is also used for outputting a ringing detection signal to the sampling module under the condition that the primary side of the switching power supply is not started according to the first timing end signal;

the sampling module is specifically configured to: the first sampling voltage and the second sampling voltage are output in response to a ringing detection signal.

According to a second aspect of the present application, a synchronous rectification control circuit is provided, the synchronous rectification control circuit includes a synchronous rectification dynamic acceleration circuit as in the first aspect of the present application, a sampling module of the dynamic acceleration circuit is coupled to a source drain of a secondary rectifier tube of a switching power supply, and a control module of the dynamic acceleration circuit is connected to a gate of a control switch connected in parallel to the source drain of the secondary rectifier tube.

According to a third aspect of the present application, there is provided a switching power supply, comprising a primary winding, a primary switching tube and a secondary winding connected to the primary winding, a secondary rectifier tube connected to the secondary winding, and a synchronous rectification control circuit according to the second aspect of the present application.

Has the advantages that:

in the embodiment of the application, under the condition that the secondary side of the switching power supply is turned off, the target voltage can represent the output voltage of the switching power supply, at this time, based on the comparison result of the first sampling voltage and the second sampling voltage of the target voltage, whether the target voltage is in a ringing state or not can be determined, and after the target voltage is accurately determined not to be in the ringing state or the ringing state of the target voltage is waited to be ended, the third sampling voltage of the target voltage is compared with the second sampling voltage of the sampling hold, so that whether the output voltage drops or not is determined. By adopting the ringing detection means, whether the target voltage is in the ringing state can be accurately determined, and then the stable moment of the output voltage can be accurately obtained, the ringing detection means is not influenced by the duration of ringing or no matter how long the ringing time is, the embodiment of the application can realize that the system is not subjected to output voltage drop sampling judgment when being in the ringing stage in a self-adaptive manner, and the system is not subjected to the purpose of output voltage drop judgment when being in the ringing stage.

The embodiment of the application compares the third sampling voltage of the target voltage with the second sampling voltage of the sampling hold, determines that the output voltage drops when the third sampling voltage is reduced to be smaller than the second sampling voltage of the sampling hold, outputs a voltage drop signal, and then controls the secondary rectifier tube of the switching power supply to generate short-circuit pulses according to the voltage drop signal, so that the primary side auxiliary winding detects an oscillation signal to open the primary side switch tube, supplement secondary side energy, and further enable the output voltage to be increased. Because the third sampling voltage and the second sampling voltage are sampling values of the target voltage of the output voltage after the secondary synchronous rectifier tube is turned off, for the output voltage in a certain sampling range, the detection of the output voltage drop can be realized based on the comparison result of the third sampling voltage and the second sampling voltage, the universality and the flexibility of output application are improved, the leakage source voltage Vds of the secondary rectifier tube is compared with a fixed reference voltage in a chip, and therefore whether the output voltage drops or not is judged, the accuracy of judging the output voltage drop is also guaranteed, and the reliability of a system is improved.

Further features of embodiments of the present application and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the application with reference to the attached drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and together with the description, serve to explain the principles of the embodiments of the application.

Fig. 1 is a functional block diagram of a synchronous rectification dynamic acceleration circuit according to an embodiment of the present disclosure;

FIG. 2 is a block diagram of another embodiment of a synchronous rectification dynamic accelerating circuit;

FIG. 3 is a functional block diagram of a synchronous rectification dynamic accelerating circuit according to an embodiment of the present disclosure;

FIG. 4 is a functional block diagram of a synchronous rectification dynamic accelerating circuit according to another embodiment of the present disclosure;

FIG. 5A is a schematic circuit diagram of a sampling module in a synchronous rectification dynamic acceleration circuit according to an embodiment of the present application;

FIG. 5B is a schematic circuit diagram of a sampling module in another synchronous rectification dynamic acceleration circuit according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of a ring detection submodule in a synchronous rectification dynamic accelerating circuit according to an embodiment of the present application;

fig. 7 is a schematic circuit diagram of an output drop detection submodule in a synchronous rectification dynamic acceleration circuit according to an embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a primary side response detection submodule in a synchronous rectification dynamic acceleration circuit according to an embodiment of the present disclosure;

FIG. 9A is a schematic circuit diagram illustrating a control module in a synchronous rectification dynamic acceleration circuit according to an embodiment of the present disclosure;

FIG. 9B is a schematic circuit diagram of a control module in another synchronous rectification dynamic acceleration circuit according to an embodiment of the present application;

FIG. 10 is a waveform diagram of a signal in a synchronous rectification dynamic acceleration circuit according to an embodiment of the present application;

fig. 11 is a functional block diagram of a synchronous rectification control circuit according to an embodiment of the present application;

fig. 12 is a functional block diagram of a switching power supply according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.

Various embodiments and examples according to the present application are described below with reference to the accompanying drawings.

In the case where the secondary side of the switching power supply is turned off, the secondary side coil corresponds to a wire, and the drain voltage Vds of the secondary side rectifier tube can represent the output voltage, which can be a target voltage representing the output voltage of the switching power supply. In the process that the load of the switching power supply jumps from a light load to a heavy load, whether the output voltage of the switching power supply drops or not needs to be detected, and the light load detection needs to be carried out before the output voltage of the switching power supply is detected. However, the light load detection occurs under the condition that the secondary side of the switching power supply is turned off, and when the secondary side of the switching power supply is turned off, a ringing effect is generated, so that the sampling precision and the sampling timeliness of the target voltage of the output voltage are affected.

Based on this, the embodiment of the application provides a synchronous rectification dynamic accelerating circuit, a synchronous rectification control circuit and a switching power supply.

FIG. 1 is a functional block diagram of a synchronous rectification dynamic acceleration circuit according to some embodiments of the present application. As shown in fig. 1, a dynamic acceleration circuit (alternatively referred to as a synchronous rectification dynamic acceleration circuit) 100 includes: a sampling module 110, a detection module 120, and a control module 130.

The sampling module 110 is configured to output a first sampling voltage and a second sampling voltage, which can represent a target voltage of an output voltage of the switching power supply, when the secondary side of the switching power supply is turned off; and after the detection module 120 determines that the target voltage is not in a ringing state or waits for the end of ringing of the target voltage, stopping outputting the first and second sampled voltages and outputting a third sampled voltage of the target voltage.

Specifically, the switching power supply comprises a primary winding, a secondary winding, a primary switching tube connected with the primary winding, and a secondary rectifying tube connected with the secondary winding.

And sampling the target voltage to obtain a first sampling voltage and a second sampling voltage corresponding to the target voltage. When the first sampling voltage and the second sampling voltage are stopped to be output, the second sampling voltage is sampled and held, and the sampling module 110 samples the target voltage to output a third sampling voltage. In some embodiments, the relationship of the first sampled voltage and the second sampled voltage satisfies: the first sampling voltage is greater than the second sampling voltage. The relationship between the second sampling voltage and the third sampling voltage satisfies: the third sampling voltage is greater than the second sampling voltage.

In some examples, a ratio of the first sampled voltage to the target voltage is a first ratio, a ratio of the second sampled voltage to the target voltage is a second ratio, and the first ratio is greater than the second ratio. The ratio of the third sampling voltage to the target voltage is a third ratio, and the third ratio is greater than the second ratio.

The detecting module 120 is configured to determine whether the target voltage is in a ringing state based on a comparison result between the first sampling voltage and the second sampling voltage, compare the third sampling voltage with the second sampling voltage sampled and held at a time when the sampling module 110 stops outputting the second sampling voltage after determining that the target voltage is not in the ringing state or waiting for the end of ringing of the target voltage, and output a voltage droop signal when the third sampling voltage is reduced to be less than the second sampling voltage sampled and held.

When whether the target voltage is in a ringing state is judged based on the comparison result of the first sampling voltage and the second sampling voltage, the first sampling voltage and the second sampling voltage are obtained by sampling the target voltage, so that the first sampling voltage and the second sampling voltage have the same phase and different amplitudes. In this case, the detection module 120 may shift the phase of any one of the first and second sampled voltages after obtaining the first and second sampled voltages, for example, shift the phase of the second sampled voltage, so that the phases of the first and second sampled voltages are different. Under the condition that the target voltage is in a ringing state, a voltage ripple generated after the first sampling voltage and the second sampling voltage are overlapped is large (for example, more than 1%); in the case where the target voltage is not in the ringing state, the voltage ripple generated after the first and second sampling voltages are overlapped is small (for example, less than 1%), and thus it is possible to distinguish whether the target voltage is in the ringing state or not.

In some embodiments, as shown in fig. 2, detection module 120 includes a ring detection submodule 1201 and an output fall detection submodule 1202.

And the ring detection submodule 1201 is configured to compare the first sampling voltage with the second sampling voltage, and determine that the target voltage is not in a ring state or the ring state is ended when the first sampling voltage is greater than the second sampling voltage and the duration exceeds a preset time threshold.

The preset time threshold may be set by a person skilled in the art according to an actual situation, which is not limited in the embodiment of the present application, as long as it is ensured that after the time that the first sampling voltage is continuously greater than the second sampling voltage exceeds the preset time threshold, the voltage ripples on the first sampling voltage and the second sampling voltage are small (for example, less than 1%).

In some examples, the target voltage is not in a ringing state, and there is no oscillation on the first sampling voltage and the second sampling voltage, in which case the first sampling voltage may be continuously greater than the second sampling voltage, and thus the target voltage may be determined not to be in a ringing state or the ringing may be ended as long as it is determined that the duration of the first sampling voltage continuously greater than the second sampling voltage exceeds the preset time threshold.

In other examples, the target voltage is in a ring state, the first and second sampled voltages both oscillate, in which case a difference between the first and second sampled voltages alternates between positive and negative, such that a duration of the first sampled voltage being greater than the second sampled voltage does not exceed a preset time threshold, and a duration of the first sampled voltage being greater than the second sampled voltage is greater than the preset time threshold only if there is no or little oscillation on the first and second sampled voltages, whereby the target voltage may be determined to be not in a ring state or the ring has ended. For example, in a case that ring detection submodule 1201 determines that the target voltage is not in a ring state, a signal indicating an end of the ring state may be output to output dip detection submodule 1202 of control module 130 and detection module 120, so that control module 130 controls sampling module 110 to stop outputting the first and second sampling voltages and outputs the third sampling voltage, and so that output dip detection submodule 1202 sample-holds the second sampling voltage at a time when sampling module 110 stops outputting the second sampling voltage.

It should be noted that, when both the first sampling voltage and the second sampling voltage oscillate, although the first sampling voltage may be larger than the second sampling voltage, the time corresponding to the oscillation may be very short in practice, and is usually smaller than the determination time in the control module 130, so that the erroneous determination may not occur.

It is understood that the control module 130 of the previous example may be replaced with the output drop detection sub-module 1202.

And an output drop detection submodule 1202, configured to compare the third sampling voltage with the second sampling voltage sampled and held by the sampling module at the moment when the sampling module stops outputting the second sampling voltage, and output a voltage drop signal when the third sampling voltage is less than the second sampling voltage sampled and held when the target voltage is not in a ringing state or waiting for the ringing of the target voltage to be ended and the sampling module 110 stops outputting the first sampling voltage and the second sampling voltage and outputs the third sampling voltage of the target voltage.

In a case where the sampling module 110 stops the second sampling voltage, the output droop detection sub-module 1202 sample-holds the current second sampling voltage, and compares the third sampling voltage with the currently sample-held second sampling voltage.

Specifically, under normal sampling, the third sampling voltage is greater than the second sampling voltage, but in the process that the load jumps from a light load to a heavy load, the output voltage will have a large drop, so the third sampling voltage will also drop, and under the condition that the third sampling voltage drops to be less than the second sampling voltage currently held by sampling, a voltage drop signal is output.

The percentage of the voltage dropped from the third sampling voltage is the ratio of the voltage dropped from the third sampling voltage to the third sampling voltage, and specifically includes: 1-sample-and-hold second sampled voltage/initially-collected third sampled voltage. Since the sampling and holding of the second sampling voltage and the start of the collection of the third sampling voltage occur at the same time, the second sampling voltage of the sampling and holding and the third sampling voltage of the initial collection can be regarded as the second sampling voltage and the third sampling voltage collected at the same time, when the ratio of the second sampling voltage to the target voltage is the second ratio and the ratio of the third sampling voltage to the target voltage is the third ratio, the percentage of the voltage dropped across the third sampling voltage =1- [ (the second ratio: [ target voltage ]/[ the third ratio ]/[ target voltage) ] = [ 1- (the second ratio/the third ratio) ], and since the second ratio/the third ratio is a fixed value, the percentage of the voltage dropped across the third sampling voltage is a fixed value, and thus it can be obtained that the drop detection submodule 1202 outputs the voltage drop signal when it is detected that the voltage across the third sampling voltage has dropped by a fixed percentage. Since the third sampling voltage is a sample of a target voltage that characterizes the output voltage, it is possible to obtain: in the case where the voltage at the third sampling voltage drops by a fixed percentage, the output voltage also drops by a fixed percentage, in which case the output drop detection submodule 1202 outputs a voltage drop signal.

Therefore, the detection of the output voltage drop in the embodiment of the application is the detection of the percentage of the output voltage drop, and the voltage drop signal is output under the condition that the percentage of the output voltage drop exceeds a set percentage. In this case, even if the output voltages in different system stable states are different in magnitude, since the percentage of the output voltage drop is detected, the detection result of whether the output voltage drops is not affected, and thus the accuracy and the universality of the detection result of the output voltage drop detection can be improved.

And the control module 130 is configured to control the secondary rectifier of the switching power supply to generate a short-circuit pulse according to the voltage drop signal, so as to increase the output voltage.

Therefore, in the embodiment of the application, under the condition that the secondary side of the switching power supply is turned off, whether the target voltage is in a ringing state or not can be determined based on the first sampling voltage and the second sampling voltage of the target voltage for representing the output voltage of the switching power supply, and after the target voltage is accurately determined not to be in the ringing state or the ringing state of the target voltage is waited to be ended, the output voltage is determined to drop when the third sampling voltage is reduced to be smaller than the second sampling voltage of the sampling hold, and a voltage drop signal is output based on the third sampling voltage of the target voltage and the second sampling voltage of the sampling hold. According to the voltage drop signal, a wake-up signal with fixed frequency is sent out by the wake-up module to regularly short-circuit the source and drain ends of the secondary rectifier tube, so that the secondary rectifier tube generates short-circuit pulses, the primary auxiliary winding detects oscillation signals of the short-circuit pulses to open the primary switching tube, and at the moment, the primary side responds quickly to supplement secondary energy and the output voltage is increased. Therefore, the embodiment of the application can effectively solve the problem that the accuracy of the detection result of the output voltage drop detection is low due to the fact that the accuracy of the sampling time of the output voltage cannot be guaranteed, the end moment of the ringing state of the target voltage can be accurately determined, the system can be self-adaptively judged that the output voltage drop sampling is not carried out when the system is in the ringing stage, the target voltage is directly sampled to carry out the purpose of the output voltage drop judgment when the system is not in the ringing stage, the timeliness and the accuracy of the target voltage sampling of the output voltage are guaranteed, the moment when the output voltage drops is accurately judged, the output voltage is timely awakened to rise, and the reliability of the system is improved. In some embodiments, after the secondary side of the switching power supply is turned off, if the primary side switch is turned on within a short time (for example, a first preset time hereinafter), it is not necessary to perform the steps of detecting whether the target voltage is in a ringing state and the subsequent steps thereof in the present application; if the primary side is not opened, the process in the application can be executed, so that when the output voltage is detected to drop, the secondary side rectifier tube of the switching power supply is controlled in time to generate short-circuit pulses, the primary side is enabled to respond quickly, the secondary side energy is supplemented, and the output voltage is boosted. It should be noted that in each embodiment of the present application, the primary side turning on refers to turning on of a primary side switching tube, and the primary side turning on is abbreviated; the primary side switch tube is only one code number and can also be called a primary side switch.

Based on this, as shown in fig. 3, the dynamic acceleration circuit 100 further includes: a timing module 301. The timing module 301 is connected to the sampling module 110, and the timing module 301 is further connected to the control module 130.

The timing module 301 is configured to start timing when the secondary side of the switching power supply is turned off, and output a first timing end signal to the control module 130 after timing a first preset time.

For example, in the case that the secondary side of the switching power supply is turned off, the sampling module 110 sends a signal to start timing to the timing module 301, so that the timing module 301 starts timing. The first preset time is set by a person skilled in the art according to actual conditions, and is not limited in the embodiment of the present application.

The control module 130 outputs a ring detection signal to the sampling module 110 according to the first timing end signal when the primary side of the switching power supply is determined not to be turned on.

The sampling module 110 outputs the first sampling voltage and the second sampling voltage in response to the ringing detection signal.

In some embodiments, whether the primary side responds or not can be detected, so that the dynamic acceleration circuit is turned off in advance, and the purpose of saving power consumption is achieved.

Turning off the dynamic acceleration circuit can be accomplished in three ways as follows.

The implementation mode is as follows: and under the condition that the primary side is switched on, the dynamic acceleration circuit is switched off. The sampling module 110, the detection module 120 and the control module 130 are used to detect whether the primary side responds. The method is realized as follows:

the sampling module 110 is further configured to stop outputting the third sampled voltage and output a fourth sampled voltage of the target voltage based on the voltage drop signal output by the detection module 120.

Specifically, the sampling module 110 may be connected to the output drop detection submodule 1202 in the detection module 120 to receive the voltage drop signal from the output drop detection submodule 1202, stop outputting the third sampled voltage based on the voltage drop signal, and output the fourth sampled voltage of the target voltage.

It should be noted that the fourth sampling voltage is smaller than the second sampling voltage. In some examples, the fourth sample voltage is at a fourth ratio to the target voltage, the fourth ratio being less than the second ratio. After the primary side of the switching power supply is turned on, the fourth sampling voltage is increased due to the turn-on of the primary side of the switching power supply.

The detection module 120 further includes a primary side response detection submodule 1203 (see fig. 4) configured to compare the fourth sampling voltage with the second sampling voltage sampled and held at the moment when the sampling module stops outputting the second sampling voltage, and output a primary side response signal when the fourth sampling voltage is increased to be greater than the second sampling voltage sampled and held due to the fact that a primary side switching tube of the switching power supply is turned on.

Specifically, the primary side response detection sub-module 1203 receives the fourth sampling voltage from the sampling module 110, compares the fourth sampling voltage with the second sampling voltage sampled and held in the foregoing embodiment, and initially, the fourth sampling voltage is smaller than the second sampling voltage, after the primary side is started, the output voltage increases, the fourth sampling voltage also increases, and when the fourth sampling voltage increases to be larger than the second sampling voltage, the primary side response signal is output to the control module 130.

Of course, it is understood that the primary side response detection sub-module 1203 may also receive the third sampling voltage and the second sampling voltage at the beginning, in this case, the sampling module 110 stops outputting the third sampling voltage and the second sampling voltage based on the voltage drop signal, outputs a fourth sampling voltage of the target voltage, and the primary side response detection sub-module 1203 performs sampling and holding on the second sampling voltage when the output is stopped, and then compares the magnitude of the fourth sampling voltage with the magnitude of the second sampling voltage subjected to sampling and holding.

The control module 130 is further configured to turn off the dynamic acceleration circuit according to the primary side response signal.

The dynamic accelerating circuit can be closed in advance by the method of actively detecting whether the primary side responds or not.

The implementation mode two is as follows: the primary side switching tube of the switching power supply is turned on based on short-circuit pulses generated by regular short circuits of the secondary side rectifying tube, and the short circuit of the secondary side rectifying tube is controlled by a wake-up signal with fixed conduction time. Accordingly, the control module 130 may turn off the dynamic acceleration circuit at the end of the fixed on-time timer. The fixed on-time may be a preset on-time required for the primary side to turn on. In this case, referring to fig. 4, after the control module 130 executes an operation of sending a wake-up signal by controlling the wake-up module to generate a short-circuit pulse to the secondary rectifier of the switching power supply according to the voltage droop signal, the timing module 301 may be controlled to start timing, and when the timing time of the timing module 301 is greater than a second preset time (i.e., a fixed on-time), the timing module 301 outputs a second timing end signal to the control module 130, and the control module 130 turns off the dynamic acceleration circuit according to the second timing end signal.

The implementation mode is three: the control module 130 turns off the dynamic acceleration circuit when the first secondary on-period after the primary is turned on.

For example, after the control module 130 determines that the primary side is turned on, the timing module 301 is started to start timing, and when the timing time of the timing module 301 is greater than a third preset time (set by a person skilled in the art according to an actual situation), the first secondary side conduction period after the primary side is turned on is started, at this time, the timing module 301 outputs a third timing end signal to the control module 130, and the control module 130 turns off the dynamic acceleration circuit according to the third timing end signal.

For example, as shown in fig. 2 to 4, the dynamic acceleration circuit 100 may further include: the control switch 140, and the control switch 140 may be a MOS transistor (e.g., an N-type MOS transistor). As shown in fig. 2 to 4, the control switch 140 is connected in parallel to the source-drain ends of a secondary rectifier tube (not shown in fig. 2 to 4, and specifically, see fig. 11) of the switching power supply, wherein the source of the control switch 140 is connected to the source S end of the secondary rectifier tube; the drain of the control switch 140 is connected to the drain D of the secondary rectifier via the current limiting resistor R, and the gate of the control switch 140 is connected to the control module 130.

The control module 130 can control the control switch 140 to be turned on according to the voltage drop signal, so that the control switch 140 regularly short-circuits the secondary rectifier tube, and the primary auxiliary winding detects the oscillation signal to turn on the primary switch tube, supplement the secondary energy, and increase the output voltage.

The control module 130 may control the control switch 140 to be turned off when the primary side is determined to be turned on or when the fixed on-time is timed out based on the primary side response signal, in which case the control switch 140 is not coupled to the secondary rectifier tube, so that the connection between the entire dynamic acceleration circuit and the secondary rectifier tube is disconnected, thereby turning off the entire dynamic acceleration circuit.

The circuit implementation of the sampling module 110, the detection module 120, and the control module 130 is described below.

The sampling module 110, the detection module 120, and the control module 130 of the present application may have different implementations for different applications.

In one embodiment, an application is to not actively detect whether the primary side is responding, that is, the detection module does not include a primary side response detection sub-module, and the synchronous rectification dynamic acceleration circuit is shown in fig. 3, in which case the structure of the sampling module 110 is shown in fig. 5A.

As shown in fig. 5A, the sampling module 110 may include a voltage divider circuit 501. The voltage divider circuit 501 includes a plurality of serially connected voltage dividing resistors (e.g., resistors R1 to R4 in fig. 5A) connected between the output terminal 5011 of the target voltage and ground, and a second switch S2, a third switch S3, a fourth switch S4, a first output terminal 5012, and a second output terminal 5013.

The voltage dividing circuit 501 has a second voltage dividing node N2, a third voltage dividing node N3, and a fourth voltage dividing node N4. The voltages of the second voltage division node N2, the third voltage division node N3 and the fourth voltage division node N4 are sequentially increased, the voltage at the second voltage division node N2 is greater than zero, and the voltage at the fourth voltage division node N4 is less than the target voltage.

As shown in fig. 5A, the fourth switch S4 connects the second voltage dividing node N2 and the second output terminal 5013, so that the second output terminal 5013 outputs the second sampled voltage Vds4 in the closed condition.

As shown in fig. 5A, the third switch S3 connects the third voltage division node N3 and the first output terminal 5012 so as to make the first output terminal 5012 output the first sampled voltage Vds3 in the closed condition (the second switch S2 is open).

As shown in fig. 5A, the second switch S2 connects the fourth voltage dividing node N4 and the first output terminal 5012 so as to cause the first output terminal 5012 to output the third sampled voltage Vds2 in the closed condition (both the fourth switch S4 and the third switch S3 are open).

It is understood that the number of the plurality of voltage dividing resistors connected in series in sequence includes, but is not limited to, 4 shown in fig. 5A, and may be 5, 6, 7, 8 \8230 \ 8230, etc., as long as the voltage dividing circuit 501 is ensured to have the second voltage dividing node N2, the third voltage dividing node N3, and the fourth voltage dividing node N4.

In the case where Vds (i.e., the target voltage) is large, the voltage output by the sampling module 110 is also large. For example, vds may be hundreds of volts (e.g., 200 volts), in which case the voltage output by the sampling module 110 may correspond to tens of volts, and an excessively high voltage may cause the chip circuitry connected to the sampling module 110 to burn out. Based on this, to avoid the above situation, in some embodiments, with continued reference to fig. 5A, the sampling module 110 further includes: a clamp 502.

The clamp circuit 502 is connected to the voltage divider circuit 501, specifically to an output terminal 5011 of a target voltage through at least one voltage dividing resistor in the voltage divider circuit 501, and a voltage at a connection point of the clamp circuit 502 and the voltage divider circuit 501 is greater than or equal to a voltage at a fourth voltage dividing node N4.

In fig. 5A, the clamp circuit 502 is connected to the output terminal 5011 of the target voltage via a resistor R5 in the voltage divider circuit 501. It will be appreciated that the resistor R5 may also be replaced by two or more resistors in series. By providing the clamp circuit 502, the voltage at the connection between the clamp circuit 502 and the output 5011 of the target voltage does not exceed the set clamp voltage V when Vds is large _clamp To ensure that the voltages output at the first output terminal 5012 and the second output terminal 5013 are not too large, to ensure that the chip circuit connected to the sampling module 110 is not burned out,the application range of the dynamic response circuit 100 is expanded.

V _clamp The method is set by a person skilled in the art according to practical situations, and the embodiment of the present application is not limited thereto. Taking the circuit shown in FIG. 5A as an example, at 0<Vds≤V _clamp *R _{General (1)} /（R ₂ +R ₃ +R ₄ ) In the case of (2), vds2, vds3, vds4 satisfy:

Vds2=Vds*（R ₂ +R ₃ +R ₄ ）/R _{general assembly} ；

Vds3=Vds*（R ₂ +R ₃ ）/R _{General (1)} ；

Vds4=Vds*R ₂ /R _{General assembly} ；

Wherein R is _{General assembly} =R ₂ +R ₃ +R ₄ +R ₅ 。

It can be seen that, at 0<vds≤V _clamp *R _{General (1)} /（R ₂ +R ₃ +R ₄ ) In the case of (3), vds2, vds3, vds4 are proportional to Vds, and the change in Vds can be accurately reflected.

Taking the circuit shown in fig. 5A as an example, in the case where the secondary side of the switching power supply is turned off, the third switch S3 and the fourth switch S4 in the voltage dividing circuit 501 of the sampling module 110 are closed, in which case the first output terminal 5012 outputs the first sampled voltage Vds3 and the second output terminal 5013 outputs the second sampled voltage Vds4. Ratio of Vds3 to Vds first ratio, first ratio = (R) ₂ +R ₃ ）/R _{General assembly} Vds4 to Vds ratio is a second ratio, the second ratio = R ₂ /R _{General (1)} ，[（R ₂ +R ₃ ）/R _{General (1)} ]>[R ₂ /R _{General assembly} ]The first ratio is greater than the second ratio, and thus the first sampling voltage is greater than the second sampling voltage.

In the case of using an ideal comparator, the closer the first ratio and the second ratio are, i.e., (Vds 3-Vds 4)/Vds = R ₃ /R _{General (1)} The smaller the detection module 120, the higher the accuracy of the determination result of whether the target voltage is in the ringing state based on the first and second sampling voltages. In this case, R can be set appropriately ₂ ~R ₅ Such that R is caused to be equal to R without affecting other detection results (e.g., a detection result of whether a voltage drop signal is output or not, a detection result of whether a primary side response signal is output or not) ₃ /R _{General assembly} As small as possible.

In another embodiment, an application is to actively detect whether the primary side responds, i.e., the detection module includes a primary side response detection sub-module, and the synchronous rectification dynamic acceleration circuit is shown in fig. 4, in which case the structure of the sampling module 110 is shown in fig. 5B.

Fig. 5B is different from fig. 5A in that the sampling module 110 further includes a first switch S1, and the voltage dividing circuit 501 further has a first voltage dividing node N1. The voltages of the first voltage division node N1, the second voltage division node N2, the third voltage division node N3 and the fourth voltage division node N4 are sequentially increased in an increasing manner, and the voltage at the first voltage division node N1 is greater than zero.

As shown in fig. 5B, the first switch S1 connects the first voltage division node N1 and the first output terminal 5012 so as to make the first output terminal 5012 output the fourth sampled voltage Vds1 in a closed condition (both the second switch S2 and the third switch S3 are open). For the outputs of the first sampling voltage Vds3, the second sampling voltage Vds4, and the third sampling voltage Vds2, reference may be made to fig. 5A, which is not repeated herein.

It is understood that the number of the plurality of voltage dividing resistors connected in series in sequence includes, but is not limited to, 5 shown in fig. 5B, and may also be 6, 7, 8 \8230 \ 8230, etc., as long as the voltage dividing circuit 501 is ensured to have the first voltage dividing node N1, the second voltage dividing node N2, the third voltage dividing node N3 and the fourth voltage dividing node N4.

As shown in fig. 5B, the sampling module 110 of the present embodiment also includes a clamping circuit 502. The function of the clamp circuit 502 can be referred to the above description, and is not repeated herein.

Take the circuit shown in FIG. 5B as an example, at 0<Vds≤V _clamp *R _{General assembly} /（R ₁ +R ₂ +R ₃ +R ₄ ) In the case of (1), vds1, vds2, vds3, vds4 satisfy:

Vds1=Vds*R ₁ /R _{general assembly} ；

Vds2=Vds*（R ₁ +R ₂ +R ₃ +R ₄ ）/R _{General assembly} ；

Vds3=Vds*（R ₁ +R ₂ +R ₃ ）/R _{General assembly} ；

Vds4=Vds*（R ₁ +R ₂ ）/R _{General assembly} ；

Wherein R is _{General assembly} =R ₁ +R ₂ +R ₃ +R ₄ +R ₅ 。

It can be seen that, at 0<vds≤V _clamp *R _{General assembly} /（R ₁ +R ₂ +R ₃ +R ₄ ) In the case of (3), vds1, vds2, vds3, vds4 are proportional to Vds, and the change in Vds can be accurately reflected.

In some embodiments, the circuit of the ring detection submodule 1201 in the detection module 120 is shown in fig. 6, and includes a first comparator 601, a current source 602, a MOS transistor 603, a first capacitor 604, a schmitt trigger 605, a D-flip-flop 606, and a first sample-and-hold circuit 607.

As shown in fig. 6, the inverting terminal of the first comparator 601 is coupled to the first output terminal 5012, and the non-inverting terminal of the first comparator 601 is coupled to the second output terminal 5013 through the first sample-and-hold circuit 607 (e.g., an RC circuit in fig. 6). In this case, the first terminal 6041 of the first capacitor 604 is connected to the connection node between the current source 602 and the MOS transistor 603, the second terminal 6042 of the first capacitor 604 is grounded, the MOS transistor 603 may be an N-type MOS transistor, the drain of the MOS transistor 603 is connected to the current source 602, and the source of the MOS transistor 603 is grounded. The current direction of the current source 602 is from the drain to the source of the MOS transistor 603.

With continued reference to fig. 6, the output terminal of the first comparator 601 is connected to the gate of the MOS transistor 603. An input 6051 of the Schmitt trigger 605 is coupled to the first terminal 6041 of the first capacitor 604, an output 6052 of the Schmitt trigger 605 is coupled to an input 6061 of the D-flip-flop 606, and an output 6062 of the D-flip-flop 606 is coupled to the output droop detection sub-module 1202.

Taking the circuit shown in fig. 6 as an example, the inverting terminal of the first comparator 601 receives the first sampled voltage Vds3 from the first output terminal 5012, the non-inverting terminal of the first comparator 601 receives the second sampled voltage Vds4 from the second output terminal 5013, and since the second output terminal 5013 is coupled to the non-inverting terminal of the first comparator 601 through the RC circuit, the phase of Vds4 changes after passing through the RC circuit, in this case, a phase difference occurs between Vds3 and Vds4, vds3 and Vds4 must overlap, and the first comparator 601 outputs an oscillation signal.

In the case where the target voltage is not in the ringing state or the ringing state has ended, there is no oscillation on Vds3 and Vds4, vds3 is continuously greater than Vds4 and exceeds the preset time threshold, the output on the first comparator 601 is continuously low, so that the first capacitor 604 is continuously charged high enough to cause the schmitt trigger 605 to flip over the schmitt trigger 605 to output a high level, and the D-flip-flop outputs a high level, i.e., a drop detection on signal (e.g., switch in fig. 6).

Under the condition that the target voltage is in a ringing state, the Vds3 and the Vds4 oscillate, a signal obtained after the Vds3 and the Vds4 are overlapped is an oscillation signal, and the oscillation period of the oscillation signal is smaller than a preset period, in this case, the first capacitor 604 is repeatedly charged and discharged, so that the voltage on the first capacitor 604 cannot be charged high enough to turn over the schmitt trigger 605, the schmitt trigger 605 outputs a low level, and the D trigger outputs a low level. When the ringing state of the target voltage is over, the oscillation period of the oscillation signal is greater than the preset period, where Vds3> Vds4, the output of the first comparator 601 is low continuously, the voltage of the first capacitor 604 may be charged high to flip the schmitt trigger 605, the schmitt trigger 605 outputs a high level, and the D-flip-flop outputs a high level, i.e., a drop detection enable signal (e.g., switch in fig. 6). The voltage on the first capacitor 604 continues to be charged high for the time required to flip the schmitt trigger 605, i.e., the preset time threshold.

In some embodiments, the circuit diagram of the output drop detection submodule 1202 may be as shown in fig. 7, including a second sample-and-hold circuit 701, a second comparator 702, and an and-gate circuit 703.

As shown in fig. 7, the input end 7011 of the second sample-and-hold circuit 701 is connected to the second output end 5013, the output end 7012 of the second sample-and-hold circuit 701 is connected to the non-inverting end of the second comparator 702, the inverting end of the second comparator 702 is connected to the first output end 5012, the output end of the second comparator 702 is connected to one input end of the and circuit 703, the other input end of the and circuit 703 is connected to the ring detection submodule 1201 (not shown in fig. 7) to receive a fall detection start signal (e.g., switch in fig. 7) from the ring detection submodule 1201, and the output end of the and circuit 703 is connected to the control module 130.

As shown in fig. 5A and 7, in a case where the ring detection sub-module 1201 outputs the drop detection on signal, the third switch S3 is opened, the fourth switch S4 is opened, and the second switch S2 is closed in the voltage division circuit 501 of the sampling module 110, in which case the third sampling voltage Vds2 is output at the first output terminal 5012, and the second sampling voltage Vds4 is stopped at the second output terminal 5013.

If the first output terminal 5012 is connected to the inverting terminal of the second comparator 702, the inverting terminal of the second comparator 702 receives the third sampled voltage Vds2.

Since the second output terminal 5013 is coupled to the non-inverting terminal of the second comparator 702 through the second sample-and-hold circuit 701, the second sample-and-hold circuit 701 sample-and-holds the current second sampled voltage Vds4 under the condition that the second output terminal 5013 stops the second sampled voltage Vds4, so that the second sampled voltage Vds4 which is sample-and-held is received at the non-inverting terminal of the second comparator 702.

The second comparator 702 compares the third sampling voltage Vds2 with the second sampling voltage Vds4, and when the output voltage is stable (i.e., a large drop does not occur), (Vds 2-Vds 4)/Vds = (R) ₃ +R ₄ ）/R _{General assembly} Thus vds2>vds4, the second comparator 702 outputs a low level, since the falling detection on signal (switch in fig. 7) is a high level, the and circuit 703 outputs a low level to the control module 130; as shown in FIG. 5A, the output voltage drops [ (R) ₃ +R ₄ ）/R ₂ ]% after, or as in FIG. 5B, at the output voltage drop [ (R) ₃ +R ₄ ）/（R ₁ +R ₂ ）]% after, i.e. vds2<In vds4, the second comparator 702 outputs a high level, and in this case, the and circuit 703 outputs a high level (i.e., a voltage drop signal)Number) to the control module 130.

The magnitude of this ratio is related to the magnitude of the drop of the output voltage, so the smaller this value is set, the smaller the drop of the output voltage is, and the greater the accuracy in output is.

In some embodiments, as shown in fig. 8, primary side response detection submodule 1203 includes a third sample and hold circuit 801 and a third comparator 802.

An input terminal 8011 of the third sample-and-hold circuit 801 is connected to the second output terminal 5013, an output terminal 8012 of the third sample-and-hold circuit 801 is connected to the non-inverting terminal of the third comparator 802, and the inverting terminal of the third comparator 802 is connected to the first output terminal 5012. The output of the third comparator 802 is connected to the control module 130.

As shown in fig. 4, 5B and 8, after the output drop detection sub-module 1202 outputs the voltage drop signal, the control module 130 may control the sampling module 110 to open the second switch S2 and the fourth switch S4 and close the first switch S1, in which case the fourth sampled voltage Vds1 is output at the first output terminal 5012 and the second sampled voltage Vds4 is stopped at the second output terminal 5013.

If the first output terminal 5012 is connected to the inverting terminal of the third comparator 802, the inverting terminal of the third comparator 802 receives the fourth sampled voltage Vds1. Since the second output terminal 5013 is coupled to the non-inverting terminal of the third comparator 802 through the third sample-and-hold circuit 801, the third sample-and-hold circuit 801 sample-and-hold the current second sampled voltage Vds4 in the case that the second sampled voltage Vds4 is stopped at the second output terminal 5013, and thus the second sampled voltage Vds4 which is sample-and-held is received at the non-inverting terminal of the third comparator 802.

The third comparator 802 compares the fourth sampling voltage Vds1 with the second sampling voltage Vds4 of the sample-and-hold, and in the case where the primary side is not activated (responded), (Vds 4-Vds 1)/Vds = R ₂ /R _{General assembly} Thus vds4>vds1, the third comparator 802 outputs high; in case of primary side starting, vds rises, and the fourth sampling voltage Vds1 also rises, and the Vds rises to Vds R ₂ /R ₁ Thereafter, vds1>vds4, the third comparator 802 outputs a low level (i.e., the primary side response signal) to the control module 130.

For example, in an application where the detection module does not actively detect whether the primary side is responding, i.e., the detection module does not include a primary side response detection sub-module, the synchronous rectification dynamic acceleration circuit is shown in fig. 3, and in this case, the structure of the control module 130 is shown in fig. 9A.

As shown in fig. 9A, the control module 130 includes: a wake-up unit 901, a control logic unit 902, a nand logic unit 903, and an inverter 904.

The wake-up unit 901 is configured to send a wake-up signal with a fixed turn-on frequency and a fixed turn-on time, so that the secondary rectifier of the switching power supply generates a short-circuit pulse.

The wake-up signal is, for example, one or a group of pulse signals with a predetermined pulse width, a primary side switch tube of the switching power supply is turned on based on an oscillation signal generated by a short circuit of a secondary side rectifier tube, and the short circuit of the secondary side rectifier tube is controlled by the wake-up signal with a fixed frequency and a fixed conduction time.

The control logic 902 has an input terminal one 9021, an input terminal two 9022, an output terminal one 9023, and an output terminal two 9024.

Input end one 9021 may be connected to ring detection submodule 1201 and output drop detection submodule 1202.

For example, as shown in fig. 6 and fig. 9A, input terminal one 9021 may be connected to an output terminal of D flip-flop 606 in ring detection submodule 1201, so as to receive a signal (e.g., a fall detection on signal, i.e., a switch) output on D flip-flop 606.

For example, as shown in fig. 7 and 9A, input terminal one 9021 may be connected to an output terminal of the and circuit 703 in the output droop detection sub-module 1202 to receive a signal (e.g., a voltage droop signal) output on the and circuit 703.

The first output end 9023 outputs the detection result of the output drop detection submodule 1201, the second output end 9024 is connected with the wake-up unit 901, and the wake-up unit 901 and the first output end 9023 are connected with the plurality of input ends of the nand logic unit 903 in a one-to-one correspondence manner.

The output terminal of the nand logic unit 903 is connected to the input terminal of the inverter 904, and the output terminal of the inverter 904 is the output terminal of the control block.

Specifically, dyat _ s defaults to low and toff _ dlar defaults to high. When the first input end 9021 of the control logic unit 902 receives the high level output by the and circuit 703, or the input end of the control logic unit 902 receives a high level signal output by the D flip-flop 606 in the ring detection submodule, the control logic unit 902 controls the first output end 9023 to correspondingly output a high level (i.e., dyat _ s is converted from a low level to a high level), and controls the wake-up unit to output a wake-up signal to control the secondary rectifier tube to generate a short-circuit pulse.

In another embodiment, an application is to actively detect whether the primary side is responding, i.e., the detection module includes a primary side response detection sub-module, the synchronous rectification dynamic acceleration circuit is shown in fig. 4, and in this case, the control module 130 is configured as shown in fig. 9B.

Fig. 9B is different from fig. 9A in that the control logic unit 902 in the control module further includes an output terminal three 9025 connected to the input terminal of the nand logic unit 903 in a one-to-one correspondence manner, where the input terminal one 9021 is further connected to the primary side response detection submodule 1203, and the output terminal three 9025 outputs a detection result of the primary side response detection submodule 1203.

For example, as shown in fig. 8 and 9B, input one 9021 may also be connected to an output of a third comparator 802 in output drop detection submodule 1202 to receive a signal (e.g., a primary side response signal) output by third comparator 802. And the output end three 9025 outputs the detection result of the primary side response detection submodule 1203.

After the wake-up unit starts to operate, the first input end 9021 of the control logic unit 902 receives a signal output by the third comparator 802, and when the signal is at a low level (indicating that the primary side is started), the control logic unit 902 controls the third output end 9025 to output a low level (i.e., toff _ dlar is converted from a high level to a low level).

The second input terminal 9022 may be connected to the timing module 301 in the dynamic acceleration circuit 100, and when the dyat _ s is converted from the low level to the high level, if the timing module starts timing and the timing time count _ over reaches a second preset time, the control logic unit 902 turns off the dynamic acceleration circuit.

In some embodiments, in order to make the circuit simpler and more efficient, the first comparator 601, the second comparator 702 and the third comparator 802 may multiplex the same comparator, and the first sample-and-hold circuit 607, the second sample-and-hold circuit 701 and the third sample-and-hold circuit 702 may multiplex the same circuit, such as the RC circuits in fig. 6 to 8. In this case, fig. 10 shows an operation waveform diagram of a dynamic acceleration circuit.

As shown in fig. 10, the secondary side of the switching power supply is turned off at time T1, the target voltage Vds starts to oscillate, at this time, the timing module 301 starts to time, when the timing reaches time T2 (T1-T2 = a first preset time), it is detected that the primary side is not started yet, the dynamic acceleration circuit starts to detect whether Vds is in a ringing state (corresponding to the ringing detection portion in fig. 10), first, the sampling module acquires the target voltage and outputs a first sampling voltage and a second sampling voltage, the comparator outputs a comparison result of the first sampling voltage and the second sampling voltage, see a waveform corresponding to "comparator output" in fig. 10, at a stage when Vds is in the ringing state (from time T2 to time T3), a signal output by the ringing detection submodule is as a waveform corresponding to switch in fig. 10, and is low level before time T3, and the first sampling voltage is detected to be greater than the second sampling voltage at time T3 and the duration time exceeds a preset time threshold, and is switched from the low level to the high level.

The period from time T3 to time T4 is a period for detecting an output voltage drop. The inverting terminal of the comparator receives Vds2, the non-inverting terminal of the comparator receives Vds4 held by sampling, when the output voltage does not drop greatly, vds2 is greater than Vds4, and the output of the comparator is low level as shown in fig. 10; at the time of T4, the output voltage has dropped by the set percentage, vds2 is less than Vds4, the output of the comparator is a high level, and at this time, the secondary rectifier tube of the switching power supply is awakened to generate a short-circuit pulse, and it can be seen from fig. 10 that the waveform of dayt from the time of T4 is a square wave signal, which means that the control module 130 outputs an awakening signal and controls the secondary rectifier tube of the switching power supply to generate a short-circuit pulse, so that the primary side auxiliary winding detects an oscillation signal to turn on the primary side switching tube; meanwhile, an inverting terminal of the comparator receives Vds1, a non-inverting terminal of the comparator receives a sample hold Vds4 to detect whether a primary side is opened or not, vds1 is smaller than Vds4 at the beginning, and the output of the comparator is still high level; at the time T5, vds1> Vds4 (where Vds1 is preferably greater than the maximum peak value of Vds oscillation in the period from T2 to T3 to avoid false triggering), the comparator output is switched from a high level to a low level, the primary side is determined to be on at this time, the dynamic acceleration circuit is actively turned off through the nand logic unit 903 and the inverter 904 in the control module, the comparator output is a low level at this time, switch is a low level, and dayt is switched from a square wave signal to a low level signal. Of course, when the timing module times for more than the second preset time (i.e., the fixed on-time), the timing signal count _ over will be switched from the low level to the high level, and at this time, the control module also turns off the dynamic acceleration circuit.

The embodiment of the application also provides a synchronous rectification control circuit. As shown in fig. 11, the synchronous rectification control circuit 1100 includes the dynamic acceleration circuit 100 as described in the above embodiment, the sampling module 110 of the dynamic acceleration circuit 100 is coupled to the source and drain (i.e., source and drain) of the secondary rectifier 1110 of the switching power supply, and the control module 130 of the dynamic acceleration circuit 100 is connected to the gate of the control switch 140 connected in parallel to the source and drain of the secondary rectifier 1110.

The embodiment of the application further provides a switching power supply. As shown in fig. 12, the switching power supply 1200 includes: the synchronous rectification control circuit comprises a primary winding 1210, a primary switch tube 1220 connected with the primary winding 1210, a secondary winding 1230, a secondary rectification tube 1110 connected with the secondary winding 1230, and the synchronous rectification control circuit 1100 in the embodiment.

Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the market, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the application is defined by the appended claims.

Claims

1. A synchronous rectification dynamic acceleration circuit, the dynamic acceleration circuit comprising: sampling module, detection module and control module, wherein:

the sampling module is used for outputting a first sampling voltage and a second sampling voltage which can represent a target voltage of the output voltage of the switching power supply under the condition that the secondary side of the switching power supply is turned off; and after the detection module determines that the target voltage is not in a ringing state or waits for the ringing of the target voltage to finish, stopping outputting the first sampling voltage and the second sampling voltage, and outputting a third sampling voltage of the target voltage;

the detection module is used for judging whether the target voltage is in a ringing state or not based on a comparison result of the first sampling voltage and the second sampling voltage, comparing the third sampling voltage with the second sampling voltage sampled and held by the sampling module at the moment when the sampling module stops outputting the second sampling voltage after determining that the target voltage is not in the ringing state or waiting for the ringing of the target voltage to be finished, and outputting a voltage drop signal when the third sampling voltage is reduced to be smaller than the second sampling voltage sampled and held by the sampling module;

2. The synchronous rectification dynamic acceleration circuit of claim 1, wherein the detection module comprises: the ringing detection submodule is used for comparing the first sampling voltage with the second sampling voltage and determining that the target voltage is not in a ringing state or the ringing is finished under the condition that the first sampling voltage is greater than the second sampling voltage and the duration time exceeds a preset time threshold;

and the output drop detection submodule is used for comparing the third sampling voltage with the second sampling voltage which is sampled and held at the moment when the sampling module stops outputting the second sampling voltage under the condition that the target voltage is not in a ringing state or the ringing is finished and the sampling module stops outputting the first sampling voltage and the second sampling voltage and outputting the third sampling voltage of the target voltage, and outputting the voltage drop signal when the third sampling voltage is smaller than the second sampling voltage which is sampled and held.

3. The synchronous rectification dynamic acceleration circuit of claim 2, wherein the control module comprises: the device comprises a wake-up unit, a control logic unit, a NAND logic unit and an inverter; wherein the content of the first and second substances,

the control logic unit is provided with an input end I, an input end II, an output end I and an output end II, wherein the input end I is respectively connected with the ringing detection submodule and the output falling detection submodule, the input end II is connected with a timing module in the dynamic accelerating circuit, the output end I outputs a detection result of the output falling detection submodule, the output end II is connected with the awakening unit, and the awakening unit, the output end I and the plurality of input ends of the NAND logic unit are correspondingly connected one by one;

and the output end of the NAND logic unit is connected with the input end of the phase inverter, and the output end of the phase inverter is the output end of the control module.

4. The synchronous rectification dynamic accelerating circuit according to any one of claims 1 to 3, wherein the sampling module comprises a plurality of voltage dividing resistors connected in series in sequence between the output end of the target voltage and the ground, and a second switch, a third switch, a fourth switch, a first output end, a second output end and a clamping circuit;

sequentially determining a second voltage division node, a third voltage division node and a fourth voltage division node from a voltage division circuit in which the voltage division resistors which are sequentially connected in series are located, wherein the voltages of the second voltage division node, the third voltage division node and the fourth voltage division node are sequentially increased, the voltage of the second voltage division node is greater than zero, and the voltage of the fourth voltage division node is smaller than the target voltage;

the fourth switch connects the second voltage-dividing node and the second output terminal so as to cause the second output terminal to output the second sampling voltage in a closed condition;

the third switch connects the third voltage division node and the first output terminal so as to cause the first output terminal to output the first sampling voltage in a closed condition;

the clamp circuit is connected with the output end of the target voltage through at least one voltage dividing resistor in the voltage dividing circuit, and the voltage at the connection position of the clamp circuit and the voltage dividing circuit is greater than or equal to the voltage at the fourth voltage dividing node.

5. The synchronous rectification dynamic acceleration circuit of claim 2,

the sampling module is further configured to stop outputting the third sampling voltage based on the voltage drop signal output by the detection module, and output a fourth sampling voltage of the target voltage;

the detection module further comprises:

the primary side response detection submodule is used for comparing the fourth sampling voltage with the second sampling voltage sampled and held at the moment that the sampling module stops outputting the second sampling voltage, and outputting a primary side response signal when the fourth sampling voltage is increased to be larger than the second sampling voltage sampled and held due to the primary side of the switching power supply being started; the primary side of the switching power supply is started based on short-circuit pulses generated by the secondary rectifier tube, and the short-circuit pulses generated by the secondary rectifier tube are controlled by wake-up signals with fixed conduction frequency and fixed conduction time;

the control module is further configured to turn off the dynamic acceleration circuit according to the primary side response signal or when the fixed on-time is timed out.

6. The synchronous rectification dynamic acceleration circuit of claim 5, wherein the control module comprises: the device comprises a wake-up unit, a control logic unit, a NAND logic unit and an inverter; wherein the content of the first and second substances,

the wake-up unit is used for sending out the wake-up signal;

the control logic unit is provided with an input end I, an input end II, an output end I, an output end II and an output end III, wherein the input end I is respectively connected with the ringing detection submodule, the output falling detection submodule and the primary side response detection submodule;

7. The synchronous rectification dynamic acceleration circuit of claim 5, wherein the sampling module comprises a plurality of voltage dividing resistors connected in series in sequence between the output terminal of the target voltage and ground, and a first switch, a second switch, a third switch, a fourth switch, a first output terminal and a second output terminal;

sequentially determining a first voltage division node, a second voltage division node, a third voltage division node and a fourth voltage division node from a voltage division circuit in which the plurality of voltage division resistors which are sequentially connected in series are located, wherein the voltages at the first voltage division node, the second voltage division node, the third voltage division node and the fourth voltage division node are sequentially increased progressively, the voltage at the first voltage division node is greater than zero, and the voltage at the fourth voltage division node is less than the target voltage;

the first switch connects the first voltage division node and the first output terminal so as to enable the first output terminal to output the fourth sampling voltage in a closed condition;

the second switch is connected with the fourth voltage dividing node and the first output end so as to enable the first output end to output the third sampling voltage under the closed condition;

8. The synchronous rectification dynamic accelerating circuit of claim 2, wherein the sampling module comprises a first output terminal and a second output terminal, and the ringing detection submodule comprises a first comparator, a first sample-and-hold circuit, a current source, a MOS transistor, a first capacitor, a schmitt trigger, and a D trigger; the current source is connected with the MOS tube in series and then grounded;

the in-phase end and the anti-phase end of the first comparator are respectively coupled with the second sampling voltage output by the second output end and the first sampling voltage output by the first output end, and the output end of the first comparator is connected with the grid electrode of the MOS tube; the input end of the first sampling and holding circuit is connected with the second output end, and the output end of the first sampling and holding circuit is connected with the in-phase end of the first comparator;

the first end of the first capacitor is connected to the node of the current source and the MOS tube, and the second end of the first capacitor is grounded;

9. The synchronous rectification dynamic acceleration circuit of claim 2, wherein the sampling module comprises a first output terminal and a second output terminal, and the output drop detection submodule comprises a second sample-and-hold circuit, a second comparator and an and-gate circuit; the input end of the second sample-and-hold circuit is connected with the second output end to receive the second sampled voltage, the output end of the second sample-and-hold circuit is connected with the in-phase end of the second comparator, the inverting end of the second comparator is connected with the first output end to receive the third sampled voltage, the output end of the second comparator is connected with one input end of the and-gate circuit, the other input end of the and-gate circuit is connected with a drop detection start signal sent by the ringing detection submodule when the target voltage is determined not to be in a ringing state, and the output end of the and-gate circuit is connected with the control module.

10. The synchronous rectification dynamic acceleration circuit of any one of claims 5 to 7, wherein the sampling module comprises a first output terminal and a second output terminal, and the primary side response detection submodule comprises a third sample-and-hold circuit and a third comparator; the input end of the third sample-and-hold circuit is connected with the second output end to receive the second sampling voltage, the output end of the third sample-and-hold circuit is connected with the in-phase end of the third comparator, the inverting end of the third comparator is connected with the first output end to receive the fourth sampling voltage, and the output end of the third comparator is connected with the control module.

11. The synchronous rectification dynamic acceleration circuit of claim 5, wherein the ring detection submodule comprises a first sample-and-hold circuit, a first comparator, the output droop detection submodule comprises a second sample-and-hold circuit, a second comparator, and the primary side response detection submodule comprises a third sample-and-hold circuit and a third comparator, wherein the first comparator, the second comparator, and the third comparator multiplex the same comparator, and wherein the first sample-and-hold circuit, the second sample-and-hold circuit, and the third sample-and-hold circuit multiplex the same sample-and-hold circuit.

12. The synchronous rectification dynamic acceleration circuit according to any one of claims 1 to 3, further comprising: the timing module is connected with the sampling module and the control module; wherein:

the control module is further configured to output a ring detection signal to the sampling module according to the first timing end signal under the condition that the primary side of the switching power supply is determined not to be turned on;

the sampling module is specifically configured to: and outputting the first sampling voltage and the second sampling voltage in response to the ringing detection signal.

13. A synchronous rectification control circuit, characterized in that, the synchronous rectification control circuit comprises a synchronous rectification dynamic accelerating circuit as claimed in any one of claims 1 to 12, a sampling module of the dynamic accelerating circuit is coupled with a source drain of a secondary rectifier tube of a switching power supply, and a control module of the dynamic accelerating circuit is connected with a grid of a control switch connected in parallel at two ends of the source drain of the secondary rectifier tube.

14. A switching power supply comprising a primary winding, a primary switching tube and a secondary winding connected to the primary winding, a secondary rectifier tube connected to the secondary winding, and a synchronous rectification control circuit as claimed in claim 13.