WO2016019788A1

WO2016019788A1 - Dynamic quick response method and circuit of switching power supply

Info

Publication number: WO2016019788A1
Application number: PCT/CN2015/084179
Authority: WO
Inventors: 唐盛斌
Original assignee: 广州金升阳科技有限公司
Priority date: 2014-08-06
Filing date: 2015-07-16
Publication date: 2016-02-11
Also published as: CN104167923B; CN104167923A

Abstract

A dynamic quick response method of a switching power supply. The method comprises the following steps: a drop quick response step, i.e., when it is detected that the voltage at an FB end suddenly increases rapidly, sending a drop dynamic response signal, rapidly providing current to the FB end, and stopping providing the current to the FB end after the voltage at the FB end rises to a first preset value; an overshoot quick response step, i.e., when it is detected that the voltage at the FB end suddenly decreases rapidly, sending an overshoot dynamic response signal, rapidly extracting the current at the FB end, and stopping extracting the current at the FB end after the voltage at the FB end drops to a second preset value; and a steady state judgment step, i.e., judging whether a voltage loop of the switching power supply enters a steady state, if the voltage loop enters the steady state, allowing the output of the drop dynamic response signal or the overshoot dynamic response signal, and if the voltage loop does not enter the steady state, not allowing the output of the drop dynamic response signal or the overshoot dynamic response signal. The method can increase the dynamic response speed of the switching power supply.

Description

Dynamic fast response method and circuit of switching power supply

Technical field

The invention relates to a controller for a secondary side feedback switching power supply, in particular to a dynamic response of a switching power supply output voltage.

Background technique

With the continuous development of switching power supply technology, switching power supplies have become the main power supply for electrical appliances, and transformers are used to achieve electrical isolation to improve safety. Figure 1 shows the commonly used secondary feedback control of the flyback switching power supply. The resistors R1 and R2 are output voltage sampling resistors. Their partial voltage is used as the input signal of the TL431. The signal is amplified by a transconductance amplifier composed of TL431 and optocoupler. Transfer to the FB input of the controller (the FB input of the controller, also known as the voltage feedback input of the controller, hereinafter referred to as the FB terminal). Therefore, the voltage V _FB of the FB port reflects the magnitude of the power supply output voltage V _OUT , which is often referred to as a voltage feedback loop, and is also referred to as a secondary voltage feedback loop because it senses the output voltage from the secondary side of the transformer. The controller controls the output voltage according to the size of V _FB modulating the duty cycle of the GATE output. When the output voltage V _{OUT is} high, the optocoupler draws more current from the FB pin, causing V _{FB to} drop, and the duty cycle of the GATE output. When it becomes smaller, the output voltage V _OUT gradually decreases. When the output voltage is small, the optocoupler draws a smaller current from the FB pin, so that V _FB increases, the duty ratio of the GATE output becomes larger, and the output voltage V _OUT gradually increases. Therefore, the output voltage is stabilized at a set value by continuous adjustment of the loop. Since this secondary side control directly samples the voltage from the output terminal, the output voltage can be made highly accurate, so it is widely used in applications requiring high output voltage accuracy.

In today's energy resources are rapidly consumed, people's awareness of energy conservation continues to strengthen, how to design and manufacture energy-efficient green power products has become a subject of continuous research, and thus has produced a variety of switching power supplies that optimize the frequency reduction control. Although the light load reduces the switching frequency significantly improves the efficiency and standby power consumption of the switching power supply, the dynamic response of sudden load under light load or no-load condition becomes poor due to the frequency reduction, and the output voltage drops sharply. Especially in the high-power DCDC power supply, due to the small size of the output capacitor, if the frequency is low at no load, sudden loading will cause the output voltage to drop to an unacceptable level. The dynamic response of the switching power supply after light load or no-load frequency reduction is mainly due to two reasons: The first reason is the bandwidth of the control loop. It is well known that to make the loop of the switching power supply stable and effectively suppress the switching noise, the closed loop bandwidth of the control loop should be less than one tenth of the switching frequency, so the light load down-conversion control mode further limits the bandwidth of the control loop. So that the dynamic response is worse than the case of no down-conversion. The second reason is the compensator's compensation capacitor's slew rate limit. As shown in Figure 1, the maximum output current of the FB terminal of the controller is limited, because if the quiescent bias current of the optocoupler is too large, the bias circuits on both sides of the optocoupler will consume a large amount of power. Therefore, the effective bias current provided by FB limits the slew rate of the compensation capacitor C _C1 , so that the slew rate of the C _C1 capacitor is not large enough in dynamic response, resulting in dynamic response delay, large overshoot and undershoot of the output voltage. . Especially for the switching power supply with light load working in the green working mode of frequency reduction, in order to make the loop stable, the compensation capacitor C _C1 value is larger than the case of no frequency reduction. Although the light-loaded green frequency-down mode of operation is widely used in ACDC control chips, it is because of the poor dynamic response that the green-down mode is hardly seen in the controller of the DCDC galvanically isolated converter.

Summary of the invention

The object of the present invention is to solve the above technical problems and provide a green power down mode to increase the working efficiency and reduce the no-load standby power consumption regardless of whether the ACDC switching power supply controller or the DCDC power supply controller. At the same time, the dynamic fast response method of the switching power supply can greatly improve the dynamic response speed.

Correspondingly, another object of the present invention is to provide a switching power supply controller for ACDC or a power controller for DCDC, which can adopt a green frequency reduction operation mode to increase work efficiency and reduce no-load standby power consumption. At the same time, the dynamic fast response circuit of the switching power supply can greatly improve the dynamic response speed.

In terms of method, the dynamic fast response method of the switching power supply of the present invention comprises the following steps: a fall fast response step, and a falling dynamic response signal is detected when a sudden increase in the voltage of the FB terminal is detected, and the current is quickly supplied to the FB terminal, and the FB end is accelerated. The rising rate of the voltage, and stopping the supply of current to the FB terminal after the voltage of the FB terminal rises to the first preset value, the first preset value of the voltage of the FB terminal corresponds to the FB terminal at the steady state when the switching power supply is fully loaded or reloaded The voltage value; the overshoot fast response step, when an abnormally rapid decrease in the voltage at the FB terminal is detected, an overshoot dynamic response signal is issued, the current at the FB terminal is quickly extracted, the voltage drop rate at the FB terminal is accelerated, and the voltage at the FB terminal is lowered to the second pre-stage. After the value is set, the current of the FB terminal is stopped, and the second preset value of the voltage of the FB terminal corresponds to the voltage value of the FB terminal under steady state of the switching power supply under light load or no load; State judgment step, judging whether the voltage loop of the switching power supply enters a steady state. If the voltage of the FB terminal has not experienced a large fluctuation up and down within the time specified by the counter, it is considered that the voltage of the FB terminal is basically stable, and the voltage loop has entered a stable state. The state allows the output of the falling dynamic response signal or the overshoot dynamic response signal; if the FB terminal voltage fluctuates greatly up and down within the time specified by the counter, and the voltage loop does not enter the steady state, the output dynamic response signal is not allowed to be output. Or overshoot the dynamic response signal.

Preferably, the falling fast response step comprises: shifting the FB terminal voltage by a small first positive voltage drop (ΔV1) to generate an FB terminal voltage plus a first positive voltage drop of the up-shifted voltage (VFB+ΔV1) And transmitting the up-shifted voltage (VFB+ΔV1) to the first voltage sampling module; periodically sampling the up-shifted voltage under the control of the clock, and temporarily storing the sampled voltage until the next one The sampling period is again sampled and refreshed, and the sampled saved voltage is transmitted to the first comparison latch module; the sampled saved voltage is compared with the FB terminal voltage, the comparison result is output to the steady state determination module, and the comparison result is latched by the latch. It is judged that if the voltage at the FB terminal is higher than the voltage stored in the sample and the voltage loop is in a steady state state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly drops; otherwise, a logic "No" signal is output. , indicating that the output voltage of the switching power supply does not suddenly drop; after receiving the logic "yes" signal, the output falling dynamic response signal, controlling the falling fast response module within the set time The line responds quickly and generates a reset signal to reset the latch after the set time of the drop fast response module ends. After receiving the drop dynamic response signal, the output current flows out from the FB terminal, so that the FB terminal voltage is quickly charged to the first pre-charge. Set the value so that the duty cycle increases rapidly; after the voltage at the FB terminal rises to the first preset value, the output current is stopped immediately, and the voltage loop is self-regulated.

Preferably, the overshoot fast response step comprises: shifting the FB terminal voltage VFB by a small second positive voltage drop (ΔV2) to generate a voltage after the FB terminal voltage is reduced by the second positive voltage drop (VFB- ΔV2), and transfer the down-shifted voltage (VFB-ΔV2) to the second voltage sampling module; periodically sample the down-shifted voltage under the control of the clock, and temporarily save the sampled voltage, wait until The next sampling period is again sampled and refreshed, and the sampled saved voltage is transferred to the second comparison latch module; the sampled saved voltage is compared with the FB terminal voltage, the comparison result is output to the steady state determination module, and the comparison result is latched. Latching down to judge, if the voltage at the FB terminal is lower than the voltage stored in the sample, and the voltage loop is in a steady state state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly increases; otherwise, the output logic "No ” signal, indicating that the output voltage of the switching power supply does not increase suddenly; after receiving the logic “yes” signal, the overshoot dynamic response signal is output, and the overshoot fast response module is controlled at the set time. Perform a fast response, and generate a reset signal to reset the latch after the set time of the overshoot fast response module ends; after receiving the overshoot dynamic response signal, quickly extract current from the FB terminal, causing the FB terminal voltage to rapidly drop to the first The second preset value causes the duty ratio to decrease rapidly; after the voltage at the FB terminal drops to the second preset value, the current is stopped immediately, and the voltage loop is self-adjusted.

In terms of circuit, the dynamic fast response circuit of the switching power supply of the invention comprises: a drop fast response module, which sends a falling dynamic response signal when detecting a sudden and rapid increase of the voltage at the FB terminal, and rapidly supplies a current to the FB terminal to accelerate the voltage of the FB terminal. The rising rate, and the supply of current to the FB terminal is stopped after the voltage of the FB terminal rises to the first preset value, and the first preset value of the voltage of the FB terminal corresponds to the voltage value of the FB terminal under the steady state of the switching power supply at full load or heavy load. The overshoot fast response module sends an overshoot dynamic response signal when detecting the sudden and rapid decrease of the FB terminal voltage, rapidly extracts the current of the FB terminal, accelerates the falling rate of the FB terminal voltage, and drops the voltage at the FB terminal to the second preset value. After stopping the current of the FB terminal, the second preset value of the voltage of the FB terminal corresponds to the voltage value of the FB terminal in the steady state of the switching power supply under light load or no load; the steady state determining module determines whether the voltage loop of the switching power supply enters Steady state, if the FB terminal voltage has not experienced a large up and down fluctuation in the time specified by the counter, it is considered that the voltage at the FB terminal is basically stable, and the voltage loop has entered a stable state. State, it is allowed to output the falling dynamic response signal or the overshoot dynamic response signal; if the voltage of the FB terminal appears to fluctuate greatly up and down within the time specified by the counter, and the voltage loop does not enter the steady state, the output dynamic response signal is not allowed to be output. Or overshoot the dynamic response signal.

Preferably, the drop fast response module comprises: a level up shifting module, wherein the FB terminal voltage is shifted up by a small first positive voltage drop (ΔV1) to generate an FB terminal voltage plus a first positive voltage drop. Voltage (VFB+ΔV1), and transmitting the up-shifted voltage (VFB+ΔV1) to the first voltage sampling module; the first voltage sampling module periodically samples the up-shifted voltage under the control of the clock, and The sampled voltage is temporarily saved, and is sampled and refreshed again in the next sampling period, and the sampled and saved voltage is transmitted to the first comparison latching module; the first comparison latching module compares the sampled and saved voltage with the FB terminal voltage. The comparison result is output to the steady state judgment module, and the comparison result is latched by the latch to determine whether the output logic is "yes" if the voltage at the FB terminal is higher than the voltage stored in the sample and the voltage loop is in a steady state state. The signal indicates that the output voltage of the switching power supply suddenly drops; otherwise, the logic "No" signal is output, indicating that the output voltage of the switching power supply does not suddenly drop; the first control pulse generator receives Series "yes" output of the signal constant width signal is active low, the dynamic response of the control module falls within a set fast response time, and quick response in the drop latch reset signal is generated after the set time of the module Reset; drop fast response module, after receiving the falling dynamic response signal, the output current flows out from the FB port, so that the voltage of the FB port is quickly charged to the first preset value, so that the duty ratio is rapidly increased; the voltage at the FB terminal rises to Immediately after the first preset value, the output current is stopped and the voltage loop is adjusted by itself.

Preferably, the drop fast response module further includes a control clock module for outputting a clock signal, and the level up shifting module includes a first current source, a first P-channel MOS transistor, and a second P-channel MOS. a first resistor, a source of the first P-channel MOS transistor is connected to a source of the second P-channel MOS transistor, a drain of the first P-channel MOS transistor, and a first P-channel MOS The gate of the tube and the gate of the second P-channel MOS transistor are grounded via a first current source, and the drain of the second P-channel MOS transistor is connected to the FB terminal via a resistor; the first voltage sampling module includes the first single a steady state flip-flop, a first transfer gate, a first non-gate, a first capacitor, an input end of the first monostable flip-flop control clock module, an output of the first monostable flip-flop and a first transmission The reverse control end of the door is connected, and the output end of the first monostable trigger is also connected to the forward control end of the first transmission gate via the first non-gate, the input end of the first transmission gate and the first level of the module a drain of the two P-channel MOS transistors, the output end of the first transmission gate is grounded via a first capacitor; the first comparison latch module includes a first a comparator, a first NAND gate, a first RS flip-flop, a positive terminal of the first comparator is connected to the FB terminal, and a negative terminal of the first comparator is connected to an output end of the first transmission gate of the first voltage sampling module, The output end of the first comparator is connected to the S end of the first RS flip-flop via a first NAND gate; the first control pulse generator includes a first counter, a second NAND gate, and a third NAND gate. The CP of the first counter is connected to the control clock module, and the Clr of the first counter is connected to the output of the first RS flip-flop of the first comparison latch module, the first counter

The output end of the first RS flip-flop is outputted via the second NAND gate, the output end of the second NAND gate, the output end of the first RS flip-flop and the control clock module are also connected to the first RS via the third NAND gate. a R-terminal of the flip-flop; the drop fast response module includes a second NOT gate, a third P-channel MOS transistor, a fourth P-channel MOS transistor, and a third N-channel MOS transistor, the third P-channel The gate of the MOS transistor is connected to the output end of the second NAND gate, and the output of the second NAND gate is also connected to the gate of the third N-channel MOS transistor via the second non-gate, the third P-channel MOS transistor The source is connected to the power source, the drain of the third P-channel MOS transistor is respectively connected to the source of the FB terminal and the fourth P-channel MOS transistor, and the gate of the fourth P-channel MOS transistor is connected to the voltage signal, the fourth P The drain of the channel MOS transistor is connected to the drain of the third N-channel MOS transistor, and the source of the third N-channel MOS transistor is grounded.

Preferably, the overshoot fast response module comprises: a level down shifting module, wherein the FB terminal voltage is shifted down by a small second positive voltage drop (ΔV2) to generate a FB terminal voltage minus a second positive voltage drop. Voltage (VFB-ΔV2), and transfer this down-shifted voltage (VFB-ΔV2) to the second voltage sampling module; second The voltage sampling module periodically samples the down-shifted voltage under the control of the clock, and temporarily saves the sampled voltage, waits until the next sampling period to resample and refresh, and the sampled saved voltage is transmitted to the second comparison latch. The second comparison latch module compares the sampled voltage with the FB terminal voltage, and the comparison result is output to the steady state determination module, and the comparison result is latched by the latch to determine if the voltage of the FB port is sampled. When the stored voltage is low and the voltage loop is in a steady state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly increases; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply does not suddenly increase. The second control pulse generator outputs an overshoot dynamic response signal after receiving the logic "yes" signal, and the control overshoot fast response module performs a fast response within the set time, and ends at the set time of the overshoot fast response module. After the reset signal is generated, the latch is reset; the overshoot fast response module receives the overshoot dynamic response signal. After the number, the current is quickly drawn from the FB terminal, so that the voltage at the FB terminal rapidly drops to the second preset value, so that the duty ratio is rapidly reduced; after the voltage at the FB terminal rapidly drops to the second preset value, the current is immediately stopped. Let the voltage loop adjust itself.

Preferably, the overshoot fast response module further includes a control clock module for outputting a clock signal, the level down module comprising a second current source, a first N-channel MOS transistor, and a second N-channel a MOS transistor and a second resistor, wherein the second current source is respectively connected to a drain of the first N-channel MOS transistor, a gate of the first N-channel MOS transistor, and a gate of the second N-channel MOS transistor. a source of an N-channel MOS transistor is commonly connected to a source of the second N-channel MOS transistor, and a drain of the second N-channel MOS transistor is connected to the FB terminal via a second resistor; the second voltage sampling module, The second monostable trigger, the second pass gate, the third NOT gate, and the second capacitor are included, and the input end of the second monostable flip-flop is connected to the control clock module, and the output end of the second monostable flip-flop Connected to the reverse control end of the second transmission gate, the output end of the second monostable flip-flop is further connected to the forward control end of the second transmission gate via the third non-gate, and the input end of the second transmission gate and the second N a drain of the channel MOS transistor is connected, and an output end of the second transmission gate is grounded via a second capacitor; the second comparison latch module includes a second comparator, a fourth NAND gate, a second RS flip-flop, a positive terminal of the second comparator is connected to an output end of the second transmission gate, a negative terminal of the second comparator is connected to the FB terminal, and an output terminal of the second comparator is fourth. The NAND gate is connected to the S terminal of the second RS flip-flop; the second control pulse generator includes a second counter, a fifth NAND gate, and a sixth NAND gate, and the CP terminal of the second counter is connected to the control clock. a module, a Clr end of the second counter is connected to an output of the second RS flip-flop, and the second counter is

The output of the terminal and the second RS flip-flop is output through the fifth NAND gate, the output of the fifth NAND gate, the output of the second RS flip-flop and the clock signal are also triggered by the sixth NAND gate and the second RS. The R-terminal of the overshoot; the overshoot fast response module includes a fourth NOT gate and a fourth N-channel MOS transistor, and the output of the fifth NAND gate of the second control pulse generator passes through the fourth NOT gate The gate of the fourth N-channel MOS transistor is connected, the FB terminal is connected to the drain of the fourth N-channel MOS transistor via a diode, and the source of the fourth N-channel MOS transistor is grounded.

Preferably, the drop fast response module or the overshoot fast response module, the steady state determining module includes a third counter, a third RS flip flop, or a NOT gate, and the CP terminal of the third counter is connected to the control clock module. Third counter

The terminal is connected to the S terminal of the third RS flip-flop, and the output of the first comparator of the first comparison latch module and the output of the second comparator of the second comparison latch module are respectively connected to the NOR gate The Clr end of the third counter is connected to the R end of the third RS flip-flop, and the Q end of the third RS flip-flop and the output end of the first comparator are connected to the S end of the first RS flip-flop via the first NAND gate, The Q terminal of the triple RS flip-flop is also coupled to the S terminal of the second comparator of the second comparison latch module via the second NAND gate.

The invention has the following beneficial effects:

(1) By detecting the sudden increase of the voltage at the FB terminal, it is possible to judge the occurrence of the sudden drop of the output voltage of the switching power supply, and immediately suppress the tendency of the output voltage to fall after rapidly increasing the duty ratio, thereby greatly reducing the amplitude of the drop. Since the FB terminal voltage VFB rises to the heavy load region, the loop self-regulates the output voltage without causing an additional output overshoot voltage.

(2) By detecting the sudden drop of the voltage at the FB terminal, it is possible to judge the occurrence of a sudden increase in the output voltage of the switching power supply, and immediately reduce the duty cycle and immediately suppress the rising trend of the output voltage, thereby greatly reducing the magnitude of the overshoot. Since the FB terminal voltage VFB drops to the light load region, the loop self-regulates the output voltage, and the duty cycle is not limited too long.

(3) Regardless of whether it is ACDC's switching power supply controller or DCDC power supply controller, the stability of the circuit loop operation can be guaranteed in the light load frequency reduction mode, and the dynamic response is fast, so the green drop can be completely adopted. Frequency mode of operation to increase work efficiency and reduce no-load standby power consumption, while greatly improving the dynamic response speed.

DRAWINGS

1 is an application circuit diagram of a flyback switching power supply of a secondary side feedback control of the prior art;

2 is a circuit block diagram of a dynamic fast response circuit of a switching power supply of the present invention;

3 is a circuit schematic diagram of a dynamic fast response circuit of a switching power supply according to the present invention;

4 is a circuit schematic diagram of a one-shot of a dynamic fast response circuit of a switching power supply of the present invention.

detailed description

In the following detailed description, certain exemplary embodiments of the invention have As will be appreciated by those skilled in the art, the embodiments described herein may be modified in various different ways without departing from the spirit or scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative illustrative

Please refer to FIG. 2 , which is a dynamic fast response circuit of a switching power supply provided by the present invention, which has the functions of falling fast response and overshoot fast response, and therefore includes two-way detection and corresponding response module circuits. The first drop falling fast response circuit comprises: a level up shifting module 11, a voltage sampling module 12, a comparison latching module 13, a control pulse generator 14, a drop fast response module 15, an input port and a control of the level up shifting module 11. The FB terminal of the device is connected; the output signal of the level up module 11 is transmitted to the voltage sampling module 12; the output signal of the voltage sampling module 12 is sent to the comparison latch module 13; the output signals of the comparison latch module 13 are respectively sent to the control pulse The generator 14 and the steady state determination module 50 receive their feedback signals at the same time; the drop fast response module 15 performs a drop fast response under the control signal from the control pulse generator 14, which rapidly increases the voltage of the FB terminal connected thereto. to realise.

The second overshoot fast response circuit includes a level down module 21, a voltage sampling module 22, a comparison latch module 23, a control pulse generator 24, and an overshoot fast response module 25. At the same time, a steady state judgment module 50 for improving the anti-interference ability is also included. On the second overshoot dynamic response branch, the input port of the level down module 21 is connected to the FB terminal of the controller; the output signal of the level down module 21 is transmitted to the voltage sampling module 22; the output signal of the voltage sampling module 22 Transmitted to the comparison latch module 23; the output signals of the comparison latch module 23 are respectively transmitted to the control pulse generator 24 and the steady state determination module 50, while receiving their feedback signals; the overshoot fast response module 25 is controlling the pulse generator The overshoot response is responded to by the control signal sent by 24, which is achieved by rapidly reducing the voltage at the FB terminal connected to it.

The working principle of the present invention is: on the first falling fast response branch, the level up module 11 shifts the FB terminal voltage VFB by a small positive voltage drop ΔV1 to generate an upward shift of the FB terminal voltage VFB plus the positive voltage drop ΔV1. The subsequent voltage (VFB + ΔV1), and this up-shifted voltage (VFB + ΔV1) is transmitted to the voltage sampling module 12. The voltage sampling module 12 periodically samples the up-shifted voltage under the control of the clock, and temporarily saves the sampled voltage, waits until the next sampling period, samples and refreshes again, and saves the sample. The voltage is transferred to the comparison latch module 13. The comparison latch module 13 compares the sampled stored voltage with the FB terminal voltage, the comparison result is output to the steady state determination module 50, and the comparison result is latched by the latch if the FB terminal voltage is higher than the sample held voltage, and When the voltage loop is in a steady state, that is, a logic "yes" (high or low) signal is output, indicating that the output voltage of the switching power supply suddenly drops; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply is not suddenly fall. The control pulse generator 14 outputs a falling dynamic response signal after receiving the logic "yes" signal, and the control fall fast response module 15 performs a fast response within the set time, and generates a reset after the set time of the fall fast response module 15 ends. The signal resets the latch. After receiving the falling dynamic response signal, the falling fast response module 15 outputs an output current flowing from the FB terminal, so that the FB terminal voltage VFB is quickly charged to the FB terminal voltage value corresponding to the full load or the heavy load state, thereby rapidly increasing the duty ratio. After the FB terminal voltage VFB rises rapidly to the preset value, the output current is stopped immediately, and the voltage loop is adjusted by itself.

It is easy to see from the above-mentioned fast response operation principle of the output voltage drop. The voltage sampling module 12 actually stores the up-shift voltage (VFB+ΔV1) of the FB terminal voltage VFB just before, if the current FB terminal voltage VFB' The voltage is larger than the up-shift voltage (VFB+ΔV1) of the FB terminal voltage VFB just saved, indicating that the current FB terminal voltage is rising rapidly, and the side surface reflects that the output voltage of the switching power supply suddenly drops. Therefore, by detecting the sudden increase of the voltage at the FB terminal, it is possible to judge the occurrence of the sudden drop of the output voltage of the switching power supply, and immediately suppress the tendency of the output voltage to fall after rapidly increasing the duty ratio, thereby greatly reducing the amplitude of the drop. Since the FB terminal voltage VFB rises to the heavy load region, the loop self-regulates the output voltage without causing an additional output overshoot voltage.

On the second overshoot fast response branch, the level down module 21 shifts the FB terminal voltage VFB by a small positive voltage drop ΔV2 to generate a voltage of the FB terminal voltage VFB minus the voltage drop of the positive voltage drop ΔV2 (VFB- ΔV2), and this down-shifted voltage (VFB-ΔV2) is transmitted to the voltage sampling module 22. The voltage sampling module 22 periodically samples the down-shifted voltage under the control of the clock, and temporarily saves the sampled voltage, waits until the next sampling period, and then samples and refreshes, and the sampled and saved voltage is transmitted to the comparison latch module. twenty three. The comparison latch module 23 compares the voltage stored in the sample with the voltage of the FB port, and the comparison result is output to the steady state determination module 50, and the comparison result is latched by the latch to determine if the voltage at the FB terminal is higher than the voltage stored in the sample. Low, and the voltage loop is in a steady state state, that is, the output logic "yes" (high or low level) signal indicates that the output voltage of the switching power supply suddenly increases; otherwise, the output logic "no" signal indicates the output of the switching power supply. There is no sudden increase in voltage. Control pulse generator 24 receives the logic "yes" signal and outputs an overshoot dynamic response signal, and the control overshoot fast response module 25 performs a fast response within the set time, and generates a reset signal after the set time of the overshoot fast response module 25 ends. The RS trigger is reset. After receiving the overshoot dynamic response signal, the overshoot fast response module quickly extracts the current from the FB terminal, causing the FB terminal voltage to rapidly drop to the VFB voltage value corresponding to the light load or no-load state, thereby rapidly reducing the duty cycle. After the voltage VFB of the FB terminal drops rapidly to the preset value, the pumping is stopped immediately, and the voltage loop is adjusted by itself.

It is easy to see from the above-mentioned fast working principle of the output voltage overshoot that the voltage sampling module 2 is actually the voltage of the downward shift (VFB-ΔV2) of the FB terminal voltage VFB just collected, if the voltage of the current FB terminal voltage VFB' It is smaller than the downward shift voltage (VFB-ΔV2) of the FB terminal voltage VFB just collected, indicating that the current FB terminal voltage is rapidly declining, and the side surface reflects the sudden increase of the output voltage of the switching power supply. Therefore, by detecting the sudden drop of the voltage at the FB terminal, it is possible to judge the occurrence of a sudden increase in the output voltage of the switching power supply, and immediately reduce the duty cycle and immediately suppress the increase in the output voltage, thereby greatly reducing the magnitude of the overshoot. Since the FB terminal voltage VFB drops to the light load region, the loop self-regulates the output voltage, and the duty cycle is not limited too long.

At the same time, the present invention is further provided with a steady state judging module, which works on the principle that: within the duration period n microseconds (time is set as needed), the internal stability judging module 50 does not receive the comparison latch module 13 and compares When the valid signal is sent by the latch module 23, the steady state determining module 50 outputs an active high level, indicating that the FB terminal voltage VFB has entered a steady state. Only when the FB terminal voltage VFB is judged to enter the steady state, the output voltage drop dynamic response signal or the voltage overshoot dynamic response signal is allowed to be achieved, and the anti-interference performance can be improved. For example, during the startup of the switching power supply, although VFB is changing rapidly, since it has not been able to reach a steady state, no dynamic response action occurs. For example, after the action of output voltage drop rapid response, VFB may be charged too high, and the voltage of VFB is reduced by the adjustment of the feedback voltage loop. If there is no steady state judgment module, then VFB A sudden decrease may be mistaken for a sudden increase in the output voltage of the switching power supply, resulting in a false response to an output voltage overshoot. Therefore, whether it is ACDC switching power supply controller or DCDC power supply controller, in the light load frequency reduction mode, the stability of the circuit loop operation can be guaranteed, and the dynamic response is fast, so the green frequency reduction operation can be completely adopted. Modes increase work efficiency and reduce no-load standby power consumption while maximizing dynamic response speed.

Moreover, in order to provide a more intuitive understanding of the present invention, in the following description of the embodiments The design of some specific parameters, such as "ΔV1=100mV", the output active low level, and the OR gate are used to achieve the corresponding logical relationship, which are only for enhancing the perceptual knowledge and are not limited by the present invention. Because, as we all know, the design of specific parameters depends on the actual application, and the circuit of logic relationship is also diverse.

As shown in FIG. 3, it is a circuit block diagram of an embodiment of the present invention, which includes: a level up module 11, a voltage sampling module 12, a comparison latch module 13, a control pulse generator 14, a drop fast response module 15, and a level. The down shift module 21, the voltage sampling module 22, the comparison latch module 23, the control pulse generator 24, the overshoot fast response module 25, the control clock module 30, and the steady state determination module 50.

The level up module 11 includes a current source Iref1, a P channel MOS transistor MP1, a P channel MOS transistor MP2, a resistor R1, a source of the MOS transistor MP1 and a source of the MOS transistor MP2, and a MOS transistor. The drain of the MP1, the gate of the MOS transistor MP1, and the gate of the MOS transistor MP2 are grounded via the current source Iref1, and the drain of the MOS transistor MP2 is connected to the FB terminal via the resistor R1.

The function of the level up module 11 is to shift the voltage of the FB terminal by a small voltage drop ΔV1 to generate a new voltage V1=VFB+ΔV1, that is, the current I 1 generated by a P-type current mirror Iref1 flows through the resistor. R1, the voltage drop of the resistor R1 is ΔV1=I1*R1, so that the up-shifting module outputs the up-shift voltage V1=VFB+I1*R1.

The level down module 21 includes a current source Iref2, an N-channel MOS transistor MN1, an N-channel MOS transistor MN2, a resistor R2, a current source Iref2 and a drain of the MOS transistor MN1, a gate of the MOS transistor MN1, and a MOS transistor. The gate of MN2 is connected, the source of MOS transistor MN1 is connected to the source of MOS transistor MN2, and the drain of MOS transistor MN2 is connected to FB terminal via resistor R2.

The function of the level down module 21 is to lower the voltage of the FB terminal by a small voltage drop ΔV2 to generate a new voltage V2=VFB-ΔV2, and the current I2 generated by an N-type current mirror Iref2 flows through the resistor R2. The voltage drop of the resistor R2 is ΔV2=I2*R2, so that the down-shifting module outputs the downward voltage V2=VFB-I2*R2.

The voltage sampling module 12 includes a monostable flip-flop D1, a transfer gate G1, a NOT gate N1, a capacitor Cs1, an input terminal of the monostable flip-flop D1 is connected to the control clock module 30, and an output terminal and transmission of the monostable flip-flop D1 The reverse control end of the gate G1 is connected, and the output end of the monostable flip-flop D1 is also connected to the forward control end of the transmission gate G1 via the NOT gate N1, and the input end of the transmission gate G1 and the MOS transistor MP2 of the level up-shift module 11 The drain connection is connected, and the output terminal of the transmission gate G1 is grounded via the capacitor Cs1.

The voltage sampling module 22 includes a monostable flip-flop D2, a transfer gate G2, a non-gate N3, a capacitor Cs2, an input terminal of the monostable flip-flop D2 is connected to the control clock module 30, and an output terminal and transmission of the monostable flip-flop D2 The reverse control terminal of the gate G2 is connected. The output terminal of the monostable flip-flop D2 is also connected to the forward control terminal of the transmission gate G2 via the NOT gate N3, and the input terminal of the transmission gate G2 and the MOS transistor MN2 of the level down-shift module 21. The drain connection is connected, and the output terminal of the transmission gate G2 is grounded via the capacitor Cs2.

The functions of the voltage sampling module 12 and the voltage sampling module 22 are both sampling and preserving the shifted voltages, which respectively store and store the up-shift voltage V1 and the down-shift voltage V2. At the falling edge of the clock signal CLK of the control clock module 30, the one-shot (the internal circuit of the one-shot is shown in FIG. 4) outputs a low-level pulse signal Pulse, and the gate is transmitted under the control of the narrow pulse. G1 and G2 are in an on state, and the voltages on the sampling capacitors C _S1 and C _S2 are charged and discharged to the up-shift voltage V1 or the down-shift voltage V2. After the low-level pulse signal Pulse returns to the high level, the transfer gates G1 and G2 are turned off, and the sampling and holding phase is entered. During this phase, the sampling capacitors C _S1 and C _S2 hold the sampled voltage until the next cycle is resampled and refreshed. . It is easy to see that the voltage on the sampling capacitor during the sample-and-hold phase is actually the voltage of the previous sampling period. Compared with the voltage in the comparison latch module, it is equivalent to the current FB terminal voltage VFB and the FB terminal voltage VFB of the previous sampling period. Comparison.

The comparison latch module 13 includes a comparator C1, a NAND gate A1, and an RS flip-flop RS1. The positive terminal of the comparator C1 (the "+" terminal in the figure) is connected to the FB terminal, and the negative terminal of the comparator C1 (marked in the figure "- The "end" is connected to the output end of the transmission gate G1 of the voltage sampling module 12, and the output end of the comparator C1 is connected to the S terminal of the RS flip-flop RS1 via the NAND gate A1.

The comparison latch module 23 includes a comparator C2, a NAND gate A4, and an RS flip-flop RS2. The positive terminal of the comparator C2 (the "+" terminal in the figure) is connected to the output terminal of the transmission gate G2 of the voltage sampling module 22, and the comparator. The negative terminal of C2 (the "-" terminal in the figure) is connected to the FB terminal, and the output terminal of the comparator C2 is connected to the S terminal of the RS flip-flop RS2 via the NAND gate A4.

The functions of the comparison latch module 13 and the comparison latch module 23 are to compare the current VFB voltage with the shifted voltage stored in the voltage sampling module, and latch the comparison result with the RS flip-flop, and compare the results. (Set1 or Set2) is transmitted to the control pulse generator 14 and the control pulse generator 24, respectively. Since the operation process of the comparison latch module 13 and the comparison latch module 23 is substantially the same, the comparison latch module 13 is taken as an example to illustrate that the working process is: if the current FB terminal voltage VFB voltage is higher than the sample storage voltage V _S1 , then The comparator C1 outputs a high level. If the RS flip-flop RS3 in the steady state determining module 50 outputs Stable=“1” (indicating a steady state), the NAND gate A1 outputs a low level, and the latch module 13 is compared. The RS flip-flop RS1 is set to "1", that is, Set1 = "1", and the control pulse generator 14 is notified to generate a fast response control pulse signal; if the current VFB is not larger than V _S1 , Set1 remains in the "0" state.

The control pulse generator 14 includes a counter J1, a NAND gate A2, and a NAND gate A3. The CP terminal of the counter J1 is connected to the control clock module 30, and the Clr terminal of the counter J1 is connected to the output terminal of the RS flip-flop RS1 of the latch module 13. , counter J1

The output end of the RS and RS flip-flop RS1 is output through the NAND gate A2, the output end of the NAND gate A2, the output end of the RS flip-flop RS1 and the control clock module 30 are also connected to the R terminal of the RS flip-flop RS1 via the NAND gate A3. ;

The control pulse generator 24 includes a counter J2, a NAND gate A5, and a NAND gate A6. The CP of the counter J2 is connected to the control clock module 30, and the Clr of the counter J2 is connected to the output of the RS flip-flop RS2 of the comparison latch module 23. , counter J2

The output end of the RS and RS flip-flop RS2 is output through the NAND gate A5, the output end of the NAND gate A5, the output end of the RS flip-flop RS2 and the control clock module 30 are also connected to the R terminal of the RS flip-flop RS2 via the NAND gate A6. ;

The function of the

control pulse generators

14, 24 is to generate a dynamic response signal when receiving the comparison result of the

comparison latch modules

13, 23, that is, the control pulse generator 14 generates an active-low drop dynamic response signal of a certain width. The control pulse generator 24 generates an active-low overshoot dynamic response signal of a certain width to respectively control the dynamic response modules 15, 25 to respond quickly within a prescribed time, and generate a reset signal after the response is completed to make the comparison latch module The RS flip-flops in 13, 23 are reset. Since the operation processes of the

control pulse generators

14, 24 are basically the same, the control pulse generator 14 is taken as an example to illustrate its working process: in the initial state, Set1 = "0" and Pulse1 = "1".

Rset1=“1”. When the control pulse generator 14 receives the valid control signal Set1 = "1", the control signal Pusle1 immediately becomes the active level "0", since the counter J1 in the control pulse generator 14 is asynchronously cleared to the end Clr = "1" The counter J1 starts counting. After the counter J1 counts, the counter J1 outputs

Pulse1 is restored to the inactive level "1". When the rising edge of the clock signal of the control clock module 30 arrives, CLK=“1”, the output reset signal Rset1=“0”, the RS flip-flop RS1 in the comparison latch module 13 is reset, Set1=“0”, the counter J1 also Was cleared,

Rset1 is restored to the inactive level "1". Therefore, after the effective control signal is output, it returns to the initial state.

The steady state determining module 50 includes a counter J3, an RS flip-flop RS3, a NOR gate U1, and a CP end of the counter J3 is connected to the control clock module 30, and the counter J3

The terminal is connected to the S terminal of the RS flip-flop RS3, and the output terminal of the comparator C1 of the comparison latch module 13 and the output terminal of the comparator C2 of the comparison latch module 23 are respectively connected to the Clr terminal of the counter J3 and the RS via the NOR gate U1. The R terminal of the flip-flop RS3, the Q terminal of the RS flip-flop RS3 and the output terminal of the comparator C1 of the comparison latch module 13 are connected to the S terminal of the RS flip-flop RS1 via the NAND gate A1, and the Q terminal of the RS flip-flop RS3 is also The output of the comparator C2 of the comparison latch module 23 is connected to the S terminal of the RS flip-flop RS2 via the NAND gate A4.

The function of the steady state judging module 50 is to determine whether the voltage loop of the switching power supply enters a steady state. The principle is that the FB terminal voltage has not experienced a large up and down fluctuation in the time specified by the counter, and the FB terminal voltage VFB is considered to be substantially stable. The voltage loop has entered a steady state. As long as the voltage at the FB terminal fluctuates greatly, the comparator in the comparison latch module 13 or the comparison latch module 23 outputs a high level. After the NOR gate is coupled, the counter is asynchronously cleared, and the RS is also cleared. Therefore, only the FB terminal voltage does not show large fluctuations within the specified time (determined by the timer), and there is no clear signal generation. After the counter counts, the RS flip-flop is set to "1", that is, Stable = "1", indicating that the judgment is made. The result is a steady state.

The falling fast response module 15 includes a NOT gate N2, a P-channel MOS transistor MP3, a P-channel MOS transistor MP4, an N-channel MOS transistor MN3, a gate of the MOS transistor MP3 and a NAND gate A2 of the control pulse generator 14. The output terminal is connected, the output terminal of the NAND gate A2 is also connected to the gate of the MOS transistor MN3 via the non-gate N2, the source of the MOS transistor MP3 is connected to the power supply, and the drain of the MOS transistor MP3 is respectively connected to the source of the FB terminal and the MOS transistor MP4. The pole is connected, the gate of the MOS transistor MP4 is connected to the voltage signal Vref, the drain of the MOS transistor MP4 is connected to the drain of the MOS transistor MN3, and the source of the MOS transistor MN3 is grounded.

The falling fast response module 15 is configured to rapidly provide a current acceleration FB terminal voltage VFB when the voltage of the FB terminal is suddenly increased rapidly, and the FB terminal voltage VFB does not rise after rising to a preset value, the preset The value corresponds to the FB terminal voltage VFB at steady state when the switching power supply is fully loaded or reloaded. The working principle is that, under the action of the dynamic response signal Pulse1=“0”, the P-channel MOS transistor MP3 and the N-channel MOS transistor MN3 are turned on, because the voltage of the VFB has not reached the clamp voltage (V _ref + V _SG4 ) (where V _SG4 is the source gate voltage of MP4), the MOS transistor MP4 does not pass current, and the large current flowing after the MOS transistor MP3 is turned on directly charges the FB terminal, so that the voltage VFB of the FB terminal is rapidly increased. However, when the FB terminal voltage VFB exceeds (V _ref +V _SG4 ), the current will be discharged by the MOS transistor MP4 which acts as a clamp, so that the FB terminal voltage VFB is clamped near (V _ref +V _SG4 ), and cannot Then rise higher.

The overshoot fast response module 25 includes a NOT gate N4 and an N-channel MOS transistor MN4. The output terminal of the NAND gate A5 of the control pulse generator 24 is connected to the gate of the MOS transistor MN4 via the NOT gate N4, and the FB terminal passes through the diode D1. Connected to the drain of the MOS transistor MN4, the source of the MOS transistor MN4 is grounded;

The overshoot fast response module 25 is configured to quickly extract the current to accelerate the falling rate of the FB terminal voltage VFB when the FB terminal voltage suddenly decreases rapidly, and the FB terminal voltage VFB does not fall after falling to a preset value. The set value corresponds to the FB terminal voltage VFB at steady state when the switching power supply is lightly loaded or at no load. The working principle is that under the action of the dynamic response signal Pulse2=“0”, the MOS transistor MN4 is turned on, and a large current is extracted from the FB terminal, so that the FB terminal voltage VFB drops rapidly. However, due to the presence of the forward voltage drop VD1 of the diode D1, the minimum voltage of the FB terminal voltage VFB is greater than VD1. If you want VFB to have a higher minimum voltage, you can connect a diode in the same direction as diode D1.

Variations and modifications of the above-described embodiments may also be made by those skilled in the art in light of the above disclosure. Therefore, the invention is not limited to the specific embodiments disclosed and described herein, and the modifications and variations of the invention are intended to fall within the scope of the appended claims. In addition, although specific terms are used in the specification, these terms are merely for convenience of description and do not limit the invention.

Claims

A dynamic fast response method of a switching power supply, comprising the following steps,

The falling fast response step sends a falling dynamic response signal when a sudden increase in the voltage at the FB terminal is detected, rapidly supplying current to the FB terminal, accelerating the rising rate of the FB terminal voltage, and stopping after the voltage at the FB terminal rises to the first preset value. Providing a current to the FB terminal, and the first preset value of the voltage of the FB terminal corresponds to a voltage value of the FB terminal at a steady state when the switching power supply is fully loaded or reloaded;

The overshoot fast response step sends an overshoot dynamic response signal when detecting the sudden and rapid decrease of the voltage at the FB terminal, rapidly extracts the current of the FB terminal, accelerates the falling rate of the voltage at the FB terminal, and after the voltage at the FB terminal drops to the second preset value Stopping the current of the FB terminal, and the second preset value of the FB terminal voltage corresponds to the FB terminal voltage value under steady state when the switching power supply is lightly loaded or idling;

The steady state determining step determines whether the voltage loop of the switching power supply enters a steady state,

If the voltage of the FB terminal has not experienced a large up and down fluctuation in the time specified by the counter, it is considered that the voltage at the FB terminal is basically stable, and the voltage loop has entered a steady state, then the output dynamic response signal or the overshoot dynamic response signal is allowed to be output;

If the FB terminal voltage fluctuates greatly up and down within the time specified by the counter, and the voltage loop does not enter the steady state, the falling dynamic response signal or the overshoot dynamic response signal is not allowed to be output.
The dynamic fast response method of the switching power supply according to claim 1, wherein the step of falling quickly responds comprises:

The FB terminal voltage is shifted up by a small first positive voltage drop (ΔV1) to generate the FB terminal voltage plus the first positive voltage drop of the up-shifted voltage (VFB+ΔV1), and the up-shifted voltage (VFB+) ΔV1) is transmitted to the first voltage sampling module;

Periodically sampling the up-shifted voltage under the control of the clock, and temporarily storing the sampled voltage, waiting for the next sampling period to be sampled and refreshed again, and the sampled saved voltage is transmitted to the first comparison latch module;

The voltage stored in the sample is compared with the voltage at the FB terminal, and the comparison result is output to the steady state determination module, and the comparison result is latched by the latch to determine if the voltage at the FB terminal is higher than the voltage stored in the sample, and the voltage loop is at In the steady state state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly drops; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply does not suddenly drop;

After receiving the logic "yes" signal, the falling dynamic response signal is output, and the control falling fast response module performs a fast response within the set time, and generates a reset signal to reset the latch after the set time of the falling fast response module ends;

After receiving the falling dynamic response signal, the output current flows out from the FB terminal, so that the voltage at the FB terminal is quickly charged to the first preset value, thereby rapidly increasing the duty ratio; immediately after the voltage at the FB terminal rises to the first preset value, Stop the output current and let the voltage loop adjust itself.
The dynamic fast response method of a switching power supply according to claim 1, wherein the overshooting fast response step comprises:

The FB terminal voltage VFB is shifted down by a small second positive voltage drop (ΔV2) to generate a voltage (VFB-ΔV2) after the FB terminal voltage is reduced by the second positive voltage drop, and the voltage after the downward shift (VFB) -ΔV2) is transmitted to the second voltage sampling module;

Periodically sampling the down-shifted voltage under the control of the clock, and temporarily storing the sampled voltage, waiting for the next sampling period to be sampled and refreshed again, and the sampled saved voltage is transmitted to the second comparison latch module;

The voltage stored in the sample is compared with the voltage at the FB terminal, and the comparison result is output to the steady state determination module, and the comparison result is latched by the latch to determine if the voltage at the FB terminal is lower than the voltage stored in the sample, and the voltage loop is at In the steady state state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly increases; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply does not suddenly increase;

After receiving the logic "yes" signal, the overshoot dynamic response signal is output, the control overshoot fast response module performs a fast response within the set time, and a reset signal is generated after the set time of the overshoot fast response module ends to cause the latch Reset

After receiving the overshoot dynamic response signal, the current is quickly extracted from the FB terminal, so that the FB terminal voltage rapidly drops to the second preset value, thereby rapidly reducing the duty ratio; after the FB terminal voltage drops to the second preset value , immediately stop pumping current, let the voltage loop adjust itself.
A dynamic fast response circuit for a switching power supply, characterized in that:

The falling fast response module sends a falling dynamic response signal when detecting a sudden and rapid increase of the FB terminal voltage, rapidly supplying current to the FB terminal, accelerating the rising rate of the FB terminal voltage, and at the FB terminal voltage After the first preset value is raised, the supply of current to the FB terminal is stopped, and the first preset value of the voltage of the FB terminal corresponds to the voltage value of the FB terminal under steady state when the switching power supply is fully loaded or reloaded;

The overshoot fast response module sends an overshoot dynamic response signal when detecting that the voltage at the FB terminal suddenly decreases rapidly, rapidly extracts the current of the FB terminal, accelerates the falling rate of the voltage at the FB terminal, and after the voltage at the FB terminal drops to the second preset value Stopping the current of the FB terminal, and the second preset value of the FB terminal voltage corresponds to the FB terminal voltage value under steady state when the switching power supply is lightly loaded or idling;

The steady state judgment module determines whether the voltage loop of the switching power supply enters a steady state,

If the voltage of the FB terminal has not experienced a large up and down fluctuation in the time specified by the counter, it is considered that the voltage at the FB terminal is basically stable, and the voltage loop has entered a steady state, then the output dynamic response signal or the overshoot dynamic response signal is allowed to be output;

If the FB terminal voltage fluctuates greatly up and down within the time specified by the counter, and the voltage loop does not enter the steady state, the falling dynamic response signal or the overshoot dynamic response signal is not allowed to be output.
The dynamic fast response circuit of the switching power supply of claim 4, wherein the drop fast response module comprises:

Level up the module, shifting the FB terminal voltage up by a small first positive voltage drop (ΔV1) to generate the FB terminal voltage plus the first positive voltage drop of the up-shifted voltage (VFB+ΔV1), and shifting this up The subsequent voltage (VFB+ΔV1) is transmitted to the first voltage sampling module;

The first voltage sampling module periodically samples the up-shifted voltage under the control of the clock, and temporarily saves the sampled voltage, waits until the next sampling period, and then samples and refreshes, and the sampled and saved voltage is transmitted to the first comparison. Latch module

The first comparison latching module compares the sampled saved voltage with the FB terminal voltage, and the comparison result is output to the steady state determining module, and the comparison result is latched by the latch to determine, if the FB terminal voltage is higher than the sampled saved voltage High, and the voltage loop is in a steady state state, then output a logic "yes" signal, indicating that the output voltage of the switching power supply suddenly drops; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply does not suddenly drop;

The first control pulse generator receives a logic "yes" signal and outputs a low-level effective signal of a certain width, and controls the falling dynamic response module to respond quickly within a set time, and ends at a set time of the drop fast response module. A reset signal is generated to reset the latch;

Drop the fast response module, after receiving the falling dynamic response signal, the output current flows out from the FB port, so that the voltage of the FB port is quickly charged to the first preset value, so that the duty ratio is rapidly increased; the voltage at the FB terminal rises to the first Immediately after the preset value, the output current is stopped and the voltage loop is adjusted by itself.
A dynamic fast response circuit for a switching power supply according to claim 5, further comprising: a control clock module for outputting a clock signal,

The level up-shifting module includes a first current source, a first P-channel MOS transistor, a second P-channel MOS transistor, a first resistor, a source of the first P-channel MOS transistor, and a second P a source common power connection of the channel MOS transistor, a drain of the first P-channel MOS transistor, a gate of the first P-channel MOS transistor, and a gate of the second P-channel MOS transistor are grounded via the first current source, The drain of the second P-channel MOS transistor is connected to the FB terminal via a resistor;

The first voltage sampling module includes a first monostable trigger, a first transmission gate, a first NOT gate, and a first capacitor, and an input terminal of the first monostable trigger is connected to a control clock module, first The output end of the monostable flip-flop is connected to the reverse control end of the first transmission gate, and the output end of the first monostable flip-flop is also connected to the forward control end of the first transmission gate via the first non-gate, the first transmission The input end of the gate is connected to the drain of the second P-channel MOS transistor of the level-up module, and the output end of the first transmission gate is grounded via the first capacitor;

The first comparison latch module includes a first comparator, a first NAND gate, and a first RS flip-flop. The positive terminal of the first comparator is connected to the FB terminal, and the negative terminal of the first comparator is connected to the first terminal. An output end of the first transmission gate of the voltage sampling module, the output end of the first comparator is connected to the S end of the first RS flip-flop via the first NAND gate;

The first control pulse generator includes a first counter, a second NAND gate, and a third NAND gate. The CP of the first counter is connected to the control clock module, and the Clr of the first counter is terminated with the first comparison lock. The output of the first RS flip-flop of the module, the first counter
The output end of the first RS flip-flop is outputted via the second NAND gate, the output end of the second NAND gate, the output end of the first RS flip-flop and the control clock module are also connected to the first RS via the third NAND gate. The R end of the trigger;

The drop fast response module includes a second NOT gate, a third P-channel MOS transistor, a fourth P-channel MOS transistor, and a third N-channel MOS transistor, and the gate of the third P-channel MOS transistor is connected Connected to the output of the second NAND gate, the output of the second NAND gate is further connected to the gate of the third N-channel MOS transistor via the second non-gate, and the source of the third P-channel MOS transistor is connected to the power source. The drains of the third P-channel MOS transistors are respectively connected to the sources of the FB terminal and the fourth P-channel MOS transistor, the gate of the fourth P-channel MOS transistor is connected to the voltage signal, and the drain of the fourth P-channel MOS transistor is drained. The pole is connected to the drain of the third N-channel MOS transistor, and the source of the third N-channel MOS transistor is grounded.
The dynamic fast response circuit of the switching power supply of claim 4, wherein the overshoot fast response module comprises:

The level shifting module shifts the voltage of the FB terminal by a small second positive voltage drop (ΔV2) to generate a voltage of the FB terminal minus the second positive voltage drop (VFB-ΔV2), and shifts this down. The subsequent voltage (VFB-ΔV2) is transmitted to the second voltage sampling module;

The second voltage sampling module periodically samples the shifted voltage under the control of the clock, and temporarily saves the sampled voltage, waits until the next sampling period to resample and refresh, and the sampled saved voltage is transmitted to the second comparison. Latch module

The second comparison latch module compares the sampled saved voltage with the FB terminal voltage, and the comparison result is output to the steady state determination module, and the comparison result is latched by the latch to determine if the voltage of the FB port is saved compared to the sample. When the voltage is low and the voltage loop is in a steady state state, a logic "yes" signal is output, indicating that the output voltage of the switching power supply suddenly increases; otherwise, a logic "no" signal is output, indicating that the output voltage of the switching power supply does not suddenly increase;

The second control pulse generator outputs an overshoot dynamic response signal after receiving the logic "yes" signal, and the control overshoot fast response module performs a fast response within the set time, and after the set time of the overshoot fast response module ends Generating a reset signal to reset the latch;

The overshoot fast response module receives the overshoot dynamic response signal and quickly extracts the current from the FB terminal, so that the FB terminal voltage rapidly drops to the second preset value, thereby rapidly reducing the duty cycle; the voltage at the FB terminal drops rapidly. After the second preset value is reached, the current is stopped immediately, and the voltage loop is adjusted by itself.
A dynamic fast response circuit for a switching power supply according to claim 7, further comprising: a control clock module for outputting a clock signal,

The level down module includes a second current source, a first N-channel MOS transistor, a second N-channel MOS transistor, and a second resistor, and the second current source is respectively connected to the first N-channel MOS transistor a drain, a gate of the first N-channel MOS transistor, and a gate of the second N-channel MOS transistor, and a source of the first N-channel MOS transistor is commonly connected to a source of the second N-channel MOS transistor The drain of the second N-channel MOS transistor is connected to the FB terminal via the second resistor;

The second voltage sampling module includes a second monostable trigger, a second transmission gate, a third NOT gate, and a second capacitor, wherein the input terminal of the second monostable trigger is connected to the control clock module, and the second The output of the monostable flip-flop is connected to the reverse control end of the second transmission gate, and the output of the second monostable flip-flop is also subjected to the third The non-gate is connected to the forward control end of the second transmission gate, the input end of the second transmission gate is connected to the drain of the second N-channel MOS transistor, and the output end of the second transmission gate is grounded via the second capacitor;

The second comparison latch module includes a second comparator, a fourth NAND gate, and a second RS flip-flop. The positive terminal of the second comparator is connected to the output end of the second transmission gate, and the second comparator is Negatively terminating the FB terminal, and the output end of the second comparator is connected to the S terminal of the second RS flip-flop via the fourth NAND gate;

The second control pulse generator includes a second counter, a fifth NAND gate, and a sixth NAND gate. The CP of the second counter is connected to the control clock module, and the Clr end of the second counter and the second RS are triggered. The output of the device is connected, the second counter
The output of the terminal and the second RS flip-flop is output through the fifth NAND gate, the output of the fifth NAND gate, the output of the second RS flip-flop and the clock signal are also triggered by the sixth NAND gate and the second RS. R end of the device;

The overshoot fast response module includes a fourth NOT gate and a fourth N-channel MOS transistor, and an output terminal of the fifth NAND gate of the second control pulse generator passes through the fourth NOT gate and the fourth N channel The gate of the MOS transistor is connected, the FB terminal is connected to the drain of the fourth N-channel MOS transistor via a diode, and the source of the fourth N-channel MOS transistor is grounded.
A dynamic fast response circuit for a switching power supply according to claim 6 or 8, characterized in that:

The steady state determining module includes a third counter, a third RS flip-flop, or a NOT gate, and the CP of the third counter is connected to the control clock module, and the third counter is
The terminal is connected to the S terminal of the third RS flip-flop, and the output of the first comparator of the first comparison latch module and the output of the second comparator of the second comparison latch module are respectively connected to the NOR gate The Clr end of the third counter is connected to the R end of the third RS flip-flop, and the Q end of the third RS flip-flop and the output end of the first comparator are connected to the S end of the first RS flip-flop via the first NAND gate, The Q terminal of the triple RS flip-flop is also coupled to the S terminal of the second comparator of the second comparison latch module via the second NAND gate.