CN104167411A - LED array structure - Google Patents
LED array structure Download PDFInfo
- Publication number
- CN104167411A CN104167411A CN201410409590.3A CN201410409590A CN104167411A CN 104167411 A CN104167411 A CN 104167411A CN 201410409590 A CN201410409590 A CN 201410409590A CN 104167411 A CN104167411 A CN 104167411A
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- Prior art keywords
- led array
- led
- insulated substrate
- pad
- metal
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Led Device Packages (AREA)
Abstract
The invention discloses an LED array structure. The LED array structure comprises an insulating substrate, multiple bonding pads, through holes, metal pins, heat dissipation layers, grooves, LED chips and optical elements, wherein the multiple bonding pads are distributed on the front side of the insulating substrate in an array mode, the bonding pads located in odd-number columns are vertically connected into multiple columns through metal wires, the bonding pads located on even-number columns are horizontally connected into multiple rows through metal wires, the through holes are formed in the insulating substrate, and the metal wires connecting each row of bonding pads and each column of bonding pads pass through the through holes to be led to the back side of the insulating substrate; the metal pins are arranged on the back side of the insulating substrate, electrically connected with the metal wires led to the back side of the insulating substrate and used for being connected with an external circuit, the heat dissipation layers are arranged on the lateral wall and/or back side of the insulating substrate and used for heat dissipation, the grooves are located on the front side of the insulating substrate and formed between every two bonding pads which are adjacent horizontally, the LED chips are fixed in the grooves, and the optical elements are used for packaging the LED chips to protect the LED chips and secondary light distribution.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of LED array structure.
Background technology
Along with the development of LED technology, LED range of application is also in continuous expansion, the particularly light source based on LED array, not only be used to make lighting and LCD backlight, for example, in special lighting field (animals and plants cultivation), initiatively Display Technique, projection light source, the fields such as adjustable spectral illumination and visible light communication are also applied gradually.In order to meet different occasion needs, give full play to the characteristic of LED, promote the output spectrum of LED array light source and the degree of freedom of light intensity, need to modulate the every LEDs in LED array.Along with technological progress, need the encapsulation of LED array light source constantly integrated simultaneously, miniaturization, and packaging technology and step are optimized, reduce product cost, simplify production technology.
Summary of the invention
For problems of the prior art, the object of the present invention is to provide a kind of LED array structure.
The present invention proposes a kind of LED array, comprising:
Insulated substrate;
Multiple pads, its array distribution is in insulated substrate front, and the pad that is positioned at odd column vertically connects into multiple row by metal wire, and the pad that is positioned at even column laterally connects into many rows by metal wire; Or the pad that is positioned at even column vertically connects into multiple row by metal wire, the pad that is positioned at odd column laterally connects into many rows by metal wire;
Through hole, it is opened on insulated substrate, and connects each row and the metal wire of each row pad is directed to the insulated substrate back side by described through hole;
Metal pin, it is arranged on the insulated substrate back side, and is electrically connected with the metal wire that causes the insulated substrate back side, for connecting external circuit;
Heat dissipating layer, it is arranged on insulated substrate sidewall and/or the back side, for heat radiation;
Groove, it is positioned at described insulated substrate front, and is formed between two laterally adjacent pads;
LED chip, it is fixed in described groove, and its first electrode with described in described groove place laterally one of adjacent two pads be electrically connected, another of the second electrode and described two pads is electrically connected;
Optical element, it is for encapsulating described LED chip, for the protection of LED chip and secondary light-distribution.
The said method that the present invention proposes has been optimized the electric connection of inner each LED chip of LED array, utilize conductive through hole simultaneously, metallic circuit is imported to the back side of substrate, distribute again and form the pin of LED array through electrode, that has realized on the one hand the output spectrum of any LEDs chip in LED array and even array and light intensity can modularity, flexibility ratio and the degree of freedom of the output of LED array light source light are increased, meet special lighting (animals and plants cultivation), initiatively Display Technique, projection light source, spectrum and the brightness requirement of adjustable spectral illumination to light emitting diode matrix, on the other hand, make the encapsulation of LED array more integrated, miniaturization, simplify packaging technology, reduce packaging cost.
Brief description of the drawings
Fig. 1 is the positive floor map of LED array structure described in the present invention;
Fig. 2 is the back side plane schematic diagram of LED array structure described in the present invention;
Fig. 3 is the schematic cross-section (formal dress structure LED chip) of described LED array structure;
LED array structural section schematic diagram (light emitting diode (LED) chip with vertical structure) described in Fig. 4.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
Refer to shown in Fig. 1 to Fig. 4, the invention provides a kind of LED array, it comprises:
Insulated substrate 10, it can be PCB substrate, ceramic substrate, sapphire substrate, organic material substrate or High Resistivity Si;
Multiple pads 101, array distribution is in the front of described insulated substrate 10;
Metallic circuit 102, it is connected between multiple pads 101; Alternatively, the connected mode of multiple pads 101 of described array distribution can be: between the pad 101 of odd column, vertically connect into respectively multiple row by metallic circuit 102, and the pad 101 that is positioned at even column connects into many rows by metallic circuit 102 cross direction profiles; The surface of described metallic circuit 102 is through protectiveness coating processing, for example cover silicon dioxide, polyimides or insulating cement or and combination, avoid being subject to the intrusion of machinery, steam, dust and pernicious gas, wherein any two described metallic circuit 102 intersection regions are all prepared with separator, as coating polyimide or silicon dioxide or and combination, avoid any two metallic traces 102 short circuits of opposed polarity or any two metallic traces 102 of polarity of the same race to be communicated with, realize independent control of every LEDs chip 106 in described LED array; Certainly, the connected mode of above-mentioned pad 101 can also be: between the pad 101 of even column, vertically connect into respectively multiple row by metallic circuit 102, and the pad 101 that is positioned at odd column laterally connects into respectively many rows by metallic circuit 102.
Multiple through holes 103, it is opened on insulated substrate 10, lays respectively near a pad of the multiple pad caudal end that connect into row, and connects near a pad of multiple pad caudal end of a line; Described through hole 103 is circular hole or groove, can utilize chemical corrosion, etching, the techniques such as laser, machine drilling or and process combination process; In described through hole 103, be filled with conducting metal 107, the conducting metal 107 of filling in described through hole 103 can be all fill or be partially filled, described being partially filled refers to and on the sidewall of through hole 103, fills one deck conducting metal 107, and described through hole 103 is electrically connected with near pad;
Metal pin 104, its be described metallic circuit 102 be directed to insulated substrate 10 through through hole 103 the back side after the metal pins that forms, object is in order to carry out electrode distribution design again; Described metal pin 104 is for being connected with external drive circuit, or splices with LED array structure described in other, to form more large-area LED array structure;
Heat dissipating layer 105, it is arranged on sidewall and/or the back side of described insulated substrate 10, effectively to reduce the working temperature of LED chip 106;
Groove 108, it is positioned at the front of described insulated substrate 10, described groove 108 is formed between two laterally adjacent pads 101, it can utilize chemical corrosion, etching, laser or machine drilling technique or and process combination process,
LED chip 106, it is formed in the described groove 108 between two laterally adjacent pads 101, wherein p electrode 109 is electrically connected with one of adjacent two pads 101, and n electrode 110 is electrically connected with another pad 101, has insulating material isolation between p electrode 109 and n electrode 110; Described LED chip 106 can be positive assembling structure, vertical stratification or growth substrates with the LED chip of conductivity through-hole structure or and combination, according to the difference of described LED chip 106 structures, for example formal dress structure chip, groove 108 bottoms are covered with insulating cement, silver slurry for die bond, for thin-film LED, there is silver slurry groove 108 bottoms for die bond, or conductive metal layer etc., be convenient to adopt eutectic technology fixed chip; Described LED chip 106 is according to the difference of its epitaxial material, and output spectrum can cover the wave-length coverage of deep ultraviolet to remote infrared;
In the present invention, every LEDs chip takies two pads (the each corresponding pad of positive and negative electrode), pad on substrate connects principle: positive pole (or negative pole) pad that is positioned at same a line LED chip connects by metal wire, and negative pole (or anodal) pad that is positioned at same row LED chip connects by metal wire.
Gap between LED chip 106 and the groove 108 that put described groove 108 inside is filled with insulating material 111, described insulating material can be gap filled polyimide, silicon dioxide, insulating cement, silica gel or and combination;
Between the pad 101 in p electrode 109, n electrode 110 and insulated substrate 10 fronts of described LED chip 106, be connected by conducting metal 107, described connection by 3D print, metal evaporation technique, ball bonding or and group technology realize;
Described LED array structure; comprise the optical element 112 that can regulate its outside allocation of square; described optical element 112 is encapsulated in the outside of described LED chip as the package casing of LED chip 106; it forms alone or in combination for resin or silica gel or glass or other transparent materials; described optical element 112 can improve the luminous efficiency of LED chip; play the effect of fluorescence conversion, described optical element 112 can play to LED chip 106 effect of protection and secondary light-distribution.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect have been carried out to further detailed description; institute is understood that; the foregoing is only the specific embodiment of the present invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a LED array, comprising:
Insulated substrate;
Multiple pads, its array distribution is in insulated substrate front, and the pad that is positioned at odd column vertically connects into multiple row by metal wire, and the pad that is positioned at even column laterally connects into many rows by metal wire; Or the pad that is positioned at even column vertically connects into multiple row by metal wire, the pad that is positioned at odd column laterally connects into many rows by metal wire;
Through hole, it is opened on insulated substrate, and connects each row and the metal wire of each row pad is directed to the insulated substrate back side by described through hole;
Metal pin, it is arranged on the insulated substrate back side, and is electrically connected with the metal wire that causes the insulated substrate back side, for connecting external circuit;
Heat dissipating layer, it is arranged on insulated substrate sidewall and/or the back side, for heat radiation;
Groove, it is positioned at described insulated substrate front, and is formed between two laterally adjacent pads;
LED chip, it is fixed in described groove, and its first electrode with described in described groove place laterally one of adjacent two pads be electrically connected, another of the second electrode and described two pads is electrically connected;
Optical element, it is for encapsulating described LED chip, for the protection of LED chip and secondary light-distribution.
2. LED array as claimed in claim 1, wherein, described metal pin is also electrically connected with other LED array, to splice multiple LED array.
3. LED array as claimed in claim 1, wherein, described metallic circuit surface process protectiveness coating processing, and be prepared with insulating barrier in any two metallic traces intersection regions.
4. LED array as claimed in claim 1, described through hole is circular hole or groove, is filled with conducting metal in through hole.
5. LED array as claimed in claim 1, wherein, described LED chip comprises vertically, formal dress or growth substrates be with conductivity through-hole structure, and in described groove, is covered with insulating cement and silver slurry or conducting metal according to these three kinds of different structure kinds.
6. LED array as claimed in claim 1, wherein, described optical element is one or more the combination in silica gel, resin, glass.
7. LED array as claimed in claim 3, wherein, described metallic circuit surface refers to that through protectiveness coating processing its surface coverage has one or more the combination in silicon dioxide, polyimides, insulating cement.
8. LED array as claimed in claim 1, wherein, is filled with insulating material in the space between described LED chip and groove.
9. LED array as claimed in claim 1, wherein, described groove is that the combination by utilize chemical corrosion, etching, laser or machine drilling technique and aforementioned technique thereof on insulated substrate processes.
10. LED array as claimed in claim 1, wherein, is connected by conducting metal between described LED chip and pad, and described conducting metal by 3D print, one or more combination in metal evaporation technique, ball bonding forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410409590.3A CN104167411A (en) | 2014-08-19 | 2014-08-19 | LED array structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410409590.3A CN104167411A (en) | 2014-08-19 | 2014-08-19 | LED array structure |
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| Publication Number | Publication Date |
|---|---|
| CN104167411A true CN104167411A (en) | 2014-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410409590.3A Pending CN104167411A (en) | 2014-08-19 | 2014-08-19 | LED array structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742228A (en) * | 2014-12-09 | 2016-07-06 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN107678215A (en) * | 2017-05-24 | 2018-02-09 | 麒麟电子（深圳）有限公司 | The manufacturing process and LCD terminal of LCD terminal |
| CN107946429A (en) * | 2017-10-27 | 2018-04-20 | 佛山市国星光电股份有限公司 | A kind of device packaging method and corresponding device encapsulation structure |
| CN108287436A (en) * | 2018-01-31 | 2018-07-17 | 武汉华星光电技术有限公司 | Backlight module and liquid crystal display device |
| CN108686907A (en) * | 2017-04-10 | 2018-10-23 | 上海臻辉光电技术有限公司 | The system and method for coating on curing optical fiber |
| CN108700275A (en) * | 2016-02-24 | 2018-10-23 | 奇跃公司 | Low profile for optical transmitting set interconnects |
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| JPH06278313A (en) * | 1993-03-25 | 1994-10-04 | Kyocera Corp | Image device |
| US20060220048A1 (en) * | 2005-03-30 | 2006-10-05 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and semiconductor light emitting unit |
| CN102931330A (en) * | 2012-11-12 | 2013-02-13 | 中国科学院半导体研究所 | Preparation method of LED (light-emitting diode) flat-panel display unit |
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2014
- 2014-08-19 CN CN201410409590.3A patent/CN104167411A/en active Pending
Patent Citations (4)
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| JPH01306110A (en) * | 1988-04-16 | 1989-12-11 | Robert Bosch Gmbh | Manual power tool |
| JPH06278313A (en) * | 1993-03-25 | 1994-10-04 | Kyocera Corp | Image device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742228A (en) * | 2014-12-09 | 2016-07-06 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105742228B (en) * | 2014-12-09 | 2019-04-19 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN108700275A (en) * | 2016-02-24 | 2018-10-23 | 奇跃公司 | Low profile for optical transmitting set interconnects |
| US11264548B2 (en) | 2016-02-24 | 2022-03-01 | Magic Leap, Inc. | Low profile interconnect for light emitter |
| US11811011B2 (en) | 2016-02-24 | 2023-11-07 | Magic Leap, Inc. | Low profile interconnect for light emitter |
| CN108686907A (en) * | 2017-04-10 | 2018-10-23 | 上海臻辉光电技术有限公司 | The system and method for coating on curing optical fiber |
| CN107678215A (en) * | 2017-05-24 | 2018-02-09 | 麒麟电子（深圳）有限公司 | The manufacturing process and LCD terminal of LCD terminal |
| CN107946429A (en) * | 2017-10-27 | 2018-04-20 | 佛山市国星光电股份有限公司 | A kind of device packaging method and corresponding device encapsulation structure |
| CN108287436A (en) * | 2018-01-31 | 2018-07-17 | 武汉华星光电技术有限公司 | Backlight module and liquid crystal display device |
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Application publication date: 20141126 |
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