CN104124253A - Thin film transistor substrate - Google Patents
Thin film transistor substrate Download PDFInfo
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- CN104124253A CN104124253A CN201310194497.0A CN201310194497A CN104124253A CN 104124253 A CN104124253 A CN 104124253A CN 201310194497 A CN201310194497 A CN 201310194497A CN 104124253 A CN104124253 A CN 104124253A
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- film transistor
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Abstract
The invention provides a thin film transistor substrate which comprises a transparent substrate, a first insulation layer, a second insulation layer and a plurality of thin film transistors. Each thin film transistor comprises a grid, a source, a drain, a channel layer and a channel protection layer. The grid is formed on the transparent substrate, the first insulation layer covers the grid, the channel layer is formed on the first insulation layer at the position right corresponding to the grid, the channel protection layer is directly formed on the channel layer, the source and the drain are formed on the first insulation layer and are connected with two opposite sides of the channel layer, and the second insulation layer is formed on the first insulation layer and covers the source, the drain, the channel layer and the channel protection layer. Compared with the prior art, the thin film transistor substrate can achieve the effect that a switching element in the thin film transistor substrate can be effectively buffered and is not easy to damage when being pressed, and the service life is long.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate.
Background technology
Display panels generally includes a thin film transistor base plate, a colored filter substrate and is clipped in the liquid crystal layer between these two substrates, it is to realize passing through or not passing through of light by applying voltage to control liquid crystal molecule torsion therebetween, thereby reaches the object of demonstration.Wherein, on described thin film transistor base plate, be provided with the thin-film transistor of multiple array arrangements as the switch element of transmitting display signal therefor.But, the channel layer of described thin-film transistor easily damages in the time being subject to pressing, especially in the display panels of high-res, the switch element in thin film transistor base plate is very easily damaged by pressure by the sept of colored filter one side, thereby causes picture disply abnormal.
Summary of the invention
Given this, be necessary to provide a kind of thin film transistor base plate, comprise transparency carrier, the first insulating barrier, the second insulating barrier and multiple thin-film transistor.Wherein, each thin-film transistor comprises grid, source electrode, drain, channel layer and path protection layer.Described grid is formed on described transparency carrier; described the first insulating barrier covers described grid; described channel layer is formed on described the first insulating barrier the just position to described grid; described path protection layer is formed directly on described channel layer; described source electrode is formed on described the first insulating barrier and respectively and is connected with the relative both sides of channel layer with drain, and described the second insulating barrier is formed on described the first insulating barrier and covers described source electrode, drain, channel layer and path protection layer.
Compared to prior art, the switch element in thin film transistor base plate of the present invention can effectively be cushioned in the time being subject to pressing, and is not easy to be damaged by pressure longer service life.
Brief description of the drawings
Fig. 1 is the part plan structural representation of thin film transistor base plate of the present invention.
Fig. 2 is the sectional structure schematic diagram along V-V line of thin film transistor base plate shown in Fig. 1.
Fig. 3 is the local enlarged diagram of thin-film transistor in Fig. 1.
Main element symbol description
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
See also Fig. 1 and Fig. 2, thin film transistor base plate 100 comprises transparency carrier 20, the scan line 110 being parallel to each other, public electrode wire 130, thin-film transistor 10, gate insulator 30, pixel electrode 150, public electrode 160, passivation layer 40 and the through hole 135 that insulate crossing data wire 120 with described scan line 110, is parallel to each other.Described public electrode wire 130 arranges and insulation with described scan line 110 intervals.Described public electrode wire 130 extends along the direction that is parallel to described scan line 110, and crossing with described data wire 120 insulation.Described public electrode wire 130 is electrically connected by described through hole 135 with described public electrode 160.Any two adjacent described scan lines 110 define a pixel region 140 with any two adjacent described data wires 120.In the present embodiment, the data wire 120 of each pixel region 140 both sides is all V-shape; In other embodiments, described data wire 120 also can be by many parallel rectilinear(-al)s.
Described thin-film transistor 10 is arranged at a scan line 110 and data wire 120 intersections in each pixel region 140, and it comprises grid 11, source electrode 12, drain 13, channel layer 14 and path protection layer 15.Described grid 11 is connected with described scan line 110, and described source electrode 12 is connected with described data wire 120, and described drain 13 is electrically connected with described pixel electrode 150 1 sides.Described pixel electrode 150 is positioned at same layer with described drain 13, and described pixel electrode 150 covers pixel region 140.
Described grid 11, scan line 110 and public electrode wire 130 are formed on described transparency carrier 20; Described gate insulator 30 is formed on described transparency carrier 20, and covers described grid 11, scan line 110 and public electrode wire 130; Described channel layer 14 is formed on described gate insulator 30, and just to described grid 11; Described data wire 120 is formed on described gate insulator 30; Described source electrode 12 and drain 13 are formed on described gate insulator 30 and described channel layer 14, and each interval is to expose described channel layer 14; Described path protection layer 15 is formed on described channel layer 14; Described pixel electrode 150 is formed on described gate insulator 30, and is electrically connected with described drain 13; Described passivation layer 40 is formed on described gate insulator 30, and covers described source electrode 12, channel layer 14, path protection layer 15, drain 13 and pixel electrode 150; Described through hole 135 be arranged on the position corresponding with described public electrode wire 130 and run through described passivation layer 40 with gate insulator 30 until described public electrode wire 130.Described public electrode 160 is formed on described passivation layer 40, is connected with public electrode wire 130 by through hole 135.Between described public electrode 160 and described pixel electrode 150, there is described passivation layer 40 at interval.
In the plane; the shape of described path protection layer 15 can arrange according to described source electrode 12 and the shape of drain 13; example as shown in Figure 3; in the present embodiment; described source electrode 12 is by the extended in the plane C font structure of data wire 120 1 sides, the data wire 120 that this C font source electrode 12 connects away from the end almost parallel of data wire 120.Described drain 13 is a L font structure, its contiguous segment data line 120 of one end almost parallel of this L font drain 13, and stretch in the space that described C font source electrode 12 accommodates and do not contact with the each face of described source electrode 12 simultaneously, and substantially vertical its contiguous segment data line 120 of the other end of described drain 13 away from its contiguous data wire 120.Described channel layer 14 is a D font structure.Described C font source electrode 12 is positioned at described channel layer 14 and the curved edge setting along D font channel layer 14 substantially.One end that described drain 13 stretches into described C font source electrode 12 is positioned at described channel layer 14 substantially, and the other end of described drain 13 is positioned at outside this channel layer 14.Described path protection layer 15 is seen the U font structure that is an opening direction almost parallel data wire from in-plane.This path protection layer 15 is arranged at intervals between described source electrode 12 and drain 13, and is positioned at channel layer 14 completely.
The described path protection layer 15 being formed on channel layer 14 can, in the time that described thin film transistor base plate 100 is subject to pressing, play cushioning effect to the channel layer 14 of its below, so that described channel layer 14 is protected.In the present embodiment, the material of described path protection layer 15 is tin indium oxide (Indium Tin Oxide, ITO); In other embodiments, the material of described path protection layer 15 can be also insulating material.In the present embodiment, described path protection layer 15 opposite end leave space respectively and between described source electrode 12 and drain 13; In other embodiments, in the time of the material of described path protection layer 15, when insulating material, the opposite end of described path protection layer 15 also can extend to described source electrode 12 and drain 13 places.
Above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not depart from the spirit and scope of technical solution of the present invention.
Claims (11)
1. a thin film transistor base plate, comprising:
Transparency carrier, the first insulating barrier, the second insulating barrier and multiple thin-film transistor, wherein, each thin-film transistor comprises grid, source electrode, drain, channel layer and path protection layer, described grid is formed on described transparency carrier, described the first insulating barrier covers described grid, described channel layer is formed on described the first insulating barrier the just position to described grid, described path protection layer is formed directly on described channel layer, described source electrode is formed on described the first insulating barrier and respectively and is connected with the relative both sides of channel layer with drain, described the second insulating barrier is formed on described the first insulating barrier and covers described source electrode, drain, channel layer and path protection layer.
2. thin film transistor base plate as claimed in claim 1, is characterized in that: the material of described path protection layer is tin indium oxide.
3. thin film transistor base plate as claimed in claim 2, is characterized in that: described path protection layer, between source electrode and drain, and has space between the opposite end of described path protection layer and described source electrode and drain.
4. thin film transistor base plate as claimed in claim 1, is characterized in that: the material of described path protection layer is insulating material.
5. thin film transistor base plate as claimed in claim 4, is characterized in that: described path protection layer is between source electrode and drain, and described path protection laminating invests described source electrode and drain.
6. thin film transistor base plate as claimed in claim 1, is characterized in that: described the first insulating barrier is gate insulator, and described the second insulating barrier is passivation layer.
7. thin film transistor base plate as claimed in claim 1, is characterized in that: described thin film transistor base plate also comprises the scan line and the data wire that are parallel to each other, and described scan line is crossing with described data wire insulation.
8. thin film transistor base plate as claimed in claim 7, it is characterized in that: described source electrode is by the extended in the plane C font structure of data wire one side, the data wire that this C font source electrode connects away from the end almost parallel of data wire, described drain is a L font structure, its contiguous segment data line of one end almost parallel of this L font drain, and stretch in the space that described C font source electrode accommodates and do not contact with the each face of described source electrode simultaneously, and substantially vertical its contiguous segment data line of the other end of described drain away from its contiguous data wire, described channel layer is a D font structure, described C font source electrode is positioned at described channel layer and the curved edge setting along D font channel layer substantially, one end that described drain stretches into described C font source electrode is positioned at described channel layer substantially, and the other end of described drain is positioned at outside this channel layer, described path protection layer is seen the U font structure that is an opening direction almost parallel data wire from in-plane, this path protection layer is arranged at intervals between described source electrode and drain, and be positioned at channel layer completely.
9. the thin film transistor base plate as described in claim 1-8 any one, it is characterized in that: described thin film transistor base plate also comprises the first electrode layer, the second electrode lay, many public electrode wires that are parallel to each other and through hole, described the first electrode layer is located between described the first insulating barrier and described the second insulating barrier, and be electrically connected with described drain, described the second electrode is formed on described the second insulating barrier, and is connected with public electrode wire by described through hole.
10. thin film transistor base plate as claimed in claim 9, is characterized in that: described the first electrode layer is pixel electrode, and described the second electrode lay is public electrode.
11. thin film transistor base plates as claimed in claim 9, is characterized in that: the material of described the first electrode layer and described the second electrode lay is tin indium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310194497.0A CN104124253A (en) | 2013-05-23 | 2013-05-23 | Thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310194497.0A CN104124253A (en) | 2013-05-23 | 2013-05-23 | Thin film transistor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104124253A true CN104124253A (en) | 2014-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310194497.0A Pending CN104124253A (en) | 2013-05-23 | 2013-05-23 | Thin film transistor substrate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106125430A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, display floater and array base palte |
Citations (6)
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|---|---|---|---|---|
| US6054749A (en) * | 1997-10-21 | 2000-04-25 | International Business Machines Corporation | Thin film device repaired using enhanced repair process |
| US20040109120A1 (en) * | 2002-12-10 | 2004-06-10 | Lee Deuk Su | In-plane switching liquid crystal display with an alignment free structure and method of using back exposure to form the same |
| CN101097962A (en) * | 2006-06-26 | 2008-01-02 | 中华映管股份有限公司 | Dual-channel film transistor |
| US20080135846A1 (en) * | 2006-12-12 | 2008-06-12 | Kyoung-Ju Shin | Thin film transistor substrate and method of manufacture |
| CN102136499A (en) * | 2010-01-26 | 2011-07-27 | 三星电子株式会社 | Thin film transistor and method of manufacturing the same |
| CN102184966A (en) * | 2011-04-15 | 2011-09-14 | 福州华映视讯有限公司 | Transistor array substrate |
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2013
- 2013-05-23 CN CN201310194497.0A patent/CN104124253A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054749A (en) * | 1997-10-21 | 2000-04-25 | International Business Machines Corporation | Thin film device repaired using enhanced repair process |
| US20040109120A1 (en) * | 2002-12-10 | 2004-06-10 | Lee Deuk Su | In-plane switching liquid crystal display with an alignment free structure and method of using back exposure to form the same |
| CN101097962A (en) * | 2006-06-26 | 2008-01-02 | 中华映管股份有限公司 | Dual-channel film transistor |
| US20080135846A1 (en) * | 2006-12-12 | 2008-06-12 | Kyoung-Ju Shin | Thin film transistor substrate and method of manufacture |
| CN102136499A (en) * | 2010-01-26 | 2011-07-27 | 三星电子株式会社 | Thin film transistor and method of manufacturing the same |
| CN102184966A (en) * | 2011-04-15 | 2011-09-14 | 福州华映视讯有限公司 | Transistor array substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106125430A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, display floater and array base palte |
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Application publication date: 20141029 |