CN106125430A - The preparation method of array base palte, display floater and array base palte - Google Patents
The preparation method of array base palte, display floater and array base palte Download PDFInfo
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- CN106125430A CN106125430A CN201610728953.9A CN201610728953A CN106125430A CN 106125430 A CN106125430 A CN 106125430A CN 201610728953 A CN201610728953 A CN 201610728953A CN 106125430 A CN106125430 A CN 106125430A
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- active layer
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- base palte
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000012212 insulator Substances 0.000 claims abstract description 41
- 238000002161 passivation Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000010409 thin film Substances 0.000 description 20
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 239000010949 copper Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The open a kind of array base palte of the present invention, including: substrate；Grid, is formed on substrate；Gate insulator, is formed at the side towards grid of substrate, and gate insulator covers grid；Active layer, is formed at the side away from grid of gate insulator, and active layer uses metal oxide materials and just arranging grid；The source electrode being spaced and drain electrode, be formed at the side away from grid of gate insulator, source electrode and drain electrode and be respectively connecting to the two ends of active layer；Passivation layer, is formed at the side away from gate insulator of source electrode, and passivation layer covers source electrode, drain electrode and active layer；And light shield layer, it being formed at the side away from active layer of passivation layer, light shield layer upright projection on gate insulator is coated with active layer.The yield of array base palte of the present invention is high.Invention additionally discloses a kind of display floater and the preparation method of a kind of array base palte.
Description
Technical field
The present invention relates to technical field of display panel, particularly relate to a kind of array base palte, a kind of display floater and one
The preparation method of array base palte.
Background technology
Along with plane display dresses such as the development of Display Technique, liquid crystal displays (Liquid Crystal Display, LCD)
Put because having that high image quality, power saving, fuselage be thin and the advantage such as applied range, and be widely used in mobile phone, TV, individual number
The various consumption electronic products such as word assistant, digital camera, notebook computer, desk computer, become the master in display device
Stream.
Liquid crystal indicator major part on existing market is backlight liquid crystal display, it include display panels and
Backlight module (back light module).The operation principle of display panels is in the middle of the glass substrate that two panels is parallel
Place liquid crystal molecule, have many tiny electric wires vertically and horizontally in the middle of two panels glass substrate, control liquid by whether being energized
Brilliant molecular changes direction, reflects generation picture by the light of backlight module.
Generally display panels is by color film (Color Filter, CF) substrate, thin film transistor (TFT) (Thin Film
Transistor, TFT) array base palte, the liquid crystal (Liquid Crystal, LC) being sandwiched between color membrane substrates and array base palte and
Fluid sealant frame (Sealant) forms.Wherein, the thin-film transistor performance of array base palte directly influences the aobvious of display panels
Show quality.
Along with large scale and high PPI (Pixels Per Inch, the number of pixels that per inch is had) and high refreshing frequently
The exploitation of rate product, uses the thin film transistor (TFT) of oxide semiconductor to receive pay attention to widely owing to having higher mobility
And application.Yet with oxide semiconductor easily by illumination effect, thus cause the electrical unstable of thin film transistor (TFT), array
The product yield of substrate is low.
Summary of the invention
The technical problem to be solved is the array base palte providing a kind of yield high.
Additionally, also provide for a kind of display floater applying described array base palte.
It addition, also provide for the preparation method of a kind of array base palte.
To achieve these goals, embodiment of the present invention adopts the following technical scheme that
On the one hand, it is provided that a kind of array base palte, including:
Substrate；
Grid, is formed on the substrate；
Gate insulator, is formed at the side towards described grid of described substrate, and described gate insulator covers described
Grid；
Active layer, is formed at the side away from described grid of described gate insulator, and described active layer uses metal oxygen
Compound material and just described grid being arranged；
The source electrode being spaced and drain electrode, be formed at the side away from described grid of described gate insulator, described source
Pole and described drain electrode are respectively connecting to the two ends of described active layer；
Passivation layer, is formed at the side away from described gate insulator of described source electrode, and described passivation layer covers described source
Pole, described drain electrode and described active layer；And
Light shield layer, is formed at the side away from described active layer of described passivation layer, and described light shield layer is exhausted at described grid
Upright projection in edge layer covers described active layer.
Wherein, described light shield layer uses black resin material.
Wherein, described active layer uses indium gallium zinc oxide.
Wherein, described passivation layer has through hole, in order to expose the described source electrode of part；
Described array base palte also include pixel electrode, described pixel electrode be formed at described passivation layer away from described source electrode
Side, described pixel electrode is connected to described source electrode by described through hole.
On the other hand, a kind of display floater is also provided for, including the array base palte described in as above any one.
Yet another aspect, also provides for the preparation method of a kind of array base palte, including:
Substrate sequentially forms grid；
Forming gate insulator in the side towards described grid of described substrate, described gate insulator covers described grid
Pole；
Be formed with active layer in the side away from described grid of described gate insulator, described active layer uses burning
Thing material and just described grid being arranged；
The source electrode and drain electrode, described source electrode being spaced is formed in the side away from described grid of described gate insulator
With the two ends that described drain electrode is respectively connecting to described active layer；
Forming passivation layer in the side away from described gate insulator of described source electrode, described passivation layer covers described simultaneously
Source electrode, described drain electrode and described active layer；And
Forming light shield layer in the side away from described active layer of described passivation layer, described light shield layer is at described gate insulator
Upright projection on layer covers described active layer.
Wherein, identical light shield is used to form described active layer and described light shield layer.
Wherein, described light shield layer uses black resin material.
Wherein, described active layer uses indium gallium zinc oxide.
Wherein, the preparation method of described array base palte also includes:
Described passivation layer forms through hole, in order to expose the described source electrode of part；
Forming pixel electrode in the side away from described source electrode of described passivation layer, described pixel electrode passes through described through hole
It is connected to described source electrode.
Compared to prior art, the method have the advantages that
Array base palte of the present invention is owing to being provided with described light shield layer, therefore, it is possible to it is brilliant to prevent light from entering described thin film
The described active layer of body pipe so that described thin film transistor (TFT) has good electrical stability, and the performance of described array base palte is good
Good, yield height.
Accompanying drawing explanation
In order to be illustrated more clearly that technical scheme, the accompanying drawing used required in embodiment will be made below
Introduce simply, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, general for this area
From the point of view of logical technical staff, on the premise of not paying creative work, it is also possible to as these accompanying drawings obtain other accompanying drawing.
Fig. 1 to Fig. 8 is the structure of each step of the preparation method of a kind of array base palte that embodiment of the present invention provides
Schematic diagram.
Fig. 9 is the structural representation of a kind of display floater that embodiment of the present invention provides.
Detailed description of the invention
Below in conjunction with the accompanying drawing in embodiment of the present invention, the technical scheme in embodiment of the present invention is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole realities
Execute mode.Based on the embodiment in the present invention, those of ordinary skill in the art are institute under not making creative work premise
The every other embodiment obtained, broadly falls into the scope of protection of the invention.
Referring to Fig. 8, embodiment of the present invention provides a kind of array base palte 10, including substrate 1, grid 2, gate insulator
3, active layer 4, the source electrode 5 being spaced and drain electrode 6, passivation layer 7 and light shield layer 8.Wherein, described grid 2 is formed at described
On substrate 1.Described gate insulator 3 is formed at the side towards described grid 2 of described substrate 1 and covers described grid 2.Institute
Stating active layer 4 and be formed at the side away from described grid 2 of described gate insulator 3, described active layer 4 uses metal-oxide
Material and just described grid 2 being arranged.Described source electrode 5 and described drain electrode 6 be formed at described gate insulator 3 away from described grid
The side of pole 2, and it is respectively connecting to the two ends of described active layer 4.Described passivation layer 7 be formed at described source electrode 5 away from institute
Stating the side of gate insulator 3, described passivation layer 7 covers described source electrode 5, described drain electrode 6 and described active layer 4 simultaneously.Institute
Stating light shield layer 8 and be formed at the side away from described active layer 4 of described passivation layer 7, described light shield layer 8 is at described gate insulator
Upright projection on 3 covers described active layer 4.
Array base palte 10 described in present embodiment, owing to it is provided with described light shield layer 8, therefore, it is possible to effectively prevent light
Enter the described active layer 4 of described thin film transistor (TFT) so that described thin film transistor (TFT) has good electrical stability, described battle array
Row substrate 10 functional, yield is high.
Wherein, one or more during the material of described grid 2 can be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti)
Heap stack combination.Described grid 2 equally plays interception, has in order to prevent light from entering described in described thin film transistor (TFT)
Active layer 4 so that described thin film transistor (TFT) has good electrical stability, improves the yield of described array base palte 10.
Further, as a kind of optional embodiment, described light shield layer 8 uses black resin material, low cost, technique
Ripe.
Preferably, described active layer 4 uses indium gallium zinc oxide so that the threshold voltage of described thin film transistor (TFT) does not floats
Moving, carrier solubility is high, quickly-chargeable, thus promotes yield and the charge rate of described thin film transistor (TFT).
Further, seeing also Fig. 7 and Fig. 8, as a kind of optional embodiment, described passivation layer 7 has through hole
70, described through hole 70 is in order to source electrode described in expose portion 5.Described array base palte 10 also includes pixel electrode 9, described pixel electrode
9 are formed on described passivation layer 7 and connect described source electrode 5 by described through hole 70.
Seeing also Fig. 8 and Fig. 9, embodiment of the present invention also provides for a kind of display floater 100, described display floater
100 include the array base palte 10 being oppositely arranged and color membrane substrates 20 and are positioned at described array base palte 10 and described color membrane substrates 20
Between liquid crystal layer 30, described array base palte 10 uses the array base palte 10 described in arbitrary institute embodiment.Due to described
Array base palte 10 has higher yield and performance so that described display floater 100 display quality is good.
Seeing also Fig. 1 to Fig. 6, embodiment of the present invention also provides for the preparation method of a kind of array base palte, including:
Step1: sequentially form grid 2 on substrate 1, as shown in Figure 1；
Step2: form gate insulator 3, described gate insulator 3 in the side towards described grid 2 of described substrate 1
Cover described grid 2, as shown in Figure 2；
Step3: be formed with active layer 4 in the side away from described grid 2 of described gate insulator 3, described active layer 4 is adopted
With metal oxide materials and just described grid 2 is being arranged, as shown in Figure 3；
Step4: form the source electrode 5 and drain electrode being spaced in the side away from described grid 2 of described gate insulator 3
6, described source electrode 5 and described drain electrode 6 are respectively connecting to the two ends of described active layer 4, described grid 2, described active layer 4, described
Source electrode 5 and described drain electrode 6 are collectively forming a thin film transistor (TFT), as shown in Figure 4；
Step5: form passivation layer 7 in the side away from described gate insulator 3 of described source electrode 5, described passivation layer 7 is same
Time cover described source electrode 5, described drain electrode 6 and described active layer 4, as shown in Figure 5；
Step6: forming light shield layer 8 in the side away from described active layer 4 of described passivation layer 7, described light shield layer 8 is in institute
State the upright projection on gate insulator 3 and cover described active layer 4, as shown in Figure 6.
The array base palte 10 formed by the preparation method of array base palte described in present embodiment, described owing to being provided with
Light shield layer 8, therefore, it is possible to prevent light from entering the described active layer 4 of described thin film transistor (TFT) so that described thin film transistor (TFT) has
Have good electrical stability, described array base palte 10 functional, yield is high, so the preparation method of described array base palte
Product yield high.
Wherein, one or more during the material of described grid 2 can be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti)
Heap stack combination.Described grid 2 equally plays interception, has in order to prevent light from entering described in described thin film transistor (TFT)
Active layer 4 so that described thin film transistor (TFT) has good electrical stability, improves the product of the preparation method of described array base palte
Product yield.
Further, as a kind of optional embodiment, identical light shield can be used to form described active layer 4 and described screening
Photosphere 8, to reduce light shield quantity required in processing procedure, reduces production cost.
It should be understood that owing to position and the shape of described light shield layer 8 are completely corresponding to described active layer 4 and arrange,
Therefore identical light shield can be used to form described active layer 4 and described light shield layer 8.It should also be noted that at described light shield layer 8
In processing procedure, can make described light shield suitably coordinate processing procedure debugging (when such as adjusting exposure described light shield and light shield layer 8 place film layer it
Between spacing), so that the area of described light shield layer 8 is slightly larger than the area of described active layer 4, thus cover all described active
Layer 4, effectively prevents light from entering described active layer 4.
Further, as a kind of optional embodiment, described light shield layer 8 uses black resin material, low cost, technique
Ripe.
Preferably, described active layer 4 uses indium gallium zinc oxide so that the threshold voltage of described thin film transistor (TFT) does not floats
Moving, carrier solubility is high, quickly-chargeable, thus promotes yield and the charge rate of described thin film transistor (TFT).
Further, referring to Fig. 7 and Fig. 8, as a kind of optional embodiment, the preparation method of described array base palte is also
Including:
Step7: form through hole 70 on described passivation layer 7, in order to expose the described source electrode of part 5, as shown in Figure 7；
Step8: form pixel electrode 9 in the side away from described source electrode 5 of described passivation layer 7, described pixel electrode 9 leads to
Cross described through hole 70 and be connected to described source electrode 5, as shown in Figure 8.
Above embodiment of the present invention is described in detail, the specific case principle to the present invention used herein
And embodiment is set forth, the explanation of embodiment of above is only intended to help to understand that the method for the present invention and core thereof are thought
Think；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, in specific embodiments and applications
All will change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (10)
1. an array base palte, it is characterised in that including:
Substrate；
Grid, is formed on the substrate；
Gate insulator, is formed at the side towards described grid of described substrate, and described gate insulator covers described grid；
Active layer, is formed at the side away from described grid of described gate insulator, and described active layer uses metal-oxide
Material and just described grid being arranged；
The source electrode being spaced and drain electrode, be formed at the side away from described grid of described gate insulator, described source electrode and
Described drain electrode is respectively connecting to the two ends of described active layer；
Passivation layer, is formed at the side away from described gate insulator of described source electrode, and described passivation layer covers described source electrode, institute
State drain electrode and described active layer；And
Light shield layer, is formed at the side away from described active layer of described passivation layer, and described light shield layer is at described gate insulator
On upright projection cover described active layer.
2. array base palte as claimed in claim 1, it is characterised in that described light shield layer uses black resin material.
3. array base palte as claimed in claim 1 or 2, it is characterised in that described active layer uses indium gallium zinc oxide.
4. array base palte as claimed in claim 1, it is characterised in that described passivation layer has through hole, in order to expose part
Described source electrode；
Described array base palte also include pixel electrode, described pixel electrode be formed at described passivation layer away from the one of described source electrode
Side, described pixel electrode is connected to described source electrode by described through hole.
5. a display floater, it is characterised in that include the array base palte as described in any one of Claims 1 to 4.
6. the preparation method of an array base palte, it is characterised in that including:
Substrate sequentially forms grid；
Forming gate insulator in the side towards described grid of described substrate, described gate insulator covers described grid；
Be formed with active layer in the side away from described grid of described gate insulator, described active layer uses metal-oxide material
Expect and just described grid arranged；
The source electrode and drain electrode, described source electrode and institute being spaced is formed in the side away from described grid of described gate insulator
State drain electrode and be respectively connecting to the two ends of described active layer；
Forming passivation layer in the side away from described gate insulator of described source electrode, described passivation layer covers described source simultaneously
Pole, described drain electrode and described active layer；And
Forming light shield layer in the side away from described active layer of described passivation layer, described light shield layer is on described gate insulator
Upright projection cover described active layer.
7. the preparation method of array base palte as claimed in claim 6, it is characterised in that use identical light shield formed described in have
Active layer and described light shield layer.
The preparation method of array base palte the most as claimed in claims 6 or 7, it is characterised in that described light shield layer uses black tree
Fat material.
The preparation method of array base palte the most as claimed in claims 6 or 7, it is characterised in that described active layer uses indium gallium zinc
Oxide.
10. the preparation method of array base palte as claimed in claim 6, it is characterised in that also include:
Described passivation layer forms through hole, in order to expose the described source electrode of part；
Forming pixel electrode in the side away from described source electrode of described passivation layer, described pixel electrode is connected by described through hole
To described source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610728953.9A CN106125430A (en) | 2016-08-26 | 2016-08-26 | The preparation method of array base palte, display floater and array base palte |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610728953.9A CN106125430A (en) | 2016-08-26 | 2016-08-26 | The preparation method of array base palte, display floater and array base palte |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946321A (en) * | 2017-12-12 | 2018-04-20 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display panel, display device |
| CN110112141A (en) * | 2019-04-26 | 2019-08-09 | 深圳市华星光电技术有限公司 | Micro- LED display panel and preparation method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088025A (en) * | 2009-12-02 | 2011-06-08 | 群康科技(深圳)有限公司 | Thin film transistor substrate and method of manufacturing the same |
| CN103137557A (en) * | 2013-02-05 | 2013-06-05 | 深圳市华星光电技术有限公司 | Array substrate and display unit and manufacturing method of array substrate |
| CN103261959A (en) * | 2010-12-10 | 2013-08-21 | 夏普株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
| CN104124253A (en) * | 2013-05-23 | 2014-10-29 | 深超光电（深圳）有限公司 | Thin film transistor substrate |
| CN104900657A (en) * | 2015-06-04 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate and making method thereof, display panel, and display device |
-
2016
- 2016-08-26 CN CN201610728953.9A patent/CN106125430A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088025A (en) * | 2009-12-02 | 2011-06-08 | 群康科技(深圳)有限公司 | Thin film transistor substrate and method of manufacturing the same |
| CN103261959A (en) * | 2010-12-10 | 2013-08-21 | 夏普株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device |
| CN103137557A (en) * | 2013-02-05 | 2013-06-05 | 深圳市华星光电技术有限公司 | Array substrate and display unit and manufacturing method of array substrate |
| CN104124253A (en) * | 2013-05-23 | 2014-10-29 | 深超光电（深圳）有限公司 | Thin film transistor substrate |
| CN104900657A (en) * | 2015-06-04 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate and making method thereof, display panel, and display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946321A (en) * | 2017-12-12 | 2018-04-20 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display panel, display device |
| CN107946321B (en) * | 2017-12-12 | 2022-06-28 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, display panel and display device |
| CN110112141A (en) * | 2019-04-26 | 2019-08-09 | 深圳市华星光电技术有限公司 | Micro- LED display panel and preparation method |
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