CN104112663A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104112663A CN104112663A CN201310135962.3A CN201310135962A CN104112663A CN 104112663 A CN104112663 A CN 104112663A CN 201310135962 A CN201310135962 A CN 201310135962A CN 104112663 A CN104112663 A CN 104112663A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000000407 epitaxy Methods 0.000 claims abstract description 7
- 238000000227 grinding Methods 0.000 claims description 5
- 239000003518 caustics Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 17
- 230000008901 benefit Effects 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 description 21
- 238000005516 engineering process Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000008719 thickening Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention provides a semiconductor structure and a forming method thereof. The method comprises the following steps: a substrate is provided; doping is performed on the back side of the substrate; a liner layer is formed on the back side of the substrate; a front side structure is fabricated on the front side of the substrate; the liner layer is removed and the substrate is thinned to expose the back side of the substrate; and a back side structure is fabricated on the back side of the substrate. According to the method, the diffuser substrate is preprocessed, and then the diffuser is thickened through the epitaxy or bonding method, the front side structure is fabricated and then the thickened portion is removed, and the back side structure is further fabricated so as to bypass high requirements of existing processes on the substrate, and advantages of convenience, wide application range and good flexibility can be realized.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of semiconductor structure and forming method thereof.
Background technology
Novel semi-conductor power device IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) there is the advantages such as conduction loss is low, switching speed is fast, in mesohigh high frequency field, have a wide range of applications.Conventional I GBT has PT(Punch Through, punch), NPT(Non Punch Through, non-punch), FS(Trench Field Stop, termination type) etc.
Making PT type IGBT is generally at the N-type resilient coating (N-buffer) of the heavily doped substrate of P type upper outside Yanzhong doping and low-doped N-type Withstand voltage layer (N-), because the size of device withstand voltage and the thickness of N-type Withstand voltage layer become certain proportional relationship, but the feature due to epitaxy technology, blocked up epitaxial growth is slow, cost is expensive, and along with the further growth of extension, its consistency is variation gradually also, defect showed increased, this has just determined that the epitaxial thickness of PT type is difficult to surpass more than 120um, therefore, the withstand voltage of PT type IGBT is difficult to higher than more than 1200V, be only applicable to low-pressure field, and due to thick heavy doping P district, the back side, cause back of the body note effect very strong, turn-off power loss is very large, must adopt carrier lifetime control technology, to reduce turn-off power loss, but adopt after life-span control technology, the conduction voltage drop of device becomes negative temperature coefficient, be unfavorable in parallel use, leakage current also increases.
Make the general evenly low-doped N-type substrate (N-) that adopts of NPT type IGBT, the about 600um of thickness left and right, first make Facad structure, attenuate substrate again, then form overleaf the P type doped region of shallow (less than 1um), this technology can design according to different withstand voltage ranks different attenuate residual thickness, in senior middle school, low-pressure field is all suitable for, but the feature due to NPT type technology, bearing depletion layer when withstand voltage can not exhaust Withstand voltage layer completely, therefore thickness of detector is thicker, conduction loss and turn-off power loss are all larger.
Make the general evenly low-doped N-type substrate (N-) that adopts of FS type IGBT, thickness is about 600um left and right, first carry out positive technique, attenuate substrate then, forms the N-type field stop layer of dark (approximately several um are to tens um) and the p type island region of shallow (less than 1um) overleaf.FS technology, due to the field stop layer adopting, can end electric field fall, so, bearing when withstand voltage, depletion layer can exhaust N-layer completely, compares with NPT, and the thickness after attenuate can further reduce, and conduction loss is can turn-off power loss less.The same with NPT, can extensive use in high-low pressure field.But due to the rapid cut-off of electric field, there is hidden danger in the robustness of device.
For optimizing the characteristic of above-mentioned conventional I GBT, a kind of SPT(Soft Punch Through is provided in prior art, soft break-through) technology of type, this technology adopts evenly low-doped N-type substrate, first carries out overleaf N-type diffusion, in substrate, form a dark diffusion region of N-type (diffusion sheet substrate) that concentration is gradual, at the opposite side of substrate, complete again the positive technique of IGBT, and then the attenuate back side, according to device property, retain the gradual diffusion region of certain thickness N-type, then form shallow P doped region.This technology utilizes gradual N-type diffusion region to end electric field, can make depletion layer exhaust low-doped N-type Withstand voltage layer completely, and because expanding district concentration is gradual, electric field is not rapid cut-off, has improved the robustness of device.But the method exists certain not enough: according to the feature of above-mentioned SPT technology, first be at the back side of evenly low-doped N-type substrate, to carry out the diffusion of dark N district, according to the principle of diffusion technology, when junction depth chin-deep, very difficult toward the interior diffusion impurity of substrate again, so, generally about the about 250um of this diffusion region depth capacity.And at mesolow devices field (lower than 1700V), often require the thickness of device N-type Withstand voltage layer lower than 150um, therefore, the thickness of initial substrates just must be lower than 250um+150um=400um, and wafer thickness below 400um is when making the positive technique of IGBT, very difficult, fragmentation very easily, pass through reforming equipment, can make the exercisable wafer thickness of the positive technique of IGBT drop to 360um, but, expense is very expensive, and still cannot produce for the wafer thickness below 360um, therefore, although SPT type IGBT has good characteristic, but there is application restric-tion in mesolow field.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or at least provides a kind of useful business to select.For this reason, one object of the present invention is to propose a kind of simple and easy to do, applied range, method for forming semiconductor structure that flexibility is good.Another object of the present invention is to propose that a kind of diffusion layer is thinner, doping quality better, the semiconductor structure of applied range.
Method for forming semiconductor structure according to the embodiment of the present invention, comprises the following steps: A. provides substrate; B. adulterated in the back side of described substrate; C. at the back side of described substrate, form laying; D. in the front of described substrate, make Facad structure; E. remove substrate described in described laying and attenuate, to expose the back side of described substrate; And F. makes structure at the back side of described substrate.
In one embodiment of the invention, the original depth sum of described substrate and described laying is 400-700 micron.
In one embodiment of the invention, by extension or the back side that is bonded in described substrate, form laying.
In one embodiment of the invention, during the described laying that forms by epitaxy method, the original depth of described substrate is 300-400 micron, and the thickness of described laying is less than 100 microns.
In one embodiment of the invention, during the described laying that forms by bonding method, the original depth of described substrate is 150-400 micron, and the thickness of described laying is greater than 100 microns.
In one embodiment of the invention, by grinding caustic solution, remove substrate described in described laying and attenuate.
In one embodiment of the invention, the resistivity of described substrate is 10-300 Ω/cm.
In one embodiment of the invention, the back side of described substrate is doped to dark diffusing, doping.
In one embodiment of the invention, described semiconductor structure is IGBT device.
In one embodiment of the invention, described substrate is the light dope substrate of the first doping type, and the back side of described substrate is doped to the heavy doping of the first kind.
According to the method for forming semiconductor structure of the embodiment of the present invention, anticipate diffusion sheet substrate, then the mode by extension or bonding thickens diffusion sheet, after making Facad structure, remove again the part thickening, further make structure, thereby met device to the doping of substrate and thickness requirement, had advantages of that simple and easy to do, applied range, flexibility are good.
According to the semiconductor structure of the embodiment of the present invention, this semiconductor structure is that the method for forming semiconductor structure proposing by the present invention obtains.
In one embodiment of the invention, described semiconductor structure is IGBT device.
Semiconductor structure according to the embodiment of the present invention, has diffusion layer thin, and doping quality is better, the advantage of applied range.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination obviously and is easily understood becoming the description of embodiment, wherein:
Fig. 1 is the method for forming semiconductor structure flow chart of the embodiment of the present invention;
The schematic diagram that Fig. 2 is the light dope substrate that initially provides;
Fig. 3 is the schematic diagram that carries out the substrate after the dark diffusing, doping in the back side;
Fig. 4 a-4b is the process schematic diagram of the method formation laying by extension;
Fig. 5 a-5b is the process schematic diagram of the method formation laying by bonding;
Fig. 6 makes the process schematic diagram of Facad structure in substrate face;
Fig. 7 is for removing the process schematic diagram of laying attenuate substrate;
Fig. 8 makes the process schematic diagram of structure at substrate back.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " " center ", " longitudinally ", " laterally ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of indications such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, rather than device or the element of indication or hint indication must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.
In addition, term " first ", " second " be only for describing object, and can not be interpreted as indication or hint relative importance or the implicit quantity that indicates indicated technical characterictic.Thus, one or more these features can be expressed or impliedly be comprised to the feature that is limited with " first ", " second ".In description of the invention, the implication of " a plurality of " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the terms such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and for example, can be to be fixedly connected with, and can be also to removably connect, or connect integratedly; Can be mechanical connection, can be to be also electrically connected to; Can be to be directly connected, also can indirectly be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, can understand as the case may be above-mentioned term concrete meaning in the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but contact by the other feature between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic under Second Characteristic and tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
As shown in Figure 1, method for forming semiconductor structure of the present invention comprises the steps:
A., substrate is provided.
Particularly, as shown in Figure 2, provide general substrate, for example low-doped Silicon Wafer.In some application scenario, for example, in semiconductor low voltage power devices, need final diffusion layer to get over Bao Yuehao, therefore preferred thin substrate.But be subject to the restriction of wafer cutting technique, the original depth of this substrate cannot be infinitely frivolous.Usually, the resistivity of substrate is 10-300 Ω/cm, and the resistivity of this scope means that substrate itself is lightly doped.
B. at the back side of substrate, adulterate.
Particularly, according to device needs, at substrate back, carry out the graphical or non-patterned dark diffusing, doping of particular type, certain concentration.Illustratively, low-doped N-shaped Silicon Wafer after the dark diffusing, doping of back side N-type as shown in Figure 3.
It should be noted that, when manufacturing IGBT, substrate should be the light dope substrate of the first doping type, is adulterated and should be the heavy doping of the first kind in the back side of substrate, and doping type must be identical.
C. at the back side of substrate, form laying.
Particularly, by extension or the back side that is bonded in substrate, form laying.The effect of laying is to increase substrate thickness, so that be unlikely to thin and cracked in follow-up positive technical process.This laying will be removed in subsequent technique, not affect device property, and just to strengthening wafer intensity, therefore the quality such as whether this laying adulterates, defect do not require, only required thickness satisfies the demands.Usually, the original depth sum of substrate and laying should be greater than 400 microns of ability and effectively avoid fragmentation, and side by side, because of production line requirement, the original depth sum of substrate and laying should be less than 700 microns.
By epitaxy method, form the process of laying as shown in Fig. 4 a-Fig. 4 b.Due to epitaxy technique, epitaxy layer thickness is 100 microns of convenient realizations when following, and therefore, the original depth that this scheme is applicable to substrate is the situation that the thickness of 300-400 micron, laying is less than 100 microns.
By bonding method, form the process of laying as shown in Fig. 5 a-Fig. 5 b.Due to bonding technology, more easily operation when bonded layer thickness is thicker, therefore, the original depth that this scheme is applicable to substrate is the situation that the thickness of 150-400 micron, laying is greater than 100 microns.
It should be noted that, it is same material that laying does not limit with substrate, as long as Lattice Matching can extension, in other words can bonding, and can be also heterogeneous material.
D. in the front of substrate, make Facad structure.
Particularly, after completing substrate thickening, in a relative side (positive) of substrate thickening, complete the processing of Facad structure.Manufacture craft generally adopts already known processes, but the technique that different semiconductor device adopts difference to some extent, and the structure of producing is also not quite similar.
E. remove laying and attenuate substrate, to expose the back side of substrate.
Particularly, at the device back side, by grinding caustic solution, remove laying and attenuate substrate, until the needed target thickness of device, and expose the back side of substrate so that carry out back process.
F. at the back side of substrate, make structure.
Particularly, at the device back side, further complete the processing of structure, form final completed device.This process also adopts conventional semiconductor technology, does not repeat herein.
According to the method for forming semiconductor structure of the embodiment of the present invention, anticipate diffusion sheet substrate, then the mode by extension or bonding thickens diffusion sheet, after making Facad structure, remove again the part thickening, further make structure, thereby met device to the doping of substrate and thickness requirement, had advantages of that simple and easy to do, applied range, flexibility are good.
The present invention also proposes a kind of semiconductor structure, and this semiconductor structure is that the method for forming semiconductor structure by above narrating obtains, and it is thin that it has diffusion layer, and doping quality is better, the advantage of applied range.
For making those skilled in the art understand better the present invention, applicant be take IGBT device as example, introduces in detail the formation method of semiconductor structure of the present invention.Method by long extension or bonding in this embodiment increases the thickness of diffusion sheet, thereby makes the original diffusion sheet thickness of low-voltage device make to reach the requirement that product line is processed initial wafer thickness, can break through existing SPT type technology in the restriction of mesolow field IGBT.Its concrete steps are as follows:
(1) provide for example, even low-doped N-type silicon substrate thinner (: lower than 400 microns).
(2) according to the requirement of made device electrology characteristic, adopt known technology from the back side of this substrate, to carry out the methods such as the dark diffusion of high concentration N-type, complete device substrate and make.Wherein, diffusion junction depth is determined according to the voltage withstand class of device.
(3) carry out overleaf extension or bonding technology, increase silicon liner layer, substrate thickness (being the thickness sum of substrate and laying) is increased to 400-700 micron.Wherein: the technique of extension is hydrogen (H
2) carry silicon tetrachloride (SiCl
4), trichlorosilane (SiHCl
3), dichloro hydrogen silicon (SiH
2cl
2) or silane (SiH
4) enter the reative cell that is equipped with silicon substrate, at reative cell, carry out high-temperature chemical reaction, make siliceous reacting gas reduction or thermal decomposition, the silicon atom producing epitaxial growth on substrate silicon surface; The technique of bonding be by the homogeneity of two surface cleaning, atomically flating or heterogeneous semiconductor material through surface clean and activation processing, directly combination under the conditions such as HTHP, by Van der Waals force, molecular force even atomic force bonding chip is become one.
(4) complete the positive technique of device, produce Facad structure metal level, control electrode as shown in Figure 6.
(5) the attenuate back side, by epitaxial loayer or bonded layer and partly or entirely n type diffused layer removal, as shown in Figure 7.Wherein, grinding refers to Silicon Wafer is positioned between the abrasive disk of grinder, by the lapping liquid with specified particle size and viscosity formula, by mutual rotation of abrasive disk, reaches grinding object; Corrosion typically refers to and adopts corrosive liquid to process wafer surface, chemical reaction occurs and erosion removal.The comprehensive efficiency of thinning process and the quality of attenuate rear surface, the order that post-etching is first ground in general employing.
(6) complete device back process, produce structure P type layer, back electrode etc., as shown in Figure 8.
It should be noted that, although the present invention draws for solving IGBT the deficiencies in the prior art, but not only for IGBT, use, because SPT technology also exists advantage on other power devices, resilient coating feature as gradual in SPT can make diode have better soft recovery characteristics, so method of the present invention also can be used on as other power device manufacture methods such as diodes, its difference is only that positive technique and the back process of said process is variant, but integral manufacturing flow and method is just the same, therefore also belong to content of the present invention.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, modification, replacement and modification.
Claims (12)
1. a method for forming semiconductor structure, is characterized in that, comprises the following steps:
A., substrate is provided;
B. adulterated in the back side of described substrate;
C. at the back side of described substrate, form laying;
D. in the front of described substrate, make Facad structure;
E. remove substrate described in described laying and attenuate, to expose the back side of described substrate; And
F. at the back side of described substrate, make structure.
2. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the original depth sum of described substrate and described laying is 400-700 micron.
3. method for forming semiconductor structure as claimed in claim 1, is characterized in that, by extension or the back side that is bonded in described substrate, forms laying.
4. method for forming semiconductor structure as claimed in claim 3, is characterized in that, during the described laying that forms by epitaxy method, the original depth of described substrate is 300-400 micron, and the thickness of described laying is less than 100 microns.
5. method for forming semiconductor structure as claimed in claim 3, is characterized in that, during the described laying that forms by bonding method, the original depth of described substrate is 150-400 micron, and the thickness of described laying is greater than 100 microns.
6. method for forming semiconductor structure as claimed in claim 1, is characterized in that, by grinding caustic solution, removes substrate described in described laying and attenuate.
7. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the resistivity of described substrate is 10-300 Ω/cm.
8. method for forming semiconductor structure as claimed in claim 1, is characterized in that, the back side of described substrate is doped to dark diffusing, doping.
9. the method for forming semiconductor structure as described in claim 1-8 any one, is characterized in that, described semiconductor structure is IGBT device.
10. method for forming semiconductor structure as claimed in claim 9, is characterized in that, described substrate is the light dope substrate of the first doping type, and the back side of described substrate is doped to the heavy doping of the first kind.
11. 1 kinds of semiconductor structures, is characterized in that, described semiconductor structure is to obtain by the method for forming semiconductor structure described in claim 1-10 any one.
12. semiconductor structures as claimed in claim 9, is characterized in that, described semiconductor structure is IGBT device.
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| CN201310135962.3A CN104112663A (en) | 2013-04-18 | 2013-04-18 | Semiconductor structure and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451399A (en) * | 2021-06-02 | 2021-09-28 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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| JP2002261281A (en) * | 2001-03-01 | 2002-09-13 | Hitachi Ltd | Manufacturing method of insulated gate bipolar transistor |
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| JP2011165771A (en) * | 2010-02-05 | 2011-08-25 | Fuji Electric Co Ltd | Method of manufacturing semiconductor device |
| CN102054690A (en) * | 2010-11-22 | 2011-05-11 | 复旦大学 | Manufacturing method of semiconductor substrate of high-power device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451399A (en) * | 2021-06-02 | 2021-09-28 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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