JP5999687B2 - SiC epitaxial wafer and SiC semiconductor device using the same - Google Patents

Description

  The present invention relates to a SiC epitaxial wafer having a predetermined off angle and a SiC semiconductor device using the same.

In recent years, SiC (silicon carbide: silicon carbide) semiconductors that can achieve higher breakdown voltage, higher current, lower on-resistance, higher efficiency, lower power consumption, higher speed switching, and the like than Si semiconductors have attracted attention.
A SiC semiconductor usually has a predetermined off angle from the (0001) plane when it is cut out from a SiC ingot. The cut wafer is subjected to processing such as polishing, and is used in the state of an epitaxial wafer in which an epitaxial layer is formed on the processed surface. In the growth process of the SiC epitaxial layer, crystal nuclei for growth are generated on the surface composed of an atomic step caused by an off angle and an atomic flat surface called a terrace. Crystal nuclei diffuse on the terrace by thermodynamic energy and stabilize at the step edge. Such a growth mechanism is called a step flow. Ideally, since the growth is performed while maintaining the terrace width at the initial stage of growth, the step of the height of one SiC molecule layer is similarly maintained. Thermodynamic factors such as the temperature and the atmosphere during growth affect the crystal nuclei so that the diffusion rate of the crystal nuclei becomes nonuniform and the terrace width becomes nonuniform. Where the terrace width is narrowed, the steps gather together to form a bundle (hereinafter referred to as step bunching), which is at least as high as two SiC molecules.

  The epi-wafer surface is also an operation region of the device and becomes an interface such as an electrode or an oxide film. For this reason, step bunching, which is unevenness on the surface, affects the operation of the device, increases the reverse leakage current at the interface with the Schottky electrode, and reduces the reliability at the interface with the oxide film. Similarly, the leakage current increases at the pn junction interface, and the surface recombination increases at the bipolar operation region formed by ion implantation. Similarly, Non-Patent Document 1 reports that basal plane dislocation (BPD: Basal Plane Dislocation) existing in a SiC epitaxial layer also affects device characteristics.

Therefore, in Non-Patent Document 1, in order to reduce the BPD density of the SiC epitaxial layer, the main surface of the SiC substrate is etched using molten KOH at 500 ° C. or higher before the SiC epitaxial growth, thereby etching the main surface. A method for forming a pit has been proposed.
On the other hand, in Non-Patent Document 2, the step bunching linear density on the surface of the SiC epitaxial wafer is the temperature at the time of forming the SiC epitaxial layer and the C / Si ratio (supply ratio of C (carbon) to Si (silicon)). It is reported that step bunching can be prevented if the C / Si ratio is 0.5 or less.

J. J. Sumakeris, et al. Material Science Forum Vol.457-460 (2004) p.1113-1116 Keiji Wada, et al. Journal of Crystal Growth 291 (2006) pp.370-374 James A. Cooper, JR., Anant Agarwal, Proceedings of the IEEE Vol.90, No.6 (2002) pp.956-968

  However, it is difficult to control the process of forming the etch pits on the SiC substrate. For example, if the temperature of the molten KOH differs by 10 ° C., the size of the etch pits will change greatly. Further, dislocations other than BPD, for example, etch pits of threading screw dislocation (TSD) and threading edge dislocation (TED) appear by etching using molten KOH. Unevenness on the main surface becomes a size of several μm or more. As a result, the surface unevenness after the formation of the SiC epitaxial layer also increases. Therefore, processing for planarizing the surface of the SiC epitaxial layer is necessary before forming a device in the SiC epitaxial layer, but the surface of the SiC epitaxial layer is damaged during the planarization processing.

On the other hand, when SiC is epitaxially grown on the Si surface (0001) surface of the SiC substrate, the residual electron concentration in the SiC epitaxial layer is preferably made as small as possible from the viewpoint of manufacturing a high breakdown voltage and high reliability device. In order to reduce the residual electron concentration, it is preferable to increase the C / Si ratio during epitaxial growth, but there is a problem that the linear density of step bunching generated on the surface of the SiC epitaxial layer increases. For example, when the C / Si ratio = 0.5, the step bunching linear density is 500 cm ⁻¹ , whereas when the C / Si ratio = 1.5, the step bunching linear density is 6000 cm ⁻¹ . As the C / Si ratio increases, the linear density of step bunching increases.

  An object of the present invention is to provide a SiC epitaxial wafer capable of producing a high-quality and high-reliability element, and a SiC semiconductor element obtained using the SiC epitaxial wafer.

In order to achieve the above object, an SiC epitaxial wafer of the present invention is formed on an SiC substrate having an off angle of 4 ° or less and a main surface of the SiC substrate, and step bunching having a height of 0.5 nm or more on the surface. The step bunching has a linear density of 40 cm ⁻¹ or less.
Various SiC semiconductor devices such as Schottky barrier diodes, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), BJTs (Bipolar Transistors), pn diodes, thyristors, IGBTs (Insulated gate bipolar transistors) manufactured using this SiC epitaxial wafer Even when the step is operated, since the step bunching linear density is 40 cm ⁻¹ or less, the defect region on the surface or interface of the SiC epitaxial layer can be reduced. As a result, it is effective in reducing element leakage current, non-uniformity of oxide film thickness, interface state, surface recombination, etc., and improving field effect mobility, so high quality and high reliability SiC semiconductor element Can be provided.

In addition, it is more preferable that the linear density of the step bunching is 5 cm ⁻¹ .
Further, the main surface of the SiC substrate may be a surface inclined at an off angle of 4 ° or less in the [11-20] axial direction with respect to the (0001) plane, or with respect to the (0001) plane. The surface may be inclined at an off angle of 4 ° or less in the [−1100] axial direction.
Further, the main surface of the SiC substrate is subjected to polishing (mainly CMP) after mechanical processing such as grinding or lapping of the cut surface of the SiC bare wafer cut out from the SiC ingot at an off angle of 4 ° or less. The amount of scraping by plasma etching is preferably 500 nm or more.

That is, after the SiC bare wafer is machined, the amount of scraping by CMP or plasma etching is set to 500 nm or more, whereby the damaged layer on the surface of the SiC bare wafer generated by machining can be sufficiently removed and the surface can be flattened. As a result, even if epitaxial growth is performed on the SiC bare wafer, the linear density of step bunching on the surface of the SiC epitaxial layer can be reduced to 40 cm ⁻¹ or less.

More preferably, the cut surface of the SiC bare wafer is formed by a dry oxidation method or a wet oxidation method before the machining and / or after the machining, before the polishing and / or after the polishing, before the plasma etching and / or after the plasma etching. Has been processed.
As a result, basal plane dislocation pits can be formed in an appropriate size on the main surface of the SiC substrate. Therefore, the basal plane dislocation density (BPD density) of the SiC epitaxial layer of the SiC wafer can be reduced. For example, basal plane dislocations propagate from the SiC bare wafer to the epitaxial layer during epitaxial growth, but if pits of an appropriate size are formed at the location of the basal plane dislocations, the basal plane dislocations are not in the off-angle direction. Can no longer propagate, and the basal plane dislocation density of the SiC epitaxial layer can be made 10 cm ⁻² or less. As a result, it is effective in device characteristics, for example, on-resistance reduction and suppression of forward voltage increase in bipolar operations such as pn diodes.

  Furthermore, when oxidation is performed after polishing or after plasma etching, a damaged layer on the surface of the SiC bare wafer that cannot be removed by polishing or plasma etching, or a damaged layer (damaged layer) generated during polishing or plasma etching is surely obtained. Can be removed. Therefore, generation of step bunching on the surface of the SiC epitaxial layer can be further reduced.

The SiC substrate is preferably made of 4H—SiC, and the main surface of the SiC substrate is preferably an Si surface. If the main surface is a Si surface, the residual electron concentration after growth can be kept low even if SiC is crystal-grown at the same C / Si ratio.
Moreover, it is preferable that the said SiC epitaxial layer consists of 4H-SiC, and it is preferable that the nitrogen concentration is 5 * 10 < ¹⁶ > cm < ^-3 > or less.

Moreover, it is preferable that the thickness of the said SiC epitaxial layer is 3 micrometers or more, and it is further more preferable that they are 4 micrometers-100 micrometers. In general, the breakdown voltage of a semiconductor element is proportional to the thickness of the layer that holds the breakdown voltage. In the case of a SiC semiconductor element, the breakdown voltage of 300 V to 10 kV is ensured by setting the thickness of the SiC epitaxial layer within this range. Can do.
The SiC semiconductor element of the present invention is formed using the above-described SiC epitaxial wafer of the present invention. For this reason, there are effects such as reduction in leakage current, improvement in field-effect mobility, and increase in current amplification factor due to a decrease in defect density on the surface of the SiC epitaxial layer, and the device is extremely high quality and highly reliable.

FIG. 1 is a schematic view of a SiC epitaxial wafer according to an embodiment of the present invention. FIG. 2 is a correlation diagram between the thickness and the carrier concentration in the SiC epitaxial layer. FIG. 3 is a correlation diagram between the thickness and the on-resistance in the SiC epitaxial layer. FIG. 4 is a schematic diagram showing a unit cell having a crystal structure of 4H—SiC. FIG. 5 is a view of the unit cell of FIG. 4 as viewed from directly above the (0001) plane. 6A and 6B are enlarged views of main parts of the SiC epitaxial wafer of FIG. 1, FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view. The cross section at the cutting line AA is shown. FIG. 7 is a graph showing the relationship between the off-angle of the SiC substrate and the step growth width. FIGS. 8A and 8B are diagrams for explaining the linear density of step bunching. FIG. 9 is a diagram illustrating a correspondence relationship between step bunching and basal plane dislocations. FIG. 10 is a diagram showing a manufacturing process of the SiC epitaxial wafer of FIG. 1 in the order of steps. FIG. 11 is a diagram for explaining how much the BPD on the epi surface changes depending on the presence or absence of oxidation treatment before SiC epitaxial growth. FIG. 12 is a graph showing the relationship between C / Si ratio and step bunching linear density in the prior art and the present invention. FIG. 13 is a graph showing the relationship between the C / Si ratio and the residual electron concentration in the SiC epitaxial layer formed on each of the Si plane and the C plane. FIG. 14 is a schematic cross-sectional view of a Schottky barrier diode fabricated using the SiC epitaxial wafer of FIG. FIG. 15 is a schematic cross-sectional view of a trench gate type MOSFET fabricated using the SiC epitaxial wafer of FIG. FIG. 16 is a schematic cross-sectional view of a planar gate type MOSFET fabricated using the SiC epitaxial wafer of FIG. 17 (a) and 17 (b) are views showing modifications of the off-angle of the SiC substrate, in which FIG. 17 (a) is a plan view, FIG. 17 (b) is a cross-sectional view, and FIG. ) Is a cross section taken along a cutting line DD.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic view of a SiC epitaxial wafer according to an embodiment of the present invention. FIG. 2 is a correlation diagram between the thickness and the carrier concentration in the SiC epitaxial layer. FIG. 3 is a correlation diagram between the thickness and the on-resistance in the SiC epitaxial layer.
The SiC epitaxial wafer 1 is made of 4H—SiC, and includes a SiC substrate 2 and a SiC epitaxial layer 3 stacked on the SiC substrate 2. The thickness t ₁ of the SiC substrate 2 is, for example, 200 μm to 500 μm, and the thickness t ₂ of the SiC epitaxial layer 3 is thinner than the SiC substrate 2, for example, 5 μm or more, preferably 4 μm to 100 μm. Moreover, the nitrogen concentration of SiC epitaxial layer 3 is, for example, 5 × 10 ¹⁶ cm ⁻³ or less. By setting the thickness and the nitrogen concentration of the SiC epitaxial layer 3 within this range, a breakdown voltage of 300 V to 10 kV can be secured as shown in FIG.

FIG. 2 is a correlation diagram between the thickness and the carrier concentration in the SiC epitaxial layer 3. In FIG. 2, six axes obtained by connecting plots of mutually equal breakdown voltage _Vb to the XY plane where the X axis is the thickness W of the SiC epitaxial layer 3 and the Y axis is the carrier concentration N _D of the SiC epitaxial layer 3 are obtained. Isovoltage lines (600V, 900V, 1200V, 3300V, 6600V and 10kV) are shown. For reference, an isovoltage line of a Si device having a withstand voltage of 600 V is also shown.

The coordinates of each plot (withstand voltage V _b ) constituting the isovoltage line of FIG. 2 were obtained by the following formula (1).

  Further, the respective guidelines for SiC and Si in FIG. 2 were obtained by the following formula (2).

In the above formulas (1) to (2), each quantity symbol expresses the following.
_Eb : dielectric breakdown electric field Si is 3 × 10 ⁵ V / m, SiC is 3 × 10 ⁶ V / m
Q: Elementary charge = 1.6 × 10 ⁻¹⁹ C
N _D : carrier concentration W: epitaxial layer thickness ε ₀ : vacuum dielectric constant = 8.85 × 10 ⁻¹² F / m
Ε _s : relative permittivity 11.8 for Si, 9.7 for SiC
The carrier concentration N _D, the case of n-type SiC, since a carrier concentration ≒ nitrogen concentration was the nitrogen concentration of the SiC epitaxial layer 3 and the carrier concentration. The nitrogen concentration of SiC epitaxial layer 3 can be adjusted by epitaxial growth conditions. For example, the nitrogen concentration (carrier concentration) can be increased by increasing the ratio of the nitrogen flow rate to the SiH ₄ flow rate during epitaxial growth.

FIG. 3 shows a correlation between the thickness and the on-resistance in the SiC epitaxial layer 3.
In FIG. 3, the X axis is the thickness W of the SiC epitaxial layer 3, and the Y axis is six equals obtained by connecting plots of the same breakdown voltage V _b to the XY plane having the on-resistance SR of the SiC epitaxial layer 3. The breakdown lines (600V, 900V, 1200V, 3300V, 6600V and 10kV) are shown. For reference, an isovoltage line of a Si device having a withstand voltage of 600 V is also shown.

  In FIG. 3, the on-resistance SR was obtained by the following formula (3).

In the above formula (3), each quantity symbol expresses the following.
Q: Elementary charge = 1.6 × 10 ⁻¹⁹ C
· _{N D:} Carrier Concentration · W: epitaxial layer thickness · mu: Mobility Si in ^{1.4 × 10 3 cm 2 V -1} s -1, the SiC 900cm ² V ^-1 s ^-1
Note that SiC is a material exhibiting crystal polymorphism (polytype) having the same composition and various laminated structures, and there are several hundred or more polytypes. In this embodiment, the SiC epitaxial wafer 1 is not limited to 4H—SiC, and may be 3C—SiC, 2H—SiC, 6H—SiC, 15R—SiC, or the like. Among these, hexagonal SiC such as 6H—SiC is preferable.

In this embodiment, SiC substrate 2 has an off angle of 4 ° or less. Specifically, the main surface 4 (substrate surface) of the SiC substrate 2 is a surface inclined with an off angle of 4 ° or less in the [11-20] axial direction with respect to the (0001) plane.
Expressions such as (0001) and [11-20] are so-called Miller indices, and are used to describe the lattice plane and lattice direction of the SiC crystal. The Miller index can be described with reference to FIGS.

FIG. 4 is a schematic diagram showing a unit cell having a crystal structure of 4H—SiC. FIG. 5 is a view of the unit cell of FIG. 4 as viewed from directly above the (0001) plane. In the perspective view of the SiC crystal structure shown in the lower part of FIG. 4, only two layers are extracted from the four layers of the SiC laminated structure shown on the side.
As shown in FIG. 4, the crystal structure of 4H—SiC can be approximated by a hexagonal system, and four carbon atoms are bonded to one silicon atom. Four carbon atoms are located at four vertices of a regular tetrahedron having a silicon atom arranged at the center. Of these four carbon atoms, one silicon atom is located in the [0001] axis direction with respect to the carbon atom, and the other three carbon atoms are located on the [000-1] axis side with respect to the silicon atom. Yes.

The [0001] axis and the [000-1] axis are along the axial direction of the hexagonal column, and the plane (the top surface of the hexagonal column) having the [0001] axis as a normal line is the (0001) plane (Si plane). On the other hand, the surface (the lower surface of the hexagonal column) whose normal is the [000-1] axis is the (000-1) surface (C surface).
Further, the directions passing through the apexes that are not adjacent to each other of the hexagonal column when viewed from directly above the (0001) plane and the [0001] axis are a ₁ axis [2-1-10], a _Two axes [-12-10] and a _three axes [-1-120].

As shown in FIG. 5, a direction [11-20] axis passing through the vertex between _{a 1-axis} and _{a 2-axis,} the direction passing through the vertex between _{a 2} axis and _{a 3} axis [- 2110] an axial direction passing through the vertex between _{a 3} axis and _{a 1-axis} is [1-210] axis.
Between each of the six axes passing through the respective apexes of the hexagonal column, the axis which is inclined at an angle of 30 ° with respect to the respective axes on both sides thereof, and which is a normal line of each side surface of the hexagonal column, [10-10] axis, [1-100] axis, [0-110] axis, [-1010] axis, [-1100] axis in order clockwise from between the ₁ axis and the [11-20] axis. And the [01-10] axis. Each plane (side surface of the hexagonal column) having these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

The main surface 4 of the SiC substrate 2 is a surface inclined at an off angle θ of 4 ° or less in the [11-20] axial direction with respect to the (0001) plane, as shown in FIGS. 6 (a) and 6 (b). It has become.
6A and 6B are enlarged views of main parts of the SiC epitaxial wafer of FIG. 1, FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view. The cross section at the cutting line AA is shown. FIG. 7 is a graph showing the relationship between the off-angle of the SiC substrate and the step growth width.

  As shown in FIG. 6B, the main surface 4 of the SiC substrate 2 has a normal n direction that does not coincide with the [0001] axis direction, and [11-20] with respect to the (0001) plane. Inclined at an off angle θ of 4 ° or less in the off direction of the shaft. As shown in FIG. 4, the off direction refers to a direction in which the normal line n of the SiC substrate 2 is inclined with respect to the [0001] axis, and the normal line n is projected (projected) from the [0001] axis onto the (0001) plane. It is indicated by the direction of the vector. That is, in this embodiment, the direction of the projection vector of the normal line n coincides with the [11-20] axis.

  Thereby, the SiC substrate 2 includes a flat terrace surface 5 constituted by the (0001) plane and a stepped portion of the terrace surface 5 caused by the main surface 4 being inclined with respect to the (0001) plane (off-angle θ). The step portion has a step surface 6 which is a (11-20) plane perpendicular to the [11-20] axis. The height of the step portion (step height h) corresponds to a layer 7 (bi-layer) of a Si—C pair in which carbon atoms are bonded on one silicon atom, and is 0.25 nm.

  As shown in FIG. 6A, the step surfaces 6 of each layer 7 are regularly arranged while maintaining the width of the terrace surface 5 in the [11-20] axial direction. Further, the step line 8 serving as the step edge of the step surface 6 maintains the vertical relationship with the [11-20] axial direction (in other words, maintains the parallel relationship with the [-1100] axial direction) and the terrace surface. It is arranged in parallel while taking the width of 5.

The SiC epitaxial layer 3 is formed by crystal growth of each layer 7 in the lateral direction along the [11-20] axial direction while maintaining the terrace surface 5 and the step surface 6 of the SiC substrate 2. The width in the growth direction of each layer 7 (step growth width s) can be expressed by t ₂ / sin θ using the thickness t ₂ of the SiC epitaxial layer 3. Further, the width (step advance width L) in the growth direction of each layer 7 on the surface 10 (epi surface) of the SiC epitaxial layer 3 can be expressed by t ₂ / tan θ. Further, the step growth width s is substantially the same as the step progress width L because the off-angle θ is as small as 4 ° or less. When the unit of the angle is radians, t ₂ / sin θ≈t ₂ / tan θ≈t ₂ / θ. The step growth width s increases with the thickness t ₂ of the SiC epitaxial layer 3. For example, when t ₂ = 1 μm, the preferred step growth width s is 10 μm to 100 μm.

  Moreover, the off angle θ of the SiC substrate 2 is preferably 0.5 ° to 4 °, more preferably 1 ° to 4 °. If the off angle θ is within this range, the step growth width s can be made substantially constant, so that the controllability during mass production of the SiC epitaxial wafer 1 can be improved. For example, as shown in FIG. 7, when the SiC epitaxial layer 3 having a thickness of 1 μm is grown, if the off-angle is 0.5 ° to 4 °, the step growth width s may be within the range of 20 μm to 100 μm. it can.

  On the other hand, in the growth process of the SiC epitaxial layer 3, step bunching 9 occurs because each layer 7 (atomic layer) grows in the lateral direction. Step bunching 9 is formed by integrating two or more layers 7 (atomic layers) on the surface 10 of the SiC epitaxial layer 3 as shown in FIG. This means that the step surface 6 having the step height h is formed. Therefore, in this embodiment, the step bunching 9 is formed along the step line 8 (that is, parallel to the direction perpendicular to the [11-20] axial direction).

Also in this embodiment, the step bunching 9 is formed on the surface 10 of the SiC epitaxial layer 3, but its linear density is 40 cm ⁻¹ or less, which is much smaller than the conventional one. The linear density of the step bunching 9 can be measured as shown in FIGS. 8 (a) and 8 (b), for example.
FIGS. 8A and 8B are diagrams for explaining the linear density of step bunching.

The linear density of the step bunching 9 can be measured using, for example, an AFM (Atomic Force Microscope). Here, in the measurement of the line density of the step bunching 9, it is possible to measure with high reliability by measuring about 10 step bunchings 9. Then, in order to measure 10 step bunchings 9 on a wafer having a linear density of 40 cm ⁻¹ using AFM (x = 0.1 mm as the maximum imaging range), 10/40 cm ⁻¹ = 0.25 cm = 2.5 mm. The width of is required. That is, in the case of an image of x = 0.1 mm, 25 images are necessary. Therefore, in the measurement using the AFM, it is preferable to perform the measurement so as to cross the wafer in the lateral direction as shown in FIG. For example, when the step bunching 9 of a 6 inch = 150 mm wafer is measured using AFM (maximum imaging range x = 0.1 mm), the measurement lower limit value is 1 if the wafer has only one step bunching. Since / 15 cm = 0.0666..., 0.1 cm ⁻¹ is obtained.

  Such step bunching 9 corresponds to the position of a basal plane dislocation (BPD: Basal Plane Dislocation) 11 propagated from the SiC substrate 2 to the SiC epitaxial layer 3 during crystal growth as shown in FIG. 6B. Exist. That is, since step bunching 9 is likely to occur where basal plane dislocations 11 are present, in order to reduce step bunching 9, main surface 4 of SiC substrate 2 must be a smooth surface on which no large irregularities are formed. However, it is also important that the density (BPD density) of the basal plane dislocations 11 in the SiC epitaxial layer 3 is small. If the BPD density of the SiC epitaxial layer 3 can be reduced, the generation location of the step bunching 9 can be reduced, the linear density can be reduced, and the basal plane dislocation 11 itself can be reduced, so that the leakage current of the element can be further reduced.

The basal plane dislocation 11 indicates a dislocation parallel to the basal plane (0001) plane of the SiC substrate 2 and the SiC epitaxial layer 3.
The correspondence relationship between the step bunching 9 and the basal plane dislocation 11 is, for example, as shown in FIG. 9, in which the surface 10 of the SiC epitaxial layer 3 is wet-etched with molten KOH (potassium hydroxide) to form etch pits 12. It can be proved by confirming that the etch pit 12 is formed on the line of the step bunching 9.

If such etch pits are formed by etching the main surface 4 of the SiC substrate 2 using molten KOH at 500 ° C. or higher before the SiC epitaxial growth, the SiC pit 2 propagates from the SiC substrate 2 to the SiC epitaxial layer 3. Non-Patent Document 1 discloses that the BPD density to be reduced can be reduced.
However, it is difficult to control the process of forming the etch pits on the SiC substrate 2. For example, if the temperature of the molten KOH differs by 10 ° C., the size of the etch pits will change greatly. Further, by etching using molten KOH, dislocations other than basal plane dislocations, for example, etch pits of threading screw dislocation (TSD) and threading edge dislocation (TED) appear, so SiC. The unevenness of the main surface 4 of the substrate 2 becomes a size of several μm or more. As a result, the surface unevenness after the formation of the SiC epitaxial layer 3 also increases. Therefore, processing for planarizing the surface 10 of the SiC epitaxial layer 3 is necessary before forming a device in the SiC epitaxial layer 3, but the surface 10 of the SiC epitaxial layer 3 is damaged during the planarization processing. Will be given.

Therefore, in this embodiment, as will be described later, the main surface 4 of the SiC substrate 2 is oxidized by a dry oxidation method or a wet oxidation method before the growth of the SiC epitaxial layer 3. Thereby, the pits of the basal plane dislocations 11 can be formed in an appropriate size on the main surface 4 of the SiC substrate 2 while preventing the appearance of dislocation etch pits other than the basal plane dislocations 11.
Next, with reference to FIG. 10, the manufacturing method of a SiC epitaxial wafer is demonstrated concretely.

FIG. 10 is a diagram showing a manufacturing process of the SiC epitaxial wafer of FIG. 1 in the order of steps.
First, as shown in FIG. 10A, a hexagonal SiC ingot 13 is prepared. Next, the SiC ingot 13 is cut out with an off angle θ of 4 ° or less in the [11-20] axial direction with respect to the (0001) plane, thereby obtaining a plurality of SiC bare wafers 14. Next, the cut surface 15 ((0001) surface) of the SiC bare wafer 14 is polished by mechanical processing such as lapping.

After machining, as shown in FIG. 10B, the cut surface 15 ((0001) surface) of the SiC bare wafer 14 is removed by 500 nm or more. The removal method can be performed by, for example, CMP (Chemical Mechanical Polishing) or plasma etching, but is preferably performed by plasma etching. The conditions of each process are as follows.
<CMP conditions>
Polishing rate: 0.01 nm / h to 0.5 nm / h, preferably 0.1 nm / h
<Etching Conditions ICP (Inductively Coupled Plasma)>
-Pressure: 200 Pa to 400 Pa, preferably 400 Pa
Source gas (flow rate): Ar or O ₂ 30 sccm and CF ₄ 60 sccm, or Cl ₂ alone 100 sccm
RF power: 100W to 1000W, preferably 500W
-Substrate bias: 10 W to 100 W, preferably 50 W
Etching rate: 10 nm / min to 200 nm / min, preferably 50 nm / min
The reason why plasma etching is preferable is that SiC is a very hard material, so that it takes several hours to remove 500 nm or more by CMP with less damage, but plasma etching requires a short time of about 20 minutes. On the other hand, the damage received by the cut surface 15 of the SiC bare wafer 14 may be greatly damaged by a material softer than SiC such as Si. However, since SiC is very hard, damage caused by plasma etching can be reduced. It doesn't matter.

By this removal of 500 nm or more, the damaged layer on the cut surface 15 of the SiC bare wafer 14 generated by the machining after the cut is sufficiently removed, and the SiC substrate 2 having a thickness t ₁ of 200 μm to 500 μm is obtained.
For example, when the removal is performed by CMP, before the formation of the SiC epitaxial layer 3 after the removal, a surface cleaning process for removing particles generated by the CMP and a drying for drying the cleaning liquid used in the surface cleaning process. It is preferable to perform the process. This is because particles generated by CMP cause bunching of steps on the surface 10 of the SiC epitaxial layer 3.

In the surface cleaning process, megasonic cleaning can be used. Preferably, the main surface 4 of the SiC substrate 2 is megasonic cleaned using functional water (ozone water, hydrogen water, etc.). The particles may be removed not only by megasonic cleaning but also by jet cleaning or scrubber cleaning.
In the drying step, as the SiC substrate 2 dries, particles may adhere again to the main surface 4, so that it is preferable to use an ionizer or ionized air. Thereby, generation | occurrence | production of the step bunching 9 in the SiC epitaxial layer 3 can be suppressed reliably.

Next, as shown in FIG. 10C, an oxide film 16 is formed on the main surface 4 of the SiC substrate 2 by oxidizing the main surface 4 (0001) surface of the SiC substrate 2. The oxidation treatment may be performed by either a dry oxidation method or a wet oxidation method. The conditions for the oxidation treatment are, for example, as follows. Although not shown, the oxide film 16 is also formed on the back surface and the peripheral surface of the SiC substrate 2.
<Oxidation conditions>
Oxidation temperature: 1000 ° C to 1400 ° C, preferably 1100 ° C to 1300 ° C
Atmosphere: O ₂ , NO, N ₂ O, NO ₂ , Air and H ₂ O, preferably O ₂ , NO, N ₂ O, NO ₂
Oxidation time: 2h to 48h, preferably 8h
Oxide film thickness: 10 nm to 2000 nm, preferably 20 nm to 80 nm, more preferably 40 nm by dry oxidation method
Thereafter, the oxide film 16 is removed using hydrofluoric acid (HF).

  By performing the formation process and the removal process of the oxide film 16, a damaged layer on the cut surface 15 of the SiC bare wafer 14 that could not be removed by CMP or plasma etching, or an altered layer (damage layer) generated during CMP or plasma etching. ) Can be reliably removed. Further, pits of the basal plane dislocations 11 can be formed in an appropriate size on the main surface 4 of the SiC substrate 2.

The formation process and the removal process of the oxide film 16 may be performed not only after the removal process of 500 nm or more, but also before the removal process, or both before and after the removal process.
Next, as shown in FIG. 10D, the SiC epitaxial layer 3 is crystal-grown on the SiC substrate 2. The conditions for crystal growth are, for example, as follows.
<Formation conditions of SiC epitaxial layer>
Growth temperature: 1600 ° C to 1700 ° C
・ Pressure: 10 kPa to 15 kPa
・ H ₂ flow rate: 100 slm to 200 slm
Source gas: SiH ₄ , C ₃ H ₈ , N ₂
Growth rate: 1 μm / h to 20 μm / h
C / Si supply ratio: 1.0 to 10.0, preferably 1.3 to 2.0
By growing the SiC epitaxial layer 3, the SiC epitaxial wafer 1 of FIG. 1 can be obtained.

In the SiC epitaxial wafer 1 thus obtained, the linear density of the step bunching 9 (see FIG. 6) can be made 40 cm ⁻¹ or less. This is because, before crystal growth of the SiC epitaxial layer 3, the cut surface 15 of the SiC bare wafer 14 is removed by 500 nm or more by CMP or plasma etching, thereby removing a damage layer generated by machining after the SiC bare wafer 14 is cut out. This is because the main surface 4 can be flattened.

In addition, in this embodiment, since the oxide film 16 is formed and removed after the removal of 500 nm or more, the damage layer on the cut surface 15 of the SiC bare wafer 14 that could not be removed by CMP or plasma etching, CMP or plasma The altered layer (damage layer) generated during the etching can be surely removed.
Further, as described above, the step bunching 9 can be reduced even if the BPD density of the SiC epitaxial layer 3 is reduced. In this embodiment, the pits of the basal plane dislocations 11 can be formed on the main surface 4 of the SiC substrate 2 with an appropriate size in the range of several nm to several μm by performing the forming process and the removing process of the oxide film 16. The BPD density of the SiC epitaxial layer 3 can be reduced with little influence on the surface irregularities.

Specifically, as shown in FIG. 11, in the case where basal plane dislocations 11 around 1000 cm ⁻² exist on the main surface 4 of the SiC substrate 2, the oxide film 16 must be formed before the growth of the SiC epitaxial layer 3. The BPD density of the SiC epitaxial layer 3 was around 80 cm ⁻² . On the other hand, when the oxide film 16 is formed, the BPD density can be reduced to 10 cm ⁻² or less.

Further, as reported in Non-Patent Document 2, the linear density of the step bunching 9 on the surface of the SiC epitaxial wafer 1 depends on the temperature and the C / Si ratio when the SiC epitaxial layer 3 is formed. If the Si ratio is 0.5 or less, the occurrence of step bunching 9 can be prevented.
However, when SiC is epitaxially grown on the Si surface (0001) surface of the SiC substrate 2, the residual electron concentration of the SiC epitaxial layer 3 is preferably made as small as possible from the viewpoint of manufacturing a highly reliable device. In order to reduce the residual electron concentration, it is preferable to increase the C / Si ratio at the time of epitaxial growth, but this causes a problem that the linear density of the step bunching 9 generated on the surface 10 of the SiC epitaxial layer 3 increases.

On the other hand, in this embodiment, even if the C / Si ratio is increased, the linear density of the step bunching 9 can be reduced as compared with the conventional case. Specifically, as shown in FIG. 12, even when the C / Si ratio is 1.3, the linear density of the step bunching 9 can be 40 cm ⁻¹ or less, and at the same time, the BPD density is also 10 cm ⁻² . I was able to.
That is, as described in Non-Patent Document 2, the residual electron concentration can be reduced by epitaxial growth at a high C / Si ratio. However, in the conventional technique, the linear density of step bunching 9 is 1000 cm ⁻¹ or more. Therefore, it was inappropriate for device use.

Therefore, if the technique of this embodiment is used, even if the SiC epitaxial layer 3 is grown at a high C / Si ratio, the linear density of the step bunching 9 is 40 cm ⁻¹ or less. Therefore, as shown in FIG. 13, regardless of whether the SiC epitaxial layer 3 is grown on the Si surface or the C surface of the SiC substrate 2, the high quality is obtained under the condition that the residual electron concentration is 1 × 10 ¹⁶ cm ⁻³ or less. Epitaxial growth is possible. As a result, a high-quality and highly reliable semiconductor element can be manufactured. This SiC epitaxial wafer 1 is particularly suitable for high breakdown voltage device applications of 10 kV or higher.

In addition, in this embodiment, since the SiC epitaxial layer 3 is formed on the Si surface of the SiC substrate 2, the residual electron concentration of the SiC epitaxial layer 3 can be further reduced as compared with the case where it is formed on the C surface. .
The SiC epitaxial wafer 1 described above can be used, for example, for manufacturing various SiC semiconductor elements. Below, the example of a Schottky barrier diode, a trench gate type MOSFET, and a planar gate type MOSFET is shown as those examples.

FIG. 14 is a schematic cross-sectional view of a Schottky barrier diode fabricated using the SiC epitaxial wafer of FIG.
The Schottky barrier diode 21 as the SiC semiconductor element includes an n ⁺ type (for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ) of an SiC substrate 2 and an n ⁻ type (for example, a concentration of The SiC epitaxial wafer 1 including the SiC epitaxial layer 3 of 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ ) is provided. For example, N (nitrogen), P (phosphorus), As (arsenic) or the like can be used as the n-type impurity doped therein.

A cathode electrode 22 is formed on the back surface ((000-1) C surface) of SiC substrate 2 so as to cover the entire region.
Further, the surface 10 ((0001) Si surface) of the SiC epitaxial layer 3 has a contact hole 24 exposing a part of the SiC epitaxial layer 3 as an active region 23, and a field region 25 surrounding the active region 23. A covering field insulating film 26 is formed. The field insulating film 26 is made of SiO ₂ (silicon oxide), but may be made of other insulators such as silicon nitride (SiN). An anode electrode 27 is formed on the field insulating film 26.

A p-type JTE (Junction Termination Extension) structure 28 is formed near the surface 10 (surface layer portion) of the SiC epitaxial layer 3 so as to be in contact with the anode electrode 27. The JTE structure 28 is formed along the outline of the contact hole 24 so as to straddle the inside and outside of the contact hole 24 of the field insulating film 26.
According to the Schottky barrier diode 21, it has been confirmed that the leakage current can be reduced by one digit or more as compared with the prior art.

FIG. 15 is a schematic cross-sectional view of a trench gate type MOSFET fabricated using the SiC epitaxial wafer of FIG.
The trench gate type MOSFET 31 as the SiC semiconductor element includes an n ⁺ type SiC substrate 2 (for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ) and an n ⁻ type (for example, a concentration of 5). The SiC epitaxial wafer 1 including the SiC epitaxial layer 3 of × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ ) is provided.

A drain electrode 32 is formed on the back surface ((000-1) C surface) of SiC substrate 2 so as to cover the entire area.
Near the surface 10 ((0001) Si surface) (surface layer portion) of SiC epitaxial layer 3 is a p-type (for example, concentration is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) body region. 33 is formed. In the SiC epitaxial layer 3, the portion on the SiC substrate 2 side with respect to the body region 33 is an n ⁻ type drain region 34 that is maintained as it is after the epitaxial growth.

A gate trench 35 is formed in the SiC epitaxial layer 3. Gate trench 35 penetrates body region 33 from surface 10 of SiC epitaxial layer 3, and the deepest portion reaches drain region 34.
A gate insulating film 36 is formed on the inner surface of the gate trench 35 and the surface 10 of the SiC epitaxial layer 3 so as to cover the entire inner surface of the gate trench 35. A gate electrode 37 is buried in the gate trench 35 by filling the inside of the gate insulating film 36 with, for example, polysilicon.

An n ⁺ -type source region 38 that forms a part of the side surface of the gate trench 35 is formed in the surface layer portion of the body region 33.
The SiC epitaxial layer 3 has ap ⁺ type (for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³⁾ that penetrates the source region 38 from the surface 10 and is connected to the body region 33. ) Body contact region 39 is formed.

On the SiC epitaxial layer 3, an interlayer insulating film 40 made of SiO ₂ is formed. A source electrode 42 is connected to the source region 38 and the body contact region 39 through a contact hole 41 formed in the interlayer insulating film 40.
By applying a predetermined voltage (voltage higher than the gate threshold voltage) to the gate electrode 37 in a state where a predetermined potential difference is generated between the source electrode 42 and the drain electrode 32 (between the source and drain), the gate electrode A channel can be formed in the vicinity of the interface with the gate insulating film 36 in the body region 33 by the electric field from 37. As a result, a current can flow between the source electrode 42 and the drain electrode 32, and the trench gate type MOSFET 31 can be turned on.

  In the manufacturing process of the trench gate type MOSFET 31, high temperature annealing (for example, 1500 ° C. or more) is performed in order to activate the ion implantation region (for example, the body region 33, the source region 38, etc.). In the high temperature annealing process, the step bunching 9 tends to increase unless the surface 10 of the SiC epitaxial layer 3 is usually protected using a carbon cap or the like.

Therefore, if the SiC epitaxial wafer 1 obtained in this embodiment is used, it is possible to prevent an increase in the step bunching 9 even if the surface 10 is not protected during the high temperature annealing.
Further, the step bunching 9 of the SiC epitaxial layer 3 becomes a carrier scattering factor at the interface of the oxide film 16 of the MOSFET 31. Therefore, when the linear density of the step bunching 9 is large, the carrier mobility is lowered. In this embodiment, since the linear density of the step bunching 9 can be reduced to 1/50 compared with the conventional case, the carrier mobility can be improved.

FIG. 16 is a schematic cross-sectional view of a planar gate type MOSFET fabricated using the SiC epitaxial wafer of FIG.
The planar gate type MOSFET 51 as the SiC semiconductor element includes an n ⁺ type SiC substrate 2 (for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ) and an n ⁻ type (for example, a concentration of 5). The SiC epitaxial wafer 1 including the SiC epitaxial layer 3 of × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ ) is provided.

A drain electrode 52 is formed on the back surface ((000-1) C surface) of SiC substrate 2 so as to cover the entire region.
Near the surface 10 ((0001) Si surface) of the SiC epitaxial layer 3 (surface layer portion), a body region 53 of p-type (for example, the concentration is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ). Is formed in a well shape. In the SiC epitaxial layer 3, the portion on the SiC substrate 2 side with respect to the body region 53 is an n ⁻ type drain region 54 that is maintained as it is after epitaxial growth.

In the surface layer portion of the body region 53, an n ⁺ -type source region 55 is formed at a distance from the periphery of the body region 53.
Inside the source region 55, a p ⁺ -type body contact region 56 (for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ) is formed. The body contact region 56 penetrates the source region 55 in the depth direction and is connected to the body region 53.

A gate insulating film 57 is formed on the surface 10 of the SiC epitaxial layer 3. The gate insulating film 57 covers a portion surrounding the source region 55 in the body region 53 (peripheral portion of the body region 53) and the outer peripheral edge of the source region 55.
On the gate insulating film 57, a gate electrode 58 made of, for example, polysilicon is formed. The gate electrode 58 faces the peripheral edge of the body region 53 with the gate insulating film 57 interposed therebetween.

On the SiC epitaxial layer 3, an interlayer insulating film 59 made of SiO ₂ is formed. A source electrode 61 is connected to the source region 55 and the body contact region 56 through a contact hole 60 formed in the interlayer insulating film 59.
By applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 58 in a state where a predetermined potential difference is generated between the source electrode 61 and the drain electrode 52 (between the source and drain), the gate electrode A channel can be formed in the body region 53 in the vicinity of the interface with the gate insulating film 57 by the electric field from 58. As a result, a current can flow between the source electrode 61 and the drain electrode 52, and the planar gate MOSFET 51 can be turned on.

In the planar gate type MOSFET 51, as in the case of the trench gate type MOSFET 31 of FIG. 15, the increase in the step bunching 9 can be prevented and the carrier mobility can be improved without performing surface protection during the high temperature annealing.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, as shown in FIGS. 17A and 17B, the main surface 4 (substrate surface) of the SiC substrate 2 has an off angle of 4 ° or less in the off direction of the [−1100] axis with respect to the (0001) plane. It may be inclined at θ.

Although not shown, a MOS capacitor can be manufactured using the SiC epitaxial wafer 1 of this embodiment. In the MOS capacitor, the yield and reliability can be improved, and in particular, the yield can be improved by 20% or more. In addition, initial failures can be reduced in terms of reliability.
Moreover, although illustration is abbreviate | omitted, a bipolar transistor can also be manufactured using the SiC epitaxial wafer 1 of this embodiment. The bipolar transistor preferably has a high amplification factor, but if the linear density of the step bunching 9 is high, it is difficult to obtain a high amplification factor due to the influence of the surface 10 recombination. Therefore, if the SiC epitaxial wafer 1 of this embodiment is used, the step density of the step bunching 9 and the residual electron concentration of the SiC epitaxial layer 3 are low and the epitaxial growth is performed at a high C / Si ratio. The gain can be further improved as compared with the prior art.

In addition, the SiC epitaxial wafer 1 of this embodiment can also be used for manufacturing pn diodes, IGBTs (Insulated Gate Bipolar Transistors), CMOSs, and the like.
Further, with respect to the Schottky barrier diode 21, the trench gate type MOSFET 31, and the planar gate type MOSFET 51 described above, a configuration in which the conductivity type of each semiconductor portion is inverted may be employed. For example, in the Schottky barrier diode 21, the p-type portion may be n-type and the n-type portion may be p-type.

  The semiconductor element of the present invention is used in, for example, a power module used in an inverter circuit that constitutes a drive circuit for driving an electric motor used as a power source for electric vehicles (including hybrid vehicles), trains, industrial robots, and the like. Can be incorporated into. It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.

  In addition, various design changes can be made within the scope of matters described in the claims.

Next, although this invention is demonstrated based on an Example and a comparative example, this invention is not limited by the following Example.
(1) Example 1
A SiC bare wafer was obtained by cutting a 4H—SiC ingot with an off angle θ of 4 ° in the [11-20] axial direction with respect to the (0001) plane. Next, the cut surface ((0001) surface) of the SiC bare wafer was polished by lapping. After machining, the cut surface ((0001) plane) of the SiC bare wafer was removed by 500 nm or more by CMP. Thereafter, after megasonic cleaning with functional water and drying with an ionizer, a SiC epitaxial layer was grown on the main surface of the SiC substrate in a range of C / Si ratio = 1.3 to 2.0 (thickness). 5μm 600V withstand voltage). When the linear density of the step bunching of the SiC epitaxial wafer obtained as described above was measured, it was 40 cm ⁻¹ or less.
(2) Example 2
By performing the same operation as in Example 1 except that the 4H-SiC ingot was cut out with an off angle θ of 4 ° in the [−1100] axial direction with respect to the (0001) plane, a SiC epitaxial wafer was obtained. Was made. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(3) Example 3
By performing the same operation as in Example 1 except that the 4H—SiC ingot was cut out with an off angle θ of 2 ° in the [11-20] axial direction with respect to the (0001) plane, A wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(4) Example 4
After machining, a SiC epitaxial wafer was fabricated by performing the same operation as in Example 1 except that the cut surface ((0001) plane) of the SiC bare wafer was removed by 500 nm or more by plasma etching. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(5) Example 5
Except for performing the process of forming an oxide film (thickness 40 nm) by dry oxidizing the main surface of the SiC substrate after removing 500 nm or more by CMP, and then performing the process of removing the oxide film with HF, By carrying out the same operation as in Example 1, a SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(6) Example 6
Except for performing a step of forming an oxide film (thickness 40 nm) by dry-oxidizing the main surface of the SiC substrate after removing 500 nm or more by plasma etching, and then a step of removing the oxide film with HF. By performing the same operation as in Example 4, a SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(7) Example 7
By performing the same operation as in Example 1 except that the SiC epitaxial layer corresponding to the withstand voltage of 1200 V was grown on the main surface of the SiC substrate in the range of C / Si ratio = 1.3 to 2.0, A SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(8) Example 8
By performing the same operation as in Example 1 except that the SiC epitaxial layer corresponding to 2400 V breakdown voltage was grown on the main surface of the SiC substrate in the range of C / Si ratio = 1.3 to 2.0, A SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(9) Example 9
By performing the same operation as in Example 1 except that the SiC epitaxial layer corresponding to 3300 V withstand voltage was grown on the main surface of the SiC substrate in the range of C / Si ratio = 1.3 to 2.0, A SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.
(10) Example 10
By performing the same operation as in Example 1 except that a 6600 V withstand voltage SiC epitaxial layer was grown on the main surface of the SiC substrate in the range of C / Si ratio = 1.3 to 2.0, A SiC epitaxial wafer was produced. The linear density of step bunching of this SiC epitaxial wafer was also 40 cm ⁻¹ or less.

DESCRIPTION OF SYMBOLS 1 SiC epitaxial wafer 2 SiC substrate 3 SiC epitaxial layer 4 Main surface (SiC substrate) 5 Terrace surface 6 Step surface 7 Layer 8 Step line 9 Step bunching 10 Surface (of SiC epitaxial layer) 11 Base surface dislocation 12 Etch pit 13 SiC Ingot 14 SiC bare wafer 15 Cut-out surface 16 Oxide film 21 Schottky barrier diode 22 Cathode electrode 23 Active region 24 Contact hole 25 Field region 26 Field insulating film 27 Anode electrode 28 JTE structure 31 Trench gate type MOSFET
32 drain electrode 33 body region 34 drain region 35 gate trench 36 gate insulating film 37 gate electrode 38 source region 39 body contact region 40 interlayer insulating film 41 contact hole 42 source electrode 51 planar gate type MOSFET
52 drain electrode 53 body region 54 drain region 55 source region 56 body contact region 57 gate insulating film 58 gate electrode 59 interlayer insulating film 60 contact hole 61 source electrode

Claims (11)

A SiC substrate having a main surface inclined at an off angle of 4 ° or less with respect to the (0001) plane ;
Is formed on the main surface of the SiC substrate, a first 1SiC layer having a first height, said second 1SiC layer is formed are integrated two or more layers, a first 2SiC layer having a height of more than 0.5nm A SiC epitaxial layer containing
A SiC epitaxial wafer, wherein the density of the second SiC layer is 40 cm ^-1 or less.   2. The SiC epitaxial wafer according to claim 1, wherein the main surface of the SiC substrate is a surface inclined at an off angle of 4 ° or less in the [11-20] axis direction with respect to a (0001) plane.   2. The SiC epitaxial wafer according to claim 1, wherein the main surface of the SiC substrate is a surface inclined at an off angle of 4 ° or less in the [−1100] axis direction with respect to a (0001) plane. The SiC substrate comprises 4H-SiC, SiC epitaxial wafer according to any one of claims 1-3. The SiC epitaxial wafer according to any one of claims 1 to 4 , wherein the main surface of the SiC substrate is a Si surface. The SiC epitaxial wafer according to any one of claims 1 to 5 , wherein a basal plane dislocation density of the SiC epitaxial layer is 10 cm ^-2 or less. The SiC epitaxial wafer according to any one of claims 1 to 6 , wherein a density of the second SiC layer is 5 cm- ¹ . The SiC epitaxial wafer according to any one of claims 1 to 7 , wherein the SiC epitaxial layer is made of 4H-SiC. The SiC epitaxial wafer as described in any one of Claims 1-8 whose nitrogen concentration of the said SiC epitaxial layer is 5 * 10 < ¹⁶ > cm < ^-3 > or less. The SiC epitaxial layer thickness is 3μm or more, SiC epitaxial wafer according to any one of claims 1-9. The SiC semiconductor element formed using the SiC epitaxial wafer as described in any one of Claims 1-10 .

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