TWI726004B - Diamond electronic components - Google Patents

Abstract

To provide a diamond electronic component such as MOSFETFET, MESFET, etc., which is useful as a power device and has excellent low loss and high withstand voltage characteristics. A diamond electronic component, which has a diamond layered structure; the diamond layered structure is formed by at least the following conforming layers: a p+ conductive layer made of diamonds, a p-type drift layer made of diamonds, and diamonds The high-resistance layer, and the p+ contact layer made of diamond. The high-resistance layer is, for example, nitrogen-doped diamond. By using the {111} plane of the high-resistance layer of the diamond multilayer structure in the trench structure of the hole channel, the vertical or analog vertical structure of MOSFET and MESFET is realized.

Description

Diamond electronic components

FIELD OF THE INVENTION The present invention relates to a high-output diamond electronic component with a vertical structure or an analog vertical structure.

Background of the Invention In recent years, diamond electronic components have been expected to operate under large frequency band gaps, high avalanche destruction electric fields, high saturated carrier mobility, high thermal conductivity, high temperature, and radiation exposure environments. , As a component that can be operated practically. As a semiconductor device that utilizes these characteristics, the development of diamond Schottky-barrier diodes, diamond electric field effect transistors, diamond pn diodes, diamond thyristors, and diamond thyristors have been developed. High-power diamond semiconductor components such as crystals.

Previously, among the stacked structures of high-power diamond semiconductor elements, research and development including the present inventors have been carried out on analog vertical structures (refer to Patent Documents 1 and 2) and vertical structures.

In addition, the inventors of the present invention have conducted research and development on obtaining a high-quality diamond layered structure and manufacturing method by CVD (refer to Patent Documents 3 to 5). In addition, the inventors proposed a horizontal MESFET (Metal-Semiconductor Field Effect Transistor; metal-semiconductor field effect transistor) having a channel on the (100) plane of diamond (see Non-Patent Document 1). In addition, MESFET is an electric field effect transistor, which has a structure in which a Schottky junction metal is formed on a semiconductor as a gate electrode.

When investigating the prior technical literature, the following techniques are used.

Patent Document 6 discloses an electric field transistor in which a substrate, a diamond semiconductor layer, and a compound semiconductor layer are formed in the following order as an electric field effect transistor having diamond as a main material. This electric field electrocrystalline system uses (111) plane diamonds to form the diamond semiconductor layer, and uses (0001) plane hexagonal crystal compound semiconductors or (111) plane cubic crystal compounds to form the compound semiconductor layer. Patent Document 6 describes that a compound semiconductor can be spontaneously aligned by crystal growth on a (111) plane diamond.

Patent Document 6 also discloses that as a prior art, FETs using diamond semiconductors as channel materials are mostly of hole conductivity type. This is the result of using the hydrogen terminal surface of the spontaneously formed diamond as a carrier supply source when using the chemical vapor deposition (CVD) method to grow and form diamond crystals. In this prior art, due to the low hole mobility, high-frequency operation and high current density are difficult. Furthermore, it is known that because the threshold voltage depends on the interface state of the hydrogen terminal surface, there is It is difficult to control the problem of threshold voltage. Prior Art Documents Patent Documents

Patent Document 1: Japanese Patent Laid-Open No. 2009-252776 Patent Document 2: Japanese Patent Laid-Open No. 2009-59798 Patent Document 3: Japanese Patent Laid-Open No. 2009-200343 Patent Document 4: Japanese Patent Laid-Open No. 2007-194231 Patent Document 5: Japanese Patent Laid-Open No. 2009-59739 Patent Document 6: Japanese Patent Laid-Open No. 2008-186936 Non-Patent Document

Non-Patent Document 1: H. Umezawa et al., IEEE Electron Device Lett. 35 (2014) 1112.

Summary of the Invention Problems to be solved by the invention Efforts have been made to use diamond semiconductors as power devices. It has been proposed to disclose a horizontal diode, a diode obtained by simulating a vertical structure, a diode obtained by a vertical structure, a horizontal MESFET, and a horizontal MOSFET. The electric field effect transistor formed by forming a gate metal on a semiconductor through an insulating film is called a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor; Metal-Oxide-Semiconductor Field Effect Transistor). In order to reduce the loss and increase the withstand voltage of the transistor, it is necessary to have a vertical structure with a trench gate structure. In order to realize the trench gate structure, it is necessary to selectively form n-type and p-type layers, and high-precision etching technology. However, implantation of ions in diamond will cause quality deterioration and movement due to implantation damage. The problem of deterioration of semiconductor characteristics such as temperature, carrier concentration, etc.; and the problem of defects in the sidewall of the growth during selective growth of a few microns. In addition, when chemical etching is performed on diamonds using chemicals, it is difficult to control and defects are generated on the surface. Moreover, when using ICP (Inductive Coupled Plasma; inductively coupled plasma) and CCP (Capasitive Coupled Plasma; capacitively coupled plasma) for physical and chemical etching, there are etched surface defects and etch pits on the bottom of the etched surface. The problem of affecting the quality of the semiconductor performance caused by the manufacturing process or adversely affecting the quality of the semiconductor performance.

The present invention was made to solve these problems, and its purpose is to reduce the loss and increase the withstand voltage of the diamond semiconductor. In addition, the object of the present invention is to provide a diamond electronic component with excellent low loss and high withstand voltage characteristics suitable for a vertical structure and a simulated vertical structure.

In order to achieve the aforementioned object, the present invention has the following features.

The present invention relates to a diamond electronic component, which has a diamond layered structure; the diamond layered structure has at least in the following order: a p+ conductive layer made of diamond, a p-type drift layer made of diamond, and a diamond made of diamond The high resistance layer and the p+ contact layer made of diamond. For example, in the case of a MOSFET, the above-mentioned multilayer structure is used. In the case of MESFET, a multilayer structure of p-type layer made of diamond is arranged between the high resistance layer made of diamond and the p+ contact layer made of diamond.

For example, in the diamond electronic component of the present invention, the p+ conductive layer is laminated on a semi-insulating substrate.

For example, in the diamond electronic device of the present invention, the high resistance layer is a layer made of nitrogen-doped diamond.

For example, the diamond electronic component of the present invention has a trench structure in the diamond layered structure, and the trench sidewalls of the trench structure are {111} planes.

For example, the diamond electronic component of the present invention has a gate electrode on the {111} plane.

For example, in the diamond electronic component of the present invention, the gate electrode has a metal-semiconductor junction transistor structure.

For example, the diamond electronic component of the present invention has a transistor structure in which the aforementioned gate electrode is a metal-insulating film-semiconductor junction.

For example, the diamond electronic component of the present invention includes a first electrode on the p+ conductive layer and a second electrode on the contact layer. For example, the first electrode is a drain electrode and the second electrode is a source electrode.

The present invention relates to a field-effect transistor, which is characterized in that the {111} plane of a nitrogen-doped diamond layer with a diamond laminated structure is used in the hole channel.

The present invention relates to a field-effect transistor, which is characterized in that the gate electrode is arranged on the {111} plane of nitrogen-doped diamond through an insulating film to form a metal-insulating film-semiconductor junction, and the aforementioned {111} The surface is used in the electric hole channel.

The present invention relates to a field-effect transistor, which is characterized in that the gate electrode is arranged on the {111} plane of nitrogen-doped diamond through a p-type layer to form a metal-semiconductor junction and the p-type layer is used as a channel.

Specifically, the {111} surface is flattened by atoms and terminated by hydrogen or OH groups. Invention effect

The diamond electronic component of the present invention can achieve low loss and high withstand voltage.

By having the diamond laminated structure of the present invention, it is possible to obtain the effect of reducing the loss of a larger current with a smaller chip area.

In addition, the diamond laminate structure formed on a high-quality semi-insulating substrate can achieve the effect of lowering the price.

In addition, because the structure in which the {111} surface is exposed and the gate electrode is formed on the exposed {111} surface, a MOS interface with a low interface level density can be obtained, so it can have a high mobility and The effect of lowering the loss of a larger current with a smaller chip area is greater.

In addition, as in the present invention, when the gate electrode adopts a metal-semiconductor junction transistor structure, it can be a MESFET structure and can obtain the effect of increasing the current.

Moreover, as in the present invention, when the gate electrode adopts a metal-insulating film-semiconductor junction transistor structure, it can be a MOSFET structure and can be enhanced.

In addition, when nitrogen-doped diamond is used for the high-resistance layer, growth can be facilitated and the effect of lowering the price can be obtained.

Furthermore, as in the present invention, in a semiconductor device with a diamond-layered structure, by using the (111) surface of diamond in the channel, the surface atoms can be flattened. In addition, the semi-insulating layer formed by using the (111) surface of diamond in the channel for atomic flattening, using hydrogen or OH groups for termination and using a nitrogen-doped layer in the channel can be used at the interface (MOS, MES) Defect-free diamond layered structure to manufacture power semiconductors.

Detailed description of preferred embodiments The following describes embodiments of the present invention.

In order to achieve low loss and high withstand voltage of field-effect transistors, a vertical channel structure must be used in the process to form a transistor that does not affect semiconductor performance and does not trap charges on the MOS interface, and it must be manufactured without MOS. The structure that generates current at the interface.

First, when the MOS interface has a defect, there is a defect in the charge accumulation, the mobility is low due to Coulomb scattering, or the voltage applied to the gate causes all the charges induced on the semiconductor side to accumulate defects, and there are problems such as inability to conduct electricity. .

In addition, when the semiconductor surface has a defect, it is scattered, resulting in low mobility and poor conductivity. Therefore, the MOS interface must be flat and free from defects such as dangling bonds.

In the Si semiconductor technology, for example, an oxide film insulator can be obtained by oxidizing and growing the base material Si. Therefore, the base material Si and the oxide film insulator have a chemical bond. However, since diamond does not have an oxide solid insulating film, it is necessary to form an insulating film of _{SiO 2} , Al ₂ O _{3, etc. on the oxide film by vapor deposition and CVD.} Since insulating film formations such as SiO ₂ and Al ₂ O ₃ lack chemical bonds with the diamond surface, the diamond surface must be treated in advance and defects such as dangling bonds must be terminated. Because usually MOSFET-based sheet carrier concentration from 1E12 / cm ² until 1E13 / cm ² or so, in order to obtain the defect density of the free carriers, must be about ² or less 1E11 / cm. However, the atom density on the diamond surface is about 1E15/cm ² and the bonding must be controlled at 99.99% of the surface atoms. In the current (001) surface diamond, although the hydrogen terminal surface is assumed to be an ideal state, there is no report revealing the technology to realize such a high-quality surface.

In addition, diamond has a large frequency band gap of 5.5 eV, and since the electron affinity becomes negative or positive depending on the terminal atom, the selection of the terminal atom is important. Especially when hydrogen is used for termination, the system becomes a negative electron affinity state, and compared to the conductive band of the insulator, the conduction band of diamond is located at a higher position, so the electron system in the diamond easily enters the conduction band and becomes a gate. Extreme leakage current.

It is important for channel doping to control the threshold. In the case of a p-channel FET, it must be an n-type layer, and in the case of an n-channel FET, it must be a p-type layer. Although phosphorus is usually used in the n-type layer in diamonds, it is very difficult to control the quality of phosphorus-doped diamonds.

The inventors focused on the laminated structure of diamond electronic components, and achieved the development of a laminated structure of the present invention including a p-type drift layer made of diamond and a high resistance layer made of diamond.

In addition, the inventor of the present invention focused on diamond electronic components and achieved the development of an invention that uses the (111) surface in the channel. More specifically, the system has the following structure: the (111) surface is planarized with a 1×1 surface structure and terminated with hydrogen or OH groups, and the n-type layer, which is difficult to synthesize, is not used but is doped with nitrogen. The semi-insulating layer (also referred to as the "high-resistance layer") serves as a channel and forms a structure with holes. With this structure, lower loss and higher withstand voltage can be achieved. In addition, in this specification, the (111) plane of atomic flattening means that atomic flattening means atomic flattening using a method such as hydrogen plasma treatment. By using a semi-insulating layer doped with nitrogen in the channel, the surface conductive layer obtained by hydrogen-terminated diamond cannot be formed in an unbiased state.

In the embodiment of the present invention, when the (111) surface is used as a channel, there are methods (a) of forming (111) on the (001) surface; and (b) of forming (111) channels on the (110) surface. In the embodiment of the present invention, a trench structure is provided in the diamond layered structure and the sidewalls of the trench structure are {111} planes. The gate electrode is arranged in such a way that it is located on the aforementioned {111} plane. Here, for example, the plane equivalent to the (001) plane is described as {001}.

In addition, with respect to the methods (a) and (b), each of the vertical structure and the simulated vertical structure can be manufactured.

Moreover, it can also be set as a MESFET structure using Schottky junction for the gate structure.

In addition, the MOSFET structure or the MESFET structure may be with a body diode attached or without a body diode. Here, the internal diode system forms a diode between the source and the drain by the structure of the embodiment described later, and is referred to as an internal diode.

The diamond laminated structure of the diamond electronic component of the embodiment of the present invention is provided with at least a p+ conductive layer, a p-type drift layer made of diamond, a high resistance layer made of diamond, and a p+ contact made of diamond Diamond layered structure formed by layering in this order.

The "p+ conductive layer" is, for example, a "p+ conductive layer" formed by forming a film on a conductive substrate or a high-quality diamond semi-insulating substrate.

The p+ conductive layer preferably has a boron concentration of 5E19/cm ³ or more and 1E22/cm ³ or less, and preferably a range of 1E20/cm ³ or more and 1E21/cm ³ or less. The specific resistance of the p+ conductive layer is preferably about 0.1 mΩcm or more and 100 mΩcm or less, and more preferably 10 mΩcm or less. The film thickness is preferably about 1 μm or more and 300 μm or less, and more preferably 10 μm or more and 200 μm or less.

The so-called "high quality" of a high-quality diamond semi-insulating substrate, for example, means that the penetration differential row density in the substrate is about 1E3/cm ³ or less. The semi-insulating substrate is preferably a diamond single crystal containing nitrogen at a concentration of ^{1E15/cm 3} or more and 1E21/cm ^{3 or less.}

The "p-type drift layer made of diamond" is, for example, a "high-quality drift layer." In addition, the so-called "drift layer" is used to maintain the voltage applied between the gate and the drain, that is, the withstand voltage area. In this embodiment, the "p-type drift layer made of diamond" is, for example, a p-type diamond layer doped with boron, and the boron concentration is preferably 1E15/cm ³ or more and 1E18/cm ³ or less. The film thickness is preferably 0.5 μm or more and 100 μm or less. The concentration and film thickness are related to the operating current and/or withstand voltage design.

The "high-resistance layer made of diamond" is, for example, the "nitrogen-doped channel layer" of MOSFET and the "nitrogen-doped layer" of MESFET, which will be described later. The so-called "high-resistance layer" here is preferably a diamond layer with a resistance of 1E8 Ohm-cm or more at room temperature, and it can also be called semi-insulating. In the case of MOSFET, the carrier of CV=Q may be induced on the semiconductor side by sandwiching the insulating film, that is, the action of "inducing the channel in the non-conductive film to make it conductive" is possible. On the other hand, in the case of MESFET, since it is impossible in principle to make the inversion induction system, only the action of "depleting the conductive channel" is possible. At this time, in the MOSFET, because the conductive region is formed on the non-conductive film, the nitrogen-doped region other than the dotted line (secondary hole gas) in the figure below is non-conductive, that is, outside the channel, it is not A current path connecting the source electrode to the drain electrode is formed. On the other hand, in the MESFET, when the current path is not cut off by the other nitrogen-doped regions, a direct flow path from the source to the drain is created, so the nitrogen-doped regions are necessary.

For the nitrogen-doped channel layer and the nitrogen-doped layer, the nitrogen concentration of the nitrogen-doped diamond is 1E13/cm ³ (representing 1.0×10 ¹³ /cm ³ ) or more and 1E21/cm ³ or less, and is 0.5 μm or more and A thickness of 50 μm or less is preferred. In addition, for the nitrogen-doped channel layer and the nitrogen-doped layer, the nitrogen concentration of the nitrogen-doped diamond is in the range of 1E15/cm ³ or more and 1E19/cm ³ or less, and preferably has a thickness of 0.5 μm or more and 10 μm or less.

For the high resistance layer of MESFET, the upper limit of nitrogen concentration is relatively wide. In the case of MOSFET, the nitrogen concentration affects the threshold (an important design parameter of FET). In the case of MESFET, it serves as a barrier layer. The barrier layer is used only to prevent holes from flowing directly from the source to the drain. . Therefore, the threshold voltage is set to 1V or more and 10V or less, and in order to make the withstand voltage 500V or more and the current controllability to 500A/cm ² , the range of the nitrogen concentration is preferably the above-mentioned range.

In the case of MESFET, it has a multilayer structure in which a p-type layer made of diamond is arranged between a high-resistance layer made of diamond and a p+ contact layer made of diamond. Because the MES system does not have a gate insulating film, it is necessary to provide a p-type layer between the p+ type contact layer and the p+ type contact layer so that each electrode is not short-circuited, especially the source and the gate, and the stacked structure system and MOS Slightly different.

When nitrogen is doped, the impurity level can be suppressed at a position of about 1.4 eV from the conduction band. In terms of resistance value, it is 1E8Ohm-cm or more at room temperature.

In the MOS structure, the carrier can be induced on the semiconductor side from the gate electrode through the insulating film. On the other hand, the carrier cannot be induced in the MES structure. The p-type channel layer where the carrier exists at the beginning is necessary, and the gate voltage is used to extend the depletion layer in the p-type channel layer to control the conductivity. The principle that the depletion layer expands in the channel to insulate it. In the MOSFET, the nitrogen-doped side surface of the interface with the nitrogen-doped diamond insulating film (MOS interface), strictly speaking, the hole channel is formed in the region of about 10nm or less on the nitrogen-doped side from the MOS interface. However, in the case of MESFET, the entire p-type film becomes a channel.

The "p+ contact layer made of diamond" refers to the "contact layer" in each figure described later. The p+ conductive layer preferably has a boron concentration of 5E19/cm ³ or more and 1E22/cm ³ or less, preferably in a range of 1E20/cm ³ or more and 1E21/cm ³ or less. The specific resistance is preferably about 0.1 mΩcm or more and 100 mΩcm or less, and more preferably 10 mΩcm or less. The film thickness is preferably about 0.05 μm or more and 1 μm or less, and more preferably 0.1 μm or more and 0.5 μm or less.

The materials of each electrode and insulating film can be used in conventional diamond electronic components.

An ohmic junction electrode can be used for the source electrode and the drain electrode system. The ohmic junction electrode system can use Ti, Cr, or Ni. It is possible to adopt a multilayer structure composed of a plurality of metals and set as an ohmic junction electrode/cap electrode on diamond, or a structure of ohmic junction electrode/barrier electrode/cap electrode on diamond. The cap electrode system can use Au or Al. The barrier electrode system can use Pt or Mo. The ohmic junction electrode and the barrier electrode system are each about 10 nm or more and 100 nm or less, and the cap electrode system preferably has a thickness of 50 nm or more and 300 nm or less.

(Embodiment 1) This embodiment will be described below with reference to Fig. 1. FIG. 1 is a schematic diagram of a vertical structure MOSFET (with an internal diode) formed on a (001) wafer in this embodiment.

The element of FIG. 1 has a diamond laminated structure composed of a conductive substrate 2, a high-quality drift layer 3, a nitrogen-doped channel layer (high-resistance layer 4), and a contact layer 5. Any layer of the aforementioned diamond layered structure is composed of diamonds. The drain electrode 9 is provided on the conductive substrate 2 and on the opposite side of the high-quality drift layer 3. The source electrode 8 is provided on the contact layer 5 on the opposite side of the high-quality drift layer 3, and a part is directly provided on the nitrogen-doped channel layer (high resistance layer 4). The surface of the nitrogen-doped channel layer is the (001) surface. The trench structure is set in the diamond layered structure, and the sidewalls of the trench structure are atomically flattened (111) planes. The trench structure of the present embodiment is shown in Fig. 1, and the side wall has an inclined structure. The bottom surface of the trench of the trench structure is located in the high-quality drift layer 3, and the sidewall is a trench formed by three layers of the high-quality drift layer 3, the nitrogen-doped channel layer (high resistance layer 4), and the contact layer 5. In the trench of the trench structure, a gate electrode 7 is provided through the insulating film 6. In addition, the gate electrode 7 and the source electrode 8 are insulated by the insulating film 6.

In this device, a layer (secondary hole gas (2DHG)) in which the gate structure (MOS interface) is parallel to the gate structure (MOS interface) and the hole carrier exists in the form of a two-dimensional sheet (two-dimensional hole gas (2DHG)) can be revealed by the gate voltage. By the appearance of the hole carrier, the source-contact layer and the drift layer-conductive layer (conductive substrate) are connected so that current flows between the source and the drain.

The nitrogen-doped channel layer is a semi-insulating diamond layer doped with nitrogen, and can be obtained with a nitrogen concentration of 1E15/cm ³ or more and 1E19/cm ³ or less, and a film thickness of 0.5 μm or more and 50 μm or less. The concentration and film thickness are related to the operating current and/or withstand voltage design.

The manufacturing method of the device shown in FIG. 1 is described.

First, a high-quality drift layer is grown and formed on a conductive substrate using the CVD method. CVD is performed using a microwave plasma method, using hydrogen as a carrier gas and controlling so that methane as a carbon raw material becomes 4% of the total flow rate. In addition, carbon dioxide to prevent unnecessary introduction of oxygen raw materials from the processing chamber and trimethyl boron as boron raw materials are added. The concentration of carbon dioxide is set so that the O/C ratio becomes 0.4, and the trimethyl boron is controlled so that the B/C ratio becomes about 0.5 ppm. Specifically, the hydrogen flow rate was set to 383 ccm, the methane flow rate was set to 12.8 sccm, the CO ₂ flow rate was set to 3.2 sccm, and trimethyl boron diluted to 10 ppm with hydrogen was introduced into the processing chamber at a flow rate of 0.5 sccm. . The carbon raw material may be set to 0.1% or more and 10% or less of the total flow rate, and the oxygen flow rate system O/C may be 1 or less. The plasma power is 3.9kW, the gas pressure in the processing chamber is 120 Torr, and the synthesis temperature is 950°C. The carbon raw material can also be carbon monoxide or ethane, and the oxygen raw material can also be oxygen. In addition, when using carbon monoxide as the carbon raw material, the oxygen raw material may not be used. The plasma power can also be set to 750W or more and 10kW or less, and the pressure in the processing chamber can also be set to 20 Torr or more and 300 Torr or less.

Then, the growth is followed to form a nitrogen-doped layer, and the growth forms a p+ layered layer. The nitrogen-doped layer is formed by introducing nitrogen raw materials in addition to hydrogen and carbon raw materials. Specifically, the hydrogen flow rate was set to 374 ccm, the methane flow rate was set to 16 sccm, and the nitrogen diluted to 100 ppm was set to 10 sccm. The p+ layer is formed by introducing hydrogen, carbon raw material, and boron raw material gas. Specifically, the hydrogen flow rate was set to 393 sccm, the methane flow rate was set to 2 sccm, and trimethylboron diluted to 1% was set to 5 sccm and introduced into the processing chamber.

Next, where it becomes a gate portion, Ni is selectively formed using a lithography method and a peeling method, and etching is performed to expose the {111} plane. In the etching process, first, Ni was deposited by a vacuum vapor deposition method to about 350 nm, _{and a mixed gas of N 2} and H ₂ O was flowed in an electric furnace in an environment of 900° C. for processing for 1 hour. Then, the metal contamination is removed by adding water with hydrochloric acid (HCl: H ₂ O ₂ : H ₂ O = 1:1: 6), and the metal contamination is removed by hot mixing acid (HNO ₃ : H ₂ SO ₄ = 1:3, 240°C). ) And remove the non-diamond layer. The {111} plane becomes atomically flat by hydrogen plasma treatment.

Next, after forming the gate oxide film, the gate electrode is formed by using the lithography method and the peeling method. The formation of the gate oxide film was performed using the ALD method, the synthesis temperature was set to 250° C., and the oxide film thickness was set to 100 nm. Ti was used for the gate electrode system, and the lithography method and the peeling method were used, and the film thickness was set to 50 nm for sputtering formation.

Next, a drain electrode, which is an ohmic electrode, is formed on the conductive substrate. The CVD method is used to form an insulating film to prevent short circuit between the gate electrode and the source electrode. The lithography method and dry etching method are used to expose the contact layer, and the lithography method and the peeling method are used to form the source electrode. The drain electrode and the source electrode are ohmic junctions and are formed by a sputtering method. It is formed in the order of Ti, Mo, and Au, and the film thickness is set to 30 nm, 30 nm, and 100 nm, respectively. The insulating film was grown by CVD using TEOS (Tetra Ethyl Ortho Silicate) as a source gas to form an SiO ₂ insulating film with a film thickness of 1 μm.

Here, investigations are made regarding the flattening of atoms at the gate portion.

Investigate that Ni was selectively formed using the lithography method and the peeling method at the above-mentioned gate part, and the {111} surface was exposed by etching and the {111} surface was made atomically flat by the hydrogen plasma treatment. The result of the state step. As an example, specifically, the nitrogen concentration of the nitrogen-doped diamond substrate is about 1E19/cm ³ . In the hydrogen plasma treatment system, only hydrogen is used as an introduction gas, and the treatment is performed at 400W and 20kPa for 150 hours. The roughness of the (111) surface channel before and after hydrogen treatment was evaluated by atomic force microscope (AFM). The roughness RMS of the (111) surface channel before the treatment was about 0.17 nm, and the atomic flatness could not be obtained and a plurality of surface atoms had a bonded state. However, after hydrogen plasma treatment, the roughness RMS is 0.03 nm and the displacement between terraces is 0.21 nm. From this result, it is known that a flat area can be obtained at the atomic level after the hydrogen plasma treatment.

On the other hand, in order to make a trial of a MESFET with channels on 100 sides as a comparative example, the following process was performed. The p-drift layer is synthesized on the Ib diamond substrate with (001) plane on the surface, and the nitrogen-doped layer is grown by selective growth. The selective growth mask uses a laminated metal structure composed of Ti and Au. The film thickness is set to 30 nm and 200 nm, respectively. The selective growth of nitrogen doping was performed by microwave CVD under the following conditions. In a hydrogen environment, the methane concentration is 1%, the N/C concentration is 5000 ppm, and the 750W is performed for 2 hours. The nitrogen concentration of the nitrogen-doped selective growth layer is about 1E15/cm ³ . After the selective growth, the selective growth mask is peeled off by acid treatment. When observed with a scanning microscope (SEM), roughness can be observed on the sidewall of the growth and it is difficult to recover by hydrogen plasma treatment. Furthermore, additional growth is performed by CVD to form a channel layer. The channel layer growth conditions were performed in a hydrogen environment with a methane concentration of 4%, 3900W, and 1 hour. It is known that even after the additional growth, the etched side surface that is used as the (001) plane channel still remains rough.

(Embodiment 2) This embodiment will be described below with reference to Fig. 2. 2 is a schematic diagram of a simulated vertical structure MOSFET (with internal diode attached) formed on a (001) wafer of this embodiment.

Compared with FIG. 1, the structure of the device in FIG. 2 does not use a conductive substrate, and the location of the drain electrode is different. In the device of FIG. 2 the p+ conductive layer 12 is epitaxially grown on the high-quality diamond semi-insulating substrate 11, and on the p+ conductive layer 12, the same as in FIG. 1, according to the high-quality drift layer 3 and the nitrogen-doped channel layer ( The high resistance layer 4) and the contact layer 5 are formed in this order. The drain electrode 9 is arranged on the p+ conductive layer 12 and the aforementioned high-quality drift layer side.

(Embodiment 3) Hereinafter, this embodiment will be described with reference to FIG. 3. Fig. 3 is a schematic diagram of a vertical structure MESFET (with internal diode attached) formed on a (001)-plane wafer of this embodiment.

The element of FIG. 3 has a diamond laminated structure composed of a conductive substrate 2, a high-quality drift layer 13, a nitrogen-doped layer (high-resistance layer 14), a p-type layer, and a contact layer 15. Any layer of the aforementioned diamond layered structure is composed of diamonds. The drain electrode 9 is provided on the conductive substrate 2 and on the opposite side of the high-quality drift layer 13. The source electrode 8 is provided on the opposite side of the contact layer 15 and the aforementioned high-quality drift layer 13, and a part is directly provided on the nitrogen-doped layer (high-resistance layer 14). The surface of the nitrogen-doped layer (high resistance layer 14) is the (001) surface. The trench structure is set in the diamond layered structure, and the sidewalls of the trench structure are atomically planarized (111) planes. The bottom surface of the trench of the trench structure is located in the high-quality drift layer 13, and the sidewall is a trench formed by three layers of the high-quality drift layer 13, the nitrogen-doped layer (high resistance layer 14), and the contact layer 5. The gate electrode 7 is provided in the trench of the trench structure through the p-type layer. In addition, the gate electrode 7 and the source electrode 8 are insulated by the insulating film 6.

The nitrogen-doped layer is a semi-insulating diamond layer doped with nitrogen, and the nitrogen concentration is about 1E15/cm ³ or more and 1E21/cm ³ or less. The film thickness is about 0.5 μm or more and 50 μm or less.

The manufacturing method of the device shown in FIG. 3 is described.

First, a high-quality drift layer is grown and formed on a conductive substrate using the CVD method. CVD is performed using a microwave plasma method, using hydrogen as a carrier gas and controlling so that methane as a carbon raw material becomes 4% of the total flow rate. In addition, carbon dioxide to prevent unnecessary introduction of oxygen raw materials from the processing chamber and trimethyl boron as boron raw materials are added. The concentration of carbon dioxide is set so that the O/C ratio becomes 0.4, and the trimethyl boron is controlled so that the B/C ratio becomes about 0.5 ppm. Specifically, the hydrogen flow rate was set to 383 ccm, the methane flow rate was set to 12.8 sccm, the CO ₂ flow rate was set to 3.2 sccm, and trimethyl boron diluted to 10 ppm with hydrogen was introduced into the processing chamber at a flow rate of 0.5 sccm. . The carbon raw material may be set to 0.1% or more and 10% or less of the total flow rate, and the oxygen flow rate system O/C may be 1 or less. The plasma power is 3.9kW, the gas pressure in the processing chamber is 120 Torr, and the synthesis temperature is 950°C.

The carbon raw material can also be carbon monoxide or ethane, and the oxygen raw material can also be oxygen. In addition, when using carbon monoxide as the carbon raw material, the oxygen raw material may not be used. The plasma power can also be set to 750W or more and 10kW or less, and the pressure in the processing chamber can also be set to 20 Torr or more and 300 Torr or less.

Furthermore, the nitrogen-doped layer is formed by successive growth, and the p-type layer and the p+ layered layer are grown and formed. The nitrogen-doped layer is formed by introducing nitrogen raw materials in addition to hydrogen and carbon raw materials. Specifically, the hydrogen flow rate was set to 374 ccm, the methane flow rate was set to 16 sccm, and the nitrogen diluted to 100 ppm was set to 10 sccm. In addition, when forming the p-type layer, as in the drift layer, it is grown using hydrogen, carbon raw material, oxygen raw material, and boron raw material gas. The p+ layer is formed by introducing hydrogen, carbon raw material, and boron raw material gas. Specifically, the hydrogen flow rate was set to 393 sccm, the methane flow rate was set to 2 sccm, and trimethylboron diluted to 1% was set to 5 sccm and introduced into the processing chamber. The thickness and doping concentration of each layer are as described above.

Next, an etching process is performed on the gate portion and the atoms are flattened on the {111} plane.

Next, a p-type channel layer is formed using a CVD method. The synthesis is performed using hydrogen, carbon raw materials, oxygen raw materials, and boron raw materials. Specifically, the flow rate of hydrogen was set to 783 sccm, the flow rate of methane was set to 10 sccm, the flow rate of carbon dioxide was set to 6 sccm, and the flow rate of trimethylboron diluted to 10 ppm with hydrogen was set to 0.5 sccm.

After the non-diamond layer is removed by heat mixed acid (HNO ₃ : H ₂ SO ₄ =1: 3, 240°C) treatment, the surface is oxidized by UV ozone treatment with a wavelength of 253 nm, and then the lithography method and the peeling method are used On the conductive substrate, a drain electrode serving as an ohmic electrode is formed. In addition, the gate electrode was formed in the channel part using the lithography method and the peeling method. In addition, the CVD method is used to form an insulating film to prevent the gate electrode and the source electrode from being short-circuited. The lithography method and dry etching method are used to expose the contact layer, and the lithography method and the peeling method are used to form the source electrode. The drain electrode and the source electrode are ohmic junctions and are formed by a sputtering method. It is formed in the order of Ti, Mo, and Au, and the film thickness is set to 30 nm, 30 nm, and 100 nm, respectively. The gate electrode of the Schottky junction is formed with a layered structure of Pt and Au and formed by a sputtering method. The thickness of each film is 30 nm and 100 nm. The insulating film was made into length by CVD using TEOS as a source gas, and the film thickness was set to 1 μm.

(Embodiment 4) Hereinafter, this embodiment will be described with reference to FIG. 4. FIG. 4 is a schematic diagram of a simulated vertical structure MESFET (with an internal diode) formed on a (001) wafer of this embodiment.

Compared with FIG. 3, the structure of the device in FIG. 4 does not use a conductive substrate, and the location of the drain electrode is different.

In the device of FIG. 4, the p+ conductive layer 12 is epitaxially grown on the high-quality diamond semi-insulating substrate 11, and on the p+ conductive layer 12, the same as in FIG. 3, according to the high-quality drift layer 13, nitrogen-doped channel layer ( The high resistance layer 14), the p-type layer, and the contact layer 5 are formed in this order. The drain electrode 9 is arranged on the p+ conductive layer 12 and the aforementioned high-quality drift layer side.

(Embodiment 5) Hereinafter, this embodiment will be described with reference to FIG. 5. FIG. 5 is a schematic diagram of a vertical structure MOSFET (with an internal diode attached) formed on a (110) plane wafer according to this embodiment.

Compared with FIG. 1, the structure of the device in FIG. 5 is that the crystal surface of the diamond layered structure is different and the shape of the trench structure is different.

The element of FIG. 5 has a diamond laminated structure composed of a conductive substrate 2, a high-quality drift layer 3, a nitrogen-doped channel layer (high-resistance layer 4), and a contact layer 5. Any layer of the aforementioned diamond layered structure is composed of diamonds. The drain electrode 9 is provided on the conductive substrate 2 and on the opposite side of the high-quality drift layer 3. The source electrode 8 is provided on the contact layer 5 on the opposite side of the high-quality drift layer 3, and a part is directly provided on the nitrogen-doped channel layer (high resistance layer 4). The surface of the nitrogen-doped channel layer is the (110) surface. The trench structure is set in the diamond layered structure, and the sidewalls of the trench structure are atomically flattened (111) planes. The bottom surface of the trench of the trench structure is located in the high-quality drift layer 3, and the sidewall is a trench formed by three layers of the high-quality drift layer 3, the nitrogen-doped channel layer (high resistance layer 4), and the contact layer 5. In the trench of the trench structure, a gate electrode 7 is provided through the insulating film 6. In addition, the gate electrode 7 and the source electrode 8 are insulated by the insulating film 6.

(Embodiment 6) This embodiment will be described below with reference to Fig. 6. FIG. 6 is a schematic diagram of a simulated vertical structure MOSFET (with internal diode attached) formed on a (110) wafer of this embodiment.

Compared with FIG. 2, the structure of the device in FIG. 6 is that the crystal surface of the diamond layered structure is different and the shape of the trench structure is different.

(Embodiment 7) This embodiment will be described below with reference to Fig. 7. FIG. 7 is a schematic diagram of a vertical structure MESFET (with an internal diode) formed on a (110) wafer in this embodiment.

Compared with FIG. 3, the structure of the device in FIG. 7 is different in the crystal plane of the diamond layered structure and the shape of the trench structure is different.

(Embodiment 8) Hereinafter, this embodiment will be described with reference to FIG. 8. FIG. 8 is a schematic diagram of a simulated vertical structure MESFET (with an internal diode) formed on a (110) wafer of this embodiment.

Compared with FIG. 4, the structure of the device in FIG. 8 is that the crystal surface of the diamond layered structure is different and the shape of the trench structure is different.

(Embodiment 9) Hereinafter, this embodiment will be described with reference to FIG. 9. FIG. 9 is a schematic diagram of a vertical structure MESFET formed on a (001)-plane wafer without internally connected diodes according to this embodiment.

Compared with FIG. 3, the structure of the device in FIG. 9 is different only in that there is no internal diode.

The examples disclosed in the above-mentioned embodiments and the like are described in order to facilitate the understanding of the present invention and are not limited by this mode. Industrial availability

The diamond electronic component of the present invention is industrially useful as a power device such as a high-output diamond electronic component having a vertical structure or an analog vertical structure.

2‧‧‧Conductive substrate 3.13‧‧‧High-quality drift layer 4.14‧‧‧High resistance layer 5.15‧‧‧Contact layer 6‧‧‧Insulation film 7‧‧‧Gate electrode 8‧‧‧Source electrode 9‧‧‧Drain electrode 11‧‧‧High-quality diamond semi-insulating substrate 12‧‧‧p+ conductive layer

FIG. 1 is a schematic diagram of a vertical structure MOSFET formed on a (001) wafer according to an embodiment of the present invention. 2 is a schematic diagram of a simulated vertical structure MOSFET formed on a (001) wafer according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a vertical structure MESFET formed on a (001)-plane wafer according to an embodiment of the present invention. 4 is a schematic diagram of a simulated vertical structure MESFET formed on a (001) wafer according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a vertical structure MOSFET formed on a (110) plane wafer according to an embodiment of the present invention. 6 is a schematic diagram of a simulated vertical structure MOSFET formed on a (110) wafer according to an embodiment of the present invention. FIG. 7 is a schematic diagram of a vertical structure MESFET formed on a (110) wafer according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a simulated vertical structure MESFET formed on a (110) wafer according to an embodiment of the present invention. FIG. 9 is a schematic diagram of a vertical structure MESFET formed on a (001)-plane wafer without internally connected diodes according to an embodiment of the present invention.

2‧‧‧Conductive substrate

3‧‧‧High quality drift layer

4‧‧‧High resistance layer

5‧‧‧Contact layer

6‧‧‧Insulation film

7‧‧‧Gate electrode

8‧‧‧Source electrode

9‧‧‧Drain electrode

Claims (10)

A diamond electronic component, characterized in that it has a diamond layered structure, and the diamond layered structure has at least a p+ conductive layer made of diamond, a p-type drift layer made of diamond, and a high layer made of diamond according to the following order. A resistance layer and a p+ contact layer made of diamond; and the above-mentioned diamond layered structure is provided with a trench structure, and the trench sidewall of the above-mentioned trench structure is a {111} plane. The diamond electronic component of claim 1, wherein the aforementioned p+ conductive layer is laminated on a semi-insulating substrate. The diamond electronic component of claim 1 or 2, wherein the high resistance layer is a layer composed of nitrogen-doped diamond. Such as the diamond electronic component of claim 1, wherein a gate electrode is provided on the aforementioned {111} plane. The diamond electronic component of claim 4, wherein the aforementioned gate electrode is a metal-semiconductor junction transistor structure. The diamond electronic component of claim 4, wherein the gate electrode is a transistor structure of a metal-insulating film-semiconductor junction. The diamond electronic component of claim 1 or 2, wherein the p+ conductive layer is provided with a first electrode and the contact layer is provided with a second electrode. A field-effect transistor, which is characterized in that the {111} plane of a nitrogen-doped diamond layer with a diamond layered structure is used in an electric hole channel. A field-effect transistor, characterized in that the gate electrode is arranged on the {111} plane of nitrogen-doped diamond through an insulating film to form a metal-insulating film-semiconductor junction, and the aforementioned {111} plane is used in the hole through Tao. A field-effect transistor, characterized in that the gate electrode is arranged on the {111} plane of nitrogen-doped diamond through a p-type layer to form a metal-semiconductor junction, and the p-type layer with the aforementioned {111} plane is used In the channel.

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