CN104091828B - 一种半导体器件及用于制作高雪崩能量ldmos器件的方法 - Google Patents

一种半导体器件及用于制作高雪崩能量ldmos器件的方法 Download PDF

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CN104091828B
CN104091828B CN201410285973.4A CN201410285973A CN104091828B CN 104091828 B CN104091828 B CN 104091828B CN 201410285973 A CN201410285973 A CN 201410285973A CN 104091828 B CN104091828 B CN 104091828B
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乔伊·迈克格雷格
郑志星
艾瑞克·布劳恩
吉扬永
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明公开了一种半导体器件、LDMOS器件及用于制作高雪崩能量LDMOS器件的方法。该半导体器件包括栅极区、N型漏极区、P型体区和N型源极区，其中体区包括第一体区、第二体区和体接触区，其中第一体区掺杂硼原子，第二体区掺杂硼原子和铟原子，第二体区位于源极区下方并与源极区相邻。该半导体器件、LDMOS器件及用于制作高雪崩能量LDMOS器件的方法具有较低的电阻、较高的雪崩能量和稳定的阈值电压等优点。

Description

一种半导体器件及用于制作高雪崩能量LDMOS器件的方法
技术领域
本发明涉及半导体器件，具体但不限于涉及LDMOS器件及用于提升其雪崩能量的方法。
背景技术
图1的截面图示出了一种现有技术的横向扩散型金属氧化物半导体场效应管(LDMOS)器件100。LDMOS器件100包含漏极，源极，体区和栅极14。其中漏极包含漂移区112和漏极接触区111。源极包含源极区12。LDMOS的体包括体区131和体接触区132。在正常工作中，LDMOS器件100的栅极14和漏极上被施加电压，其中栅极14上的电压将栅极14下的沟道区域反型成与漏极和源极相同的导通类型，在源极和漏极之间形成电流通道。当加载在漏极上的电压过高以致超过了LDMOS器件100的击穿电压时，漂移区112的高碰撞电离区域产生电子-空穴对。其中带负电的电子进入N+漏极接触区111的最高电势区域，带正电的空穴进入P+体接触区132的最低电势区。此雪崩击穿尚不具有破坏能力，当漏极上的高电压移除后，LDMOS器件100将恢复到正常状态。
然而，LDMOS器件100上有寄生的NPN双极型晶体管15。其中LDMOS器件100的源极作为晶体管15的发射极，LDMOS器件100的一部分体区作为晶体管15的基区，LDMOS器件100的漏极作为晶体管15的集电极。当由穿过体区到达P+体接触区132的带正电的空穴导致的电压降足够大时，寄生NPN双极型晶体管15将正向偏置并被导通。一旦NPN晶体管15在某个局部区域被导通，该区域迅速升温，电流增益(beta)增大，硅材料将被溶解。而该破坏将是不可恢复的。
因此需要一种LDMOS器件在寄生双极型晶体管导通前，能尽量多的吸收雪崩电流。
当前，现有的吸收雪崩电流/雪崩能量的方法包括采用较长的沟道和较长的漂流区域。但是这些方式将使得器件的尺寸变大，成本大为增高。
因此，需要一种LDMOS器件至少能解决部分上述提到的问题。
发明内容
为了解决前面描述的一个问题或者多个问题，本发明提出一种半导体器件、LDMOS器件和用于制作高雪崩能量LDMOS器件的方法。
根据本发明的一个方面，一种半导体器件包括：栅极区，包括介质层和导电层；N型漏极区，包括轻掺杂的漂移区和位于漂移区中的重掺杂的漏极接触区，其中漏极区位于栅极区的第一侧；P型体区，与漏极区相邻，体区包括轻掺杂的第一体区，与第一体区相邻的第二体区以及重掺杂的体接触区；以及N型重掺杂的源极区，源极区位于体区中，其中源极区位于栅极区的第二侧；其中第一体区掺杂硼原子，第二体区掺杂硼原子和铟原子，第二体区位于源极区下方并与源极区相邻。在一个实施例中，第二体区向漏极区方向超出源极区边缘。在一个实施例中，第二体区与栅极区边缘对准。在一个实施例中，第二体区位于源极区和体区的结区。在一个实施例中，第二体区的铟原子浓度为每立方厘米1×1018个至5×1018个，第一体区和第二体区的硼原子浓度为每立方厘米1×1018个至5×1018个。在一个实施例中，半导体器件进一步包括：漏电极，耦接漏极接触区；以及源电极，耦接源极区和体接触区。
根据本发明的另一个方面，一种LDMOS器件包括漏极、源极、栅极和体区，其中体区包括第一体区、与源极相邻并位于源极下方的第二体区以及体接触区，其中第二体区掺杂了硼和铟，第一体区和体接触区掺杂了硼而不掺杂铟，第二体区用于降低位于LDMOS器件的沟道与体接触区之间的电阻。在一个实施例中，第二体区中的铟的掺杂浓度为硼的掺杂浓度的1至3倍。在一个实施例中，第二体区的厚度约为100纳米。
根据本发明的又一个方面，一种用于制作高雪崩能量LDMOS器件的方法包括：在半导体基底中注入硼原子以形成LDMOS器件的体区的P型阱；以及在P型阱中注入铟原子，其中铟原子与LDMOS器件的源极相邻并位于源极的下方。在一个实施例中，铟原子的注入能量选择为足够大使得铟原子注入深度到达源极和体区的交界处，同时注入能量选择为足够小使得栅极区能阻挡铟原子穿透。
根据本发明的实施例所提供的半导体器件、LDMOS器件和用于制作高雪崩能量LDMOS器件的方法，具有较低的电阻、较高的雪崩能量和稳定的阈值电压等优点。
附图说明
为了更好的理解本发明，将根据以下附图对本发明的实施例进行描述。这些附图仅用于示例。附图通常仅示出实施例中系统或器件的部分特征。附图的尺寸和比例可与实际的尺寸和比例不相一致。
图1示出了一种现有技术的LDMOS器件100的截面图。
图2示出了根据本发明一实施例的LDMOS器件200的截面图。
图3示出了根据本发明一实施例的正在制作中的LDMOS器件300，用于说明LDMOS器件的制作工艺。
图4A-4H示出了根据本发明一实施例的制作LDMOS器件的方法流程示意图。
图5示出了根据本发明一实施例的LDMOS器件500的示意图。
贯穿所有附图相同的附图标记表示相同或相似的部件或特征。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在下面对本发明的详细描述中，为了更好地理解本发明，描述了大量的细节。然而，本领域技术人员将理解，没有这些具体细节，本发明同样可以实施。为了清晰明了地阐述本发明，本文简化了一些具体结构和功能的详细描述。此外，在一些实施例中已经详细描述过的类似的结构和功能，在其它实施例中不再赘述。尽管本发明的各项术语是结合具体的示范实施例来一一描述的，但这些术语不应理解为局限于这里阐述的示范实施方式。
根据本发明的部分实施例，铟原子被注入在LDMOS器件源极区下方的体区，以增大LDMOS器件在寄生双极型晶体管导通前被吸收的雪崩电流。
图2示出了根据本发明一实施例的LDMOS器件200截面图。LDMOS器件200包括栅极区24，N型漏极区，P型体区和高掺杂N型源极区22。其中栅极区24包括介质层241和导电层242。在一个实施例中，介质层241包括一二氧化硅(SiO2)层。导电层242包括多晶硅层。漏极区位于图示中栅极区24的右侧，漏极区包括轻掺杂的漂移区212和与漂移区毗邻的重掺杂的漏极接触区211。其中“轻掺杂”和“重掺杂”并不用于限定特定的掺杂浓度，仅用于指示在同一实施例中，“重掺杂”的区域掺杂浓度高于“轻掺杂”的区域，如漏极接触区211的N型掺杂浓度高于漂移区212的掺杂浓度。在一个实施例中，同一器件中同一型(如P型或N型)的“重掺杂”与“轻掺杂”分别具有特定的浓度，例如，所有的N型重掺杂区域都具有相同的一浓度，所有N型轻掺杂区都具有相同的另一浓度，其中N型轻掺杂区浓度低于N型重掺杂区浓度。应当知道，“轻掺杂”或“重掺杂”并不仅限于特定的浓度。另外，还应当知道“左边”或“右边”仅针对特定的实施例用于示意，从不同的角度可以对其进行变换。
继续图2的说明，如图2所示，漂移区212从横向上看位于体区231和漏极接触区211之间，其中漏极接触区211耦接至漏电极D。一电极可表现为金属互连、金属层或封装上的电引脚等。LDMOS器件200的体区包括第一体区231，第二体区233和体接触区232。其中第二体区233与第一体区231接触并位于第一体区231内。体接触区232为高掺杂区域。其中第一体区231和体接触区232掺杂了P型硼，第二体区233同时掺杂了硼和铟。第二体区233与源极22接触并位于源极22下方。在一个实施例中，第二体区233中铟的掺杂浓度为第一体区231和第二体区233中硼的掺杂浓度的1至3倍。在所示的实施例中，第二体区233与LDMOS器件200的栅极区24自对准。然而在另一些实施例中，第二体区233也可不与栅极区24自对准。体接触区232和源极区22耦接至源电极S。在另一个实施例中，体接触区232单独耦接至一独立的体电极B。LDMOS器件200的栅极24位于部分体区和漂移区212上。位于栅极区24下方的体区形成LDMOS器件200的沟道234。LDMOS器件200的N型高掺杂源极区22位于体区中，并在图2的示例中位于栅极区24的左边。在所示的实施例中，一个可选的比栅极氧化层241厚的厚氧层26位于栅极24和漏极接触区211之间，以利于进一步提高击穿电压。
图2同时示出了寄生NPN双极型晶体管25，其中LDMOS器件200的源极区22在功能上可视为晶体管25的发射极，LDMOS器件200的漂移区212在功能上可视为晶体管25的集电极，LDMOS器件200的部分体区在功能上作为寄生晶体管25的基区。
当施加于漏极D上的电压过高时，将产生电子-空穴对，其中带正电的空穴汇集至体接触区232。当由此产生的雪崩电流足够大时，将在体区231内至体接触区232方向产生正向压降并导致寄生NPN晶体管25导通。而NPN晶体管的正温度系数将使电流增益发生正反馈并最终导致器件的损毁。
然而，由于源极22下方从沟道区234至体接触区232之间的区域被额外地掺杂了铟，体电阻降低。在一个实施例中，这一区域的铟原子掺杂浓度为每立方厘米1×1018个原子至每立方厘米5×1018个原子，铟原子的掺杂厚度为体区厚度的0.08至0.2倍。在一个实施例中，铟原子掺杂浓度为每立方厘米5×1018个原子，铟原子的掺杂厚度为约100纳米。N+源极区22下方体电阻的降低将提高触发NPN晶体管25导通的雪崩电流，因此，铟原子能用于降低寄生NPN晶体管的电流增益，同时能增大破坏性的正反馈发生的雪崩电流水平。更重要的一点是，如果电流增益能保持在单位值以下，正反馈将不会发生。由于铟原子为重原子，铟原子能用于降低寄生NPN管的电流增益。因此，在给定的掺杂剂量和掺杂能量下，一个重原子如铟能比轻原子如硼能更大程度地破坏硅半导体的晶格。晶格的破坏能降低NPN寄生晶体管25的电流增益(beta)。根据本发明一实施例的实验数据显示，当体区仅有硼掺杂时，寄生NPN晶体管的电流增益峰值为50，而当体区同时掺杂了硼和铟时，寄生NPN晶体管的电流增益能降低到接近单位值(1.0)。
铟原子是深掺杂物质，其电能约等于140meV，而硼原子的电能约等于40meV。铟原子的自由空穴集聚效应低于硼原子。因此，在掺杂铟原子的同时还需要掺杂硼原子。在一个实施例中，在第二体区233，铟原子的掺杂浓度为硼原子掺杂浓度的1至3倍。
在一个实施例中，将在体区和源极区相邻的结区掺杂了铟原子的LDMOS器件和未在该区掺杂铟原子的LDMOS器件相比，器件损坏之前的最大雪崩电流增加至原值的2至10倍。因此LDMOS器件的可靠性得到提高。
图3示出了根据本发明一实施例的正在制作中的LDMOS器件300，用于说明LDMOS器件的制作工艺。在按常规或任意其它的方法制作完LDMOS器件的栅极区24之后，在源极区下方即体区和源极区的结区处掺杂注入铟原子以形成第二体区233。LDMOS器件的体区通过在注入硼原子之外额外注入铟原子形成。在图示的实施例中，铟原子以垂直的角度注入，使得铟原子和栅极区24的边缘自对准。铟原子的注入能量被控制用于调整注入的深度和范围，使得铟原子所在的第二体区233靠近N型源极区22和P型体区的结区(分界处)，而铟原子的能量同时不能过大，使得栅极区24的多晶硅层242能阻挡铟原子穿透栅极区24。在掺杂注入后，铟原子集聚在源极区22的下方。铟原子为P型掺杂物质，因此沟道和体接触区之间的P型体电阻降低，漏极和源极之间的击穿电压提高。
在硅基底中，铟原子的迁移率远低于于其它P型掺杂物质。因此，铟原子将稳定地驻扎在源极区的下方紧邻区域。而假如P型掺杂物质能够迁移到硅基底的表面区域，则LDMOS器件的阈值电压将会受影响并升高。因此，根据本发明实施例的LDMOS器件，在具有高雪崩能量的同时具有稳定的阈值电压。
LDMOS器件300的其它区域如漏极区、第一体区、体接触区未在图3中示出。所述其它区域可在注入铟原子之前制作，也可在注入铟原子之后制作。例如，根据不同的需要、条件或其它的考虑，硼原子可在掺杂铟原子之前注入，也可在掺杂铟原子之后注入。
图中所示的第二体区233底部呈直角的形状仅用于示意。应当知道，掺杂铟原子的第二体区可具有其它任意合适的形状，如具有一定的弧度。
图4A-4H示出了根据本发明一实施例的制作LDMOS器件的方法流程示意图。该方法包括在一半导体基底上注入硼原子以形成如图4D所示的LDMOS器件的体区P型阱，然后往P型阱中注入铟原子，如图4E所示，其中铟注入区域233靠近并位于LDMOS器件源极区22的正下方。在另一个实施例中，铟原子可在注入硼原子前进行注入。
在图4A，在一半导体基底40上注入N型掺杂物质以形成N型阱41。N型阱41通过注入磷、砷、锑中的一种或几种N型掺杂物质形成。在一个实施例中，阱41的N型电荷密度大约为每平方厘米4×1012。半导体基底40可包括初始基底401，制作于初始基底401上的N型掩埋层(NBL)402，以及制作于初始基底401和NBL层402上的上的外延层403。在一个实施例中，外延层403亦为N型掺杂。初始基底401可为N型掺杂，P型掺杂，本征半导体等。然而半导体基底40并不限于图4A所示的结构，其可包含多种不同的形式，其上可包括集成电路、器件或者电路系统。N阱41的一部分区域形成目标LDMOS器件的漂移区。漂移区可通过任意个不同深度的N型掺杂和P型掺杂组合与半导体基底40相隔离。在另一个实施例中，漂移区可通过直接在半导体基底之上制作外延层实现。
在图4B，在N型阱41上制作厚氧区26。为使图式简洁，图4B-4H仅示出了对应于图4A截面图中的部分区域A。从截面图上看，一个MOSFET器件可具有在一个N型阱41中的包括一个体区和两个栅极区的单元，也可包括多个重复的单元。
继续图4B的说明，厚氧区26为场氧区，用于提高LDMOS器件的击穿电压。在一个实施例中，厚氧区26可通过将N型阱41表面氧化，再通过一个掩膜(未示出)将不需要的部位的氧化层刻蚀除去形成。在另一个实施例中，LDMOS器件不包括厚氧区，或LDMOS器件包括一个与厚氧区作用相当的其它结构。
在图4C，将栅极24制作于半导体基底上的表面43上。具体来说，栅极24的一部分位于厚氧区26上。在一个实施例中，制作栅极包括制作二氧化硅层241和在二氧化硅层上制作多晶硅层242。在一个实施例中，在形成二氧化硅层241和多晶硅层242后，制作栅极24可进一步包括通过一个掩膜对二氧化硅层241和多晶硅层242进行刻蚀以形成栅极区。
在图4D，在N型阱41中注入硼原子，以形成LDMOS器件体区的P型阱42。接下来采取热退火将硼原子横向推进至栅极24下方，以形成LDMOS器件的沟道。此步骤形成了N阱41和P阱42的PN结。
在图4E，将铟原子注入到P型阱42。铟原子被注入到LDMOS器件的源极区22下方并与源极区22相邻的区域233。在所示的实施例中，铟原子被垂直注入。然而，在本发明的其它实施例中，铟原子也可以以一定的角度注入。铟原子的注入能量选择为足够高使得铟原子的注入深度达到源极区22和体区的交界处，即结区处，同时铟原子的注入能量也应足够低使得栅极区的多晶硅层242能阻挡铟原子穿透。在一个实施例中，P阱42的厚度d2为约770纳米，铟原子的注入区厚度d1约为100纳米，铟原子注入区域厚度即第二体区厚度d1约为体区厚度d2的约0.13倍。第二体区233的铟原子浓度选择为每立方厘米个数在1×1018个至5×1018个之间。在一个实施例中，第二体区233的铟原子浓度为约每立方厘米5×1018个，硼原子浓度为约每立方厘米2×1018个。然而，上述尺寸关系和浓度仅为示例，本发明实施例中的尺寸和浓度可不同于上述描述的范围。
在图4F，注入高浓度的N型掺杂物质以形成源极区22和漏极接触区211。
在图4G，将高浓度的P型掺杂物质注入以形成体接触区232。
在图4H所示的实施例中，可进一步在源极区22和体接触区232上制作导电层49，将LDMOS器件的源极区和体区短接。导电层49可为多晶硅层，导电孔，金属互连或其它任何可能的形式。
在一个实施例中，N型阱41不在源极区侧进行制作，而仅制作在漏极区侧，其中P型阱42和N型阱41相临制作。在一个实施例中，栅极区的制作在对体区的硼注入完成后进行。
为使描述简洁而不偏离本发明的主题，实施例中的其它一些工艺如形成栅极间隙壁(Spacer)、制作互连或封装在此被省略描述。
应当知道，方法权利要求并没有限定先后顺序，也就是说当一个方法权利要求包括步骤A和B时，步骤A可先于步骤B进行，步骤A也可后于步骤B进行。
在一个实施例中，LDMOS器件将与双极型晶体管-互补金属氧化物半导体场效应管-扩散型金属氧化物半导体场效应管(BCD)工艺中的双极型器件和互补金属氧化物半导体场效应管器件一起制作在同一半导体基底上。
图5示出了根据本发明一实施例的LDMOS器件500的示意图。与图2中的LDMOS器件相比，LDMOS器件500的掺杂了铟原子的第二体区533向漏极212方向略微超出N型源极区22的边缘。在一个实施例中，铟原子超出源极区22的原因为铟原子先于栅极间隙壁制作，而源极区后于栅极间隙壁制作。
需要声明的是，上述发明内容及具体实施方式意在证明本发明所提供技术方案的实际应用，不应解释为对本发明保护范围的限定。本领域技术人员在本发明的精神和原理内，当可作各种修改、等同替换、或改进。本发明的保护范围以所附权利要求书为准。

Claims (11)

1.一种半导体器件，包括：
栅极区，包括介质层和导电层；
N型漏极区，包括轻掺杂的漂移区和位于漂移区中的重掺杂的漏极接触区，其中漏极区位于栅极区的第一侧；
P型体区，与漏极区相邻，体区包括轻掺杂的第一体区，与第一体区相邻的第二体区以及重掺杂的体接触区；以及
N型重掺杂的源极区，源极区位于体区中，其中源极区位于栅极区的第二侧；其中
第一体区掺杂硼原子，第二体区掺杂硼原子和铟原子，第二体区位于源极区下方并与源极区相邻。
2.如权利要求1所述的半导体器件，其中第二体区向漏极区方向超出源极区边缘。
3.如权利要求1所述的半导体器件，其中第二体区与栅极区边缘对准。
4.如权利要求1所述的半导体器件，其中第二体区位于源极区和体区的结区。
5.如权利要求1所述的半导体器件，其中第二体区的铟原子浓度为每立方厘米1×1018个至5×1018个，第一体区和第二体区的硼原子浓度为每立方厘米1×1018个至5×1018个。
6.如权利要求1所述的半导体器件，进一步包括：
漏电极，耦接漏极接触区；以及
源电极，耦接源极区和体接触区。
7.一种横向扩散型金属氧化物半导体场效应管(LDMOS)器件，包括漏极、源极、栅极和体区，其中体区包括第一体区、与源极相邻并位于源极下方的第二体区以及体接触区，其中第二体区掺杂了硼和铟，第一体区和体接触区掺杂了硼而不掺杂铟，第二体区用于降低LDMOS器件的沟道与体接触区之间的电阻。
8.如权利要求7所述的LDMOS器件，其中第二体区中的铟的掺杂浓度为硼的掺杂浓度的1至3倍。
9.如权利要求8所述的LDMOS器件，其中第二体区的厚度为100纳米。
10.一种用于制作高雪崩能量LDMOS器件的方法，包括：
在半导体基底中注入硼原子以形成LDMOS器件的体区的P型阱；以及
在P型阱中注入铟原子，其中铟原子与LDMOS器件的源极相邻并位于源极的下方。
11.如权利要求10所述的方法，其中铟原子的注入能量选择为足够大使得铟原子注入深度到达源极和体区的交界处，同时注入能量选择为足够小使得栅极区能阻挡铟原子穿透。
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