CN104067252B - 用于高速同步串行接口(hsi)的多通道高速接口及相关系统和方法 - Google Patents

用于高速同步串行接口(hsi)的多通道高速接口及相关系统和方法 Download PDF

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Publication number
CN104067252B
CN104067252B CN201380006412.XA CN201380006412A CN104067252B CN 104067252 B CN104067252 B CN 104067252B CN 201380006412 A CN201380006412 A CN 201380006412A CN 104067252 B CN104067252 B CN 104067252B
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hsi
path
electronic device
additional
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CN104067252A (zh
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A·沙哈姆
A·吉尔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
CN201380006412.XA 2012-01-25 2013-01-25 用于高速同步串行接口(hsi)的多通道高速接口及相关系统和方法 Active CN104067252B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/358,312 US20130191569A1 (en) 2012-01-25 2012-01-25 Multi-lane high-speed interfaces for high speed synchronous serial interface (hsi), and related systems and methods
US13/358,312 2012-01-25
PCT/US2013/023308 WO2013112946A1 (en) 2012-01-25 2013-01-25 Multi-lane high-speed interfaces for high speed synchronous serial interface (hsi), and related systems and methods

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CN104067252A CN104067252A (zh) 2014-09-24
CN104067252B true CN104067252B (zh) 2017-03-01

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US (1) US20130191569A1 (https=)
EP (1) EP2807572B1 (https=)
JP (1) JP6066224B2 (https=)
KR (1) KR101680733B1 (https=)
CN (1) CN104067252B (https=)
BR (1) BR112014018288A8 (https=)
ES (1) ES2573285T3 (https=)
HU (1) HUE028765T2 (https=)
IN (1) IN2014CN04802A (https=)
WO (1) WO2013112946A1 (https=)

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WO2019070361A1 (en) * 2017-10-03 2019-04-11 Qualcomm Incorporated MULTI-LINE BUS WITH DYNAMIC ADJUSTMENT SHARED BY MULTIPROTOCOL DEVICES
US12530307B2 (en) * 2023-02-17 2026-01-20 Nxp Usa, Inc. Elastic buffers

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CN102129395A (zh) * 2011-03-02 2011-07-20 智比特信息技术（镇江）有限公司 通过单一硬件串口实现多进程控制的通讯方法

Also Published As

Publication number Publication date
CN104067252A (zh) 2014-09-24
HUE028765T2 (en) 2016-12-28
JP2015510182A (ja) 2015-04-02
ES2573285T3 (es) 2016-06-07
BR112014018288A8 (pt) 2017-07-11
EP2807572A1 (en) 2014-12-03
EP2807572B1 (en) 2016-03-23
KR101680733B1 (ko) 2016-11-29
WO2013112946A1 (en) 2013-08-01
IN2014CN04802A (https=) 2015-09-18
BR112014018288A2 (https=) 2017-06-20
US20130191569A1 (en) 2013-07-25
KR20140125816A (ko) 2014-10-29
JP6066224B2 (ja) 2017-01-25

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