CN104062937B - Sixty-four-way low-speed high-precision analog acquisition realizing method - Google Patents
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Abstract
The invention provides a sixty-four-way low-speed high-precision analog acquisition realizing method and belongs to the field of testing control. The method aims to solve the problems that acquisition interfaces of an existing data acquisition card are often small in number, and the acquisition precision is not high. According to the method, an operational amplifier circuit, an AD conversion chip, an FPGA and eight multiplexers are adopted for realization, sixty-four-way analog data are connected into input ends of the eight multiplexers through the operational amplifier circuit together, eight-way data output ends of all the multiplexers are connected with the eight-way data input end of the AD conversion chip, the data and control signal output end of the AD conversion chip is connected with the data and control signal input end of the FPGA, and gating signal input ends of all the multiplexers are respectively connected with one gating signal output end of the FPGA. The sixty-four-way low-speed high-precision analog acquisition realizing method is logically controlled through the FPGA.
Description
Technical field
The present invention relates to a kind of multi pass acquisition method, belong to testing and control field.
Background technology
In space equipment is tested, test equipment needs to enter the equipment under test output multi-channel analogue signal of different model and function
Row high precision collecting, as pressure, temperature, flow, sound, electrical quantity etc., existing data collecting card
Acquisition interface is the most fewer, and acquisition precision is the highest.
Summary of the invention
The invention aims to solve existing data collecting card acquisition interface the most fewer, and the highest the asking of acquisition precision
Topic, it is provided that a kind of 64 road low-speed highly precise analog acquisition implementation methods.
64 road low-speed highly precise analog acquisition implementation methods of the present invention, the method uses discharge circuit, AD conversion core
Sheet, FPGA and 8 MUX realize, and the input of 8 MUX accesses 64 commonly through discharge circuit
Road analog data, 8 circuit-switched data outfans of every MUX are all connected with 8 circuit-switched data inputs of AD conversion chip,
The data of AD conversion chip and the data of control signal outfan FPGA and control signal input are connected, every multichannel choosing
The gating signal input selecting device is connected with a gating signal outfan of FPGA respectively；
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA, are carrying out logic initialization
After, the detailed process that fpga logic controls is:
State 1: whether currently selected logical MUX switches complete, if switching complete, then proceeds to state 2；If not
Switch complete, then continue state 1；
State 2: send AD conversion sign on, and maintain a clock cycle high level, then proceed to state 3
State 3: judging that the analog digital conversion of AD conversion chip is the most complete, if changing complete, proceeding to state；If not changing
Complete, continue state 3；
State 4:FPGA is successively read the data of 8 channel acquisition of AD conversion chip, the data of collection is write successively
Enter in the RAM of 128 bytes in built-in for FPGA 16；After completing to read the data that a piece of MUX is transmitted,
Proceed to state 5；
State 5: judge whether to need MUX is carried out passage switching, if desired carry out passage switching, then by RAM
Interior storage address is incremented by, and controls a piece of MUX under gating, carries out passage switching, then proceeds to state 1.
Advantages of the present invention: the present invention is be applicable to different field tests, using the teaching of the invention it is possible to provide high-precision multi-path analog acquisition,
Different testing requirements can be met according to actual testing and debugging parameter simultaneously, control logic and possess portability.Realize 64 tunnels
The collection of analog quantity；Acquisition precision reaches 16.Functional circuit and the configuration logic of the present invention are applicable to different buses and connect
Mouthful.
Accompanying drawing explanation
Fig. 1 is the hardware elementary diagram that 64 road low-speed highly precise analog acquisition implementation methods of the present invention relate to；
Fig. 2 is logic control state diagram；
Fig. 3 is the flow chart of 64 road low-speed highly precise analog acquisition implementation methods of the present invention.
Detailed description of the invention
Detailed description of the invention one: present embodiment is described below in conjunction with Fig. 1 to Fig. 3,64 road low speed described in present embodiment
High-precision analog gathers implementation method, and the method uses discharge circuit 1, AD conversion chip 3, FPGA4 and 8 multichannels
Selector 2 realizes, and the input of 8 MUX 2 accesses 64 tunnel analog datas commonly through discharge circuit 1,
8 circuit-switched data outfans of every MUX 2 are all connected with 8 circuit-switched data inputs of AD conversion chip 3, and AD turns
Change the data of chip 3 and the data of control signal outfan FPGA4 and control signal input is connected, every multi-path choice
The gating signal input of device 2 is connected with a gating signal outfan of FPGA4 respectively；
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA4, and carrying out, logic is initial
After change, the detailed process of FPGA4 logic control is:
State 1: whether currently selected logical MUX 2 switches complete, if switching complete, then proceeds to state 2；If
Do not switch complete, then continue state 1；
State 2: send AD conversion sign on, and maintain a clock cycle high level, then proceed to state 3
State 3: judge that the analog digital conversion of AD conversion chip 3 is the most complete, if changing complete, proceeds to state 4；If not
Change complete, continue state 3；
State 4:FPGA4 is successively read the data of 8 channel acquisition of AD conversion chip 3, by the data of collection successively
In the RAM of 16 128 bytes that write FPGA4 is built-in；Complete to read the data of a piece of MUX 2 transmission
After, proceed to state 5；
State 5: judge whether to need MUX 2 is carried out passage switching, if desired carries out passage switching, then will
Memory ram storage address is incremented by, and controls a piece of MUX 2 under gating, carries out passage switching, then proceeds to state
1。
The trigger clock of AD conversion chip 3 and 8 MUX 2 is connected in a common clock signal, shape
State changes and occurs in the clock edge transition moment.
This method as master controller, uses Verilog language to be programmed, it is adaptable to different buses connects based on FPGA
Mouthful.Hardware principle is as shown in Figure 1.
The MUX that MUX 2 uses model to be MAX308.
The AD conversion chip that AD conversion chip 3 uses model to be AD7606.
Use AD7606 as the ADC of signals collecting.AD7606 is 16 8 Channel Synchronous sampling modulus data collections
System (DAS).Each device equal built-in analog input clamper protection, second order frequency overlapped-resistable filter, tracking hold amplifier,
16 Charge scaling gradual approaching A/D converters (ADC), flexibly digital filter, 2.5V reference voltage source,
Reference voltage buffering and high speed serialization and parallel interface.AD7606 uses 5V power supply to power, and can process ± 10V and ± 5V
True bipolar input signal, is simultaneously entered clamping protective circuit and can tolerate up to ± the voltage of 16.5V.No matter with what
Planting sample frequency work, the simulation input impedance of AD7606 is 1M Ω.It uses single supply working method, has sheet
Interior filtering and high input impedance, therefore without driving operational amplifier and outside bipolar power supply.In circuit use voltage with
Being made up of AD8677 with device, this amplifier performance is similar with common OP07 amplifier, and indices is better than OP07.
In order to realize the collection of 64 tunnel analog quantitys, use 8 MAX308 and 1 AD7606 design simulation Acquisition Circuit,
Each for modulus conversion chip AD7606 input channel is carried out × 8 extensions, it is possible to achieve the collection to 1～64 tunnel analog quantitys,
Sample rate is about 25kSPS.
MAX308 is a high precision of Maxim company of U.S. production, the analog multiplexer chip of 8 passages,
Its conducting resistance is less than 100 Ω, and each interchannel conducting resistance difference is less than 5 Ω, and passage is less than 250ns switching time,
Power consumption is less than 300 μ w, single phase power supply 5～30V, and two-phase powers ± 5～± 20V.
This analog quantity acquisition circuit, can conveniently realize the collection of 1～64 low frequency amounts, has extraordinary motility, general
Property and transplantability.In actual applications, when acquisition channel number difference, the control logic of FPGA only need to be changed therein
The address parameter of MAX308 is arranged.
In order to meet distinct device testing requirement, AD7606 and MAX308 controls logic and uses state machine architecture, all
Trigger clock be all connected in a common clock signal, whether the changing of state can only occur in the saltus step of clock and prolong
Moment.This control logic is made up of 5 limited state machines, state diagram as in figure 2 it is shown, flow chart as shown in Figure 3.
Detailed description of the invention two: embodiment one is described further by present embodiment, and logic initialization is arranged by host computer
The program parameter channel_count of FPGA4 completes, it is achieved gating the sheet number of MUX 2, the storage of RAM
Address space and the initialization of sample rate:
During channel_count=1, the sheet number of gating MUX 2 is 1, and the memory address space of RAM is 1h～8h,
Sample rate is 200kSPS；
During channel_count=2, the sheet number of gating MUX 2 is 2, and the memory address space of RAM is 1h～16h,
Sample rate is 100kSPS；
During channel_count=3, the sheet number of gating MUX 2 is 3, and the memory address space of RAM is 1h～24h,
Sample rate is 66kSPS；
During channel_count=4, the sheet number of gating MUX 2 is 4, and the memory address space of RAM is 1h～32h,
Sample rate is 50kSPS；
During channel_count=5, the sheet number of gating MUX 2 is 5, and the memory address space of RAM is 1h～40h,
Sample rate is 40kSPS；
During channel_count=6, the sheet number of gating MUX 2 is 6, and the memory address space of RAM is 1h～48h,
Sample rate is 33kSPS；
During channel_count=7, the sheet number of gating MUX 2 is 7, and the memory address space of RAM is 1h～56h,
Sample rate is 28kSPS；
During channel_count=8, the sheet number of gating MUX 2 is 8, and the memory address space of RAM is 1h～64h,
Sample rate is 25kSPS.
The sheet number of gating MUX 2 is different, i.e. port number is different, 1 corresponding 8 passage of MUX 2, then originally
Embodiment at most can realize the data acquisition of 64 passages.
Claims (4)
1.64 road low-speed highly precise analog acquisition implementation method, it is characterised in that the method uses discharge circuit (1), AD
Conversion chip (3), FPGA (4) and 8 MUX (2) realize, the input of 8 MUX (2)
End accesses 64 tunnel analog datas commonly through discharge circuit (1), and 8 circuit-switched data outfans of every MUX (2) are equal
It is connected with 8 circuit-switched data inputs of AD conversion chip (3), the data of AD conversion chip (3) and control signal outfan
The data of FPGA (4) and control signal input are connected, the gating signal input of every MUX (2) respectively with
One gating signal outfan of FPGA (4) is connected；
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA (4), are carrying out at the beginning of logic
After beginningization, the detailed process of FPGA (4) logic control is:
State 1: whether currently selected logical MUX (2) switches complete, if switching complete, then proceeds to state 2；
If not switching complete, then continue state 1；
State 2: send AD conversion sign on, and maintain a clock cycle high level, then proceed to state 3；
State 3: judging that the analog digital conversion of AD conversion chip (3) is the most complete, if changing complete, proceeding to state 4；If
Do not change complete, continue state 3；
State 4:FPGA (4) is successively read the data of 8 channel acquisition of AD conversion chip (3), the number that will gather
According in the RAM writing 128 bytes in built-in for FPGA (4) 16 successively；Complete to read a piece of MUX (2)
After the data of transmission, proceed to state 5；
State 5: judge whether to need MUX (2) is carried out passage switching, if desired carries out passage switching, then will
Memory ram storage address is incremented by, and controls a piece of MUX (2) under gating, carries out passage switching, then proceeds to state
1；
The program parameter channel_count that logic initialization is arranged FPGA (4) by host computer completes, it is achieved gating multichannel
The sheet number of selector (2), the memory address space of RAM and the initialization of sample rate:
During channel_count=1, the sheet number of gating MUX (2) is 1, and the memory address space of RAM is 1h～8h,
Sample rate is 200kSPS；
During channel_count=2, the sheet number of gating MUX (2) is 2, and the memory address space of RAM is 1h～16h,
Sample rate is 100kSPS；
During channel_count=3, the sheet number of gating MUX (2) is 3, and the memory address space of RAM is 1h～24h,
Sample rate is 66kSPS；
During channel_count=4, the sheet number of gating MUX (2) is 4, and the memory address space of RAM is 1h～32h,
Sample rate is 50kSPS；
During channel_count=5, the sheet number of gating MUX (2) is 5, and the memory address space of RAM is 1h～40h,
Sample rate is 40kSPS；
During channel_count=6, the sheet number of gating MUX (2) is 6, and the memory address space of RAM is 1h～48h,
Sample rate is 33kSPS；
During channel_count=7, the sheet number of gating MUX (2) is 7, and the memory address space of RAM is 1h～56h,
Sample rate is 28kSPS；
During channel_count=8, the sheet number of gating MUX (2) is 8, and the memory address space of RAM is 1h～64h,
Sample rate is 25kSPS.
64 road low-speed highly precise analog acquisition implementation method the most according to claim 1, it is characterised in that AD conversion core
The trigger clock of sheet (3) and 8 MUX (2) is connected in a common clock signal, and state changes to be sent out
Raw in the clock edge transition moment.
64 road low-speed highly precise analog acquisition implementation method the most according to claim 1, it is characterised in that multi-path choice
Device (2) uses model to be the MUX of MAX308.
64 road low-speed highly precise analog acquisition implementation method the most according to claim 1, it is characterised in that AD conversion core
Sheet (3) uses model to be the AD conversion chip of AD7606.
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| CN109062095A (en) * | 2018-07-27 | 2018-12-21 | 杭州电子科技大学 | A kind of high-precision multi-channel data acquisition board and acquisition method |
| CN109411436B (en) * | 2018-09-05 | 2021-04-30 | 湖北三江航天险峰电子信息有限公司 | 64-channel analog quantity acquisition BGA (ball grid array) packaging chip |
| CN109388087B (en) * | 2018-11-27 | 2021-06-18 | 湖北三江航天险峰电子信息有限公司 | Multichannel analog acquisition SIP chip |
| CN110955628B (en) * | 2019-11-18 | 2022-11-29 | 上海卫星工程研究所 | Analog quantity telemetering acquisition method and acquisition system based on sampling address |
| CN111796726A (en) * | 2020-07-07 | 2020-10-20 | 中航华东光电有限公司 | Signal receiving circuit of capacitive touch screen |
| CN113311222A (en) * | 2021-05-21 | 2021-08-27 | 中国科学院微小卫星创新研究院 | Satellite analog signal acquisition system |
| CN113341845A (en) * | 2021-06-29 | 2021-09-03 | 北京微纳星空科技有限公司 | Automatic data acquisition method and system |
| CN113504847A (en) * | 2021-07-16 | 2021-10-15 | 中航华东光电有限公司 | FPGA-based capacitive touch screen signal sampling system and method |
| CN113568347A (en) * | 2021-07-27 | 2021-10-29 | 中电科思仪科技股份有限公司 | High-speed digital logic acquisition circuit and acquisition method based on ADC |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103488112A (en) * | 2013-09-29 | 2014-01-01 | 成都天奥测控技术有限公司 | Multichannel data acquisition instrument based on time synchronization |
| CN103647901A (en) * | 2013-12-24 | 2014-03-19 | 中国科学院半导体研究所 | Low-cost image data collection transmission system free of external storage and based on field programmable gate array (FPGA) |
| CN103777529A (en) * | 2012-10-24 | 2014-05-07 | 北京强度环境研究所 | Fast varying signal collector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020045952A1 (en) * | 2000-10-12 | 2002-04-18 | Blemel Kenneth G. | High performance hybrid micro-computer |
-
2014
- 2014-07-09 CN CN201410325776.0A patent/CN104062937B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103777529A (en) * | 2012-10-24 | 2014-05-07 | 北京强度环境研究所 | Fast varying signal collector |
| CN103488112A (en) * | 2013-09-29 | 2014-01-01 | 成都天奥测控技术有限公司 | Multichannel data acquisition instrument based on time synchronization |
| CN103647901A (en) * | 2013-12-24 | 2014-03-19 | 中国科学院半导体研究所 | Low-cost image data collection transmission system free of external storage and based on field programmable gate array (FPGA) |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的数据采集与处理技术的研究;孔利东;《中国优秀硕士论文全文数据库》;20071115;第2.2节第1-2段、第3.1.1节第1段、第3.1.2节第1-2,5段、第3.2.1节第1段、第3.2.2节第1-3段，图2-7、3-6、3-7、3-8、3-9、3-10 * |
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