CN109388087B - Multichannel analog acquisition SIP chip - Google Patents
Multichannel analog acquisition SIP chip Download PDFInfo
- Publication number
- CN109388087B CN109388087B CN201811427453.7A CN201811427453A CN109388087B CN 109388087 B CN109388087 B CN 109388087B CN 201811427453 A CN201811427453 A CN 201811427453A CN 109388087 B CN109388087 B CN 109388087B
- Authority
- CN
- China
- Prior art keywords
- resistor
- analog
- operational amplifier
- chip
- conversion module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention discloses a multichannel analog acquisition SiP chip, which comprises an AD conversion module, an operational amplification module and a gating module; the operational amplification module comprises at least one operational amplifier connected with the AD conversion module, the gating module comprises analog gates with the same number as the operational amplifiers, and one analog gate is correspondingly connected with one operational amplifier; the analog gate is used for receiving a plurality of paths of analog signals and controlling to output one path of analog signal to the operational amplifier according to a gating address sent by the external controller; the operational amplifier adjusts the voltage amplitude of the analog signal according to a preset amplification factor, so that the voltage value of the analog signal is matched with the input voltage of the AD conversion module; the AD conversion module converts the analog signals output by the operational amplifiers into digital signals; the invention packages the analog gate, the operational amplifier and the AD analog-to-digital converter into the SiP chip in a bare chip form through the SiP, reduces the system volume and meets the requirements of miniaturization and low power consumption.
Description
Technical Field
The invention belongs to the technical field of analog quantity acquisition, and particularly relates to a multichannel analog quantity acquisition SiP chip which can realize acquisition of not less than 64 paths of analog quantity signals.
Background
The analog quantity is a physical quantity in which a variable continuously changes within a certain range, and the analog signal is information represented by the continuously changing physical quantity, and the amplitude, frequency, and phase of the signal continuously change with time. The analog signals are distributed at all corners of the nature, and the method has the advantages of intuition, easy detection, poor controllability and weak anti-interference capability. Compared with analog signals, the digital signals have higher anti-interference capability, longer transmission distance and small distortion amplitude in the transmission process. Thus, in general, analog signals need to be collected in and converted to digital signals for processing by subsequent equipment.
In the field of analog signal sampling, the situation that tens of paths of output analog signals of sensors need to be sampled sometimes, the sampling frequency does not need to be very high, generally below tens of kSPS, a multi-path analog quantity acquisition device capable of realizing tens of paths of analog signal sampling is mainly realized in the field of ICs by two modes, one mode is realized by a specific IC chip, such as an AD7656 chip (sampling rate 250kSPS, six channels, synchronous sampling, bipolar 16/14/12 bit ADC), an AD7606 chip (sampling rate 200kSPS, 8/6/4 channels, 16 bits, bipolar input, synchronous sampling ADC) and the like of AD company, and domestic manufacturers also produce devices with the same functions as the AD 7656; or a general ARM (such as STM32F4XX of ST company) and DSP (such as TMS320F28XX of TI company) device is adopted to integrate the AD function, but the sampling number is not more than 16 channels generally. For sampling requirements of more channels such as 32, 64, 96 channels and the like, only repeated stacking of a large number of circuits is needed, so that the circuit area of a printed board is increased, the pin number of a control chip and matched peripheral circuits are greatly increased, and the circuit implementation is not practical.
Disclosure of Invention
Aiming at least one defect or improvement requirement in the prior art, the invention provides a multichannel analog acquisition SiP chip, aiming at solving the problems of few sampling paths, large volume and complex circuit of the existing multichannel analog acquisition device.
In order to achieve the above object, according to an aspect of the present invention, there is provided a multi-channel analog acquisition SiP chip, including an AD conversion module, an operational amplification module, and a gating module; the operational amplification module comprises at least one operational amplifier connected with the AD conversion module, the gating module comprises analog gates with the same number as the operational amplifiers, and one analog gate is correspondingly connected with one operational amplifier;
the analog gate is used for receiving a plurality of paths of analog signals and controlling to output one path of analog signals to the operational amplifier according to a gating address sent by the external controller; the operational amplifier is used for adjusting the voltage amplitude of the analog signal according to a preset amplification factor so as to enable the voltage value of the analog signal to be matched with the input voltage of the AD conversion module; the AD conversion module is used for receiving the analog signals output by the operational amplifiers and converting the analog signals into digital signals;
the AD conversion module, the operational amplifier and the analog gate are integrated to form a SiP chip through SiP packaging in a bare chip mode.
Preferably, the multichannel analog acquisition SiP chip further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5;
one end of the first resistor R1 is connected with the signal output end of the analog gate, and the other end of the first resistor R1 is connected with the input positive end of the operational amplifier and the first end of the second resistor R2; the second end of the second resistor R2 is connected with the analog ground;
the first end of the third resistor R3 is connected with the analog ground, and the second end of the third resistor R3 is connected with the negative input end of the operational amplifier and the first end of the fourth resistor R4; a second end of the fourth resistor R4 is connected to the output end of the operational amplifier and a first end of the fifth resistor R5; a first end of the fifth resistor R5 is connected to the output end of the operational amplifier, and a second end is connected to the signal input end of the AD conversion module.
Preferably, in the multi-channel analog quantity acquisition SiP chip, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the operational amplifier form an in-phase adjustable amplification circuit, and the amplification factor of the in-phase adjustable amplification circuit and the resistance relationship of each resistor are as follows:
F＝R2/(R1+R2)(1+R4/R3)
the amplification factor is adjusted by adjusting the resistance of any one or more of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4.
Preferably, in the multi-channel analog quantity acquisition SiP chip, the AD conversion module outputs the digital signal in a serial or parallel manner.
Preferably, the multichannel analog acquisition SiP chip further includes a built-in 2.5V reference source, and the reference source is provided by the inside of the AD conversion module and is used for providing a reference voltage during AD conversion.
Preferably, the multi-channel analog acquisition SiP chip has a power interface for connecting an external power supply and an external reference source.
Preferably, the AD conversion module of the multi-channel analog acquisition SiP chip is implemented by a 6-channel bipolar 16-bit ADC bare chip SAD7656 in chongqing 24.
Preferably, the operational amplifier of the multichannel analog acquisition SiP chip is implemented by using TLE2071ID bare chip of TI corporation.
Preferably, the analog gate of the multi-channel analog acquisition SiP chip is implemented by a 16-channel ADG506A bare chip from AD.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) according to the multichannel analog quantity acquisition SiP chip, the analog gate, the operational amplifier and the AD analog-to-digital converter are integrated into the SiP chip in a full-bare chip form through the SiP packaging technology, 32, 64 and 96 sampling channels can be realized, time-sharing gating, conditioning and sampling are carried out on multi-channel bipolar analog quantity signals, meanwhile, the utilization rate of hardware resources is improved, the system volume is reduced, and the requirements of miniaturization and low power consumption are met; compared with the traditional repeated stacking of a plurality of AD7606 chips, the SiP chip provided by the invention has the advantages that the number of IO pins is reduced by about 73% or 81%, the circuit area is reduced by 72%, the circuit simplification effect is obvious, and the universality of the chip is improved.
(2) According to the multichannel analog quantity acquisition SiP chip provided by the invention, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the operational amplifier form an in-phase adjustable amplifying circuit, the amplification factor of each channel to signals can be adjusted by adjusting the resistance value of any one or more of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, so that the voltage value of an analog quantity signal is matched with the voltage of an AD converter, the SiP chip can be adapted to analog signals in various voltage ranges, and the universality of the chip is improved.
Drawings
Fig. 1 is a schematic circuit structure diagram of a multi-channel analog acquisition SiP chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an in-phase adjustable amplifying circuit provided by an embodiment of the invention;
fig. 3 is a top view of the inside of a multi-channel analog acquisition SiP chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a schematic circuit structure diagram of a multi-channel analog quantity acquisition SiP chip according to an embodiment of the present invention, and as shown in fig. 1, the multi-channel analog quantity acquisition SiP chip includes an AD conversion module, an operational amplification module, and a gating module; the operational amplification module comprises four operational amplifiers connected with the AD conversion module, the gating module comprises four analog gates, one analog gate is correspondingly connected with one operational amplifier to form a sampling channel, and the number of paths of analog quantity signals which can be collected by each sampling channel is equal to the number of channels built in the analog gate;
the analog gate used in this embodiment is an ADG506A bare chip from AD corporation, which is a single chip CMOS analog multiplexer with 16 channels built in. It switches one of the 16 inputs to the common output based on the state of the 4 binary addresses and one enable input. The ADG506A bare chip has high switching speed and low on-resistance characteristics, and the device parameters are as follows: the maximum rated power voltage is 44V, the analog model range is VSS-VDD, single/double power supplies are used for supplying power, the wide power voltage range is 10.8V-16.5V, the power consumption is 28 muA (maximum value), and the leakage is 20pA (typical value).
An analog gate can receive 16 analog signals at the same time, an external control chip (such as an FPGA) respectively sends a gating address to each analog gate, and after the analog gates receive the gating addresses, one path of analog quantity signals collected by a gating channel corresponding to the gating addresses are sent to an operational amplifier;
the operational amplifier is used for amplifying or reducing the analog signal output by the analog gate according to a preset amplification factor; the AD conversion module is used for receiving the analog signals output by each operational amplifier and converting the analog signals into digital signals;
the operational amplifier adopted in the embodiment is a TLE2071ID bare chip of TI company, is a J-FET type amplifier, and has the following device parameters: the slew rate is 45V/us, the gain bandwidth product is 10MHz, the bias current is 20pA, the offset voltage is 490uV, and the working power supply voltage is 2.7V-5.5V. The AD conversion module is a 6-channel bipolar 16-bit ADC bare chip SAD7656 produced by Chongqing 24, and the output of the AD conversion module can be serial output or parallel output, and the sampling rate of each channel is 250 ksps.
When the voltage of the analog quantity signal output by the analog gate is not matched with the input voltage range of the AD conversion module, the analog quantity signal needs to be amplified or reduced so as to enable the voltage value of the analog quantity signal to be matched with the AD conversion module; considering the circuit generalization, in the case that the analog voltage signal has a low amplitude (e.g. millivolt level) or a large amplitude (e.g. more than 10V), the amplification factor of the analog signal needs to be adjusted according to the requirement. In order to realize adjustable amplification factor of the analog quantity signal of each channel, the embodiment further provides a feedback circuit, wherein the feedback circuit and the operational amplifier jointly form an in-phase adjustable amplification circuit so as to realize adjustment of the amplification factor of the analog quantity signal; fig. 2 is a circuit structure diagram of the in-phase adjustable amplifying circuit, and as shown in fig. 2, the in-phase adjustable amplifying circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and an operational amplifier TLE2071 ID;
one end of the first resistor R1 is connected with the signal output end of the analog gate, and the other end of the first resistor R1 is connected with the input positive end 3 of the operational amplifier and the first end of the second resistor R2; the second end of the second resistor R2 is connected with the analog ground; the first end of the third resistor R3 is connected with the analog ground, and the second end is connected with the negative input end 2 of the operational amplifier and the first end of the fourth resistor R4; a second end of the fourth resistor R4 is connected to the output terminal 6 of the operational amplifier and a first end of the fifth resistor R5; a first terminal of the fifth resistor R5 is connected to the output terminal 6 of the operational amplifier, and a second terminal is connected to the signal input terminal of the AD conversion module. The positive power supply terminal 7 of the operational amplifier is connected with the anode of a 15V power supply, and the negative power supply terminal 4 is connected with the cathode of the 15V power supply.
The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the operational amplifier form an in-phase adjustable amplifying circuit, and the relationship between the signal amplification factor of the in-phase adjustable amplifying circuit and the resistance of each resistor is as follows:
F＝R2/(R1+R2)(1+R4/R3)
the amplification factor can be adjusted by adjusting the resistance of one or more of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4.
After receiving a control signal (including a chip selection signal, a range selection, a read-write enable and the like) sent by an external control chip (such as an FPGA), an AD conversion module starts a sampling and AD conversion function, collects an analog signal output by an operational amplifier and converts the analog signal into a digital signal, and sequentially outputs the digital signal according to a channel sequence in an SPI serial or parallel mode; the AD conversion module has 6 channels (U1-U6), the reserved U5 and U6 channels are used for realizing the path number expansion of the sampling channels, and the sampling speed of the sampling channels is 250kHz of the SAD7656 chip.
Further, the multichannel analog quantity acquisition SIP chip provided by this embodiment is also internally provided with a 2.5V reference source, which is provided by the AD conversion module and is used for providing a reference voltage during AD conversion.
Further, in the multi-channel analog quantity acquisition SIP chip provided by the embodiment, the packaged SIP chip has a power interface for connecting an external power supply and an external reference source.
The AD converter, the operational amplifier and the analog gate are integrated to form an SIP chip through SIP packaging in a bare chip mode; fig. 3 is a top view of the inside of a multi-channel analog quantity acquisition SIP chip provided by an embodiment of the present invention, and as shown in fig. 3, the bare chip is bonded to the upper surface of the substrate in a tiled manner, where U1, U2, U3, and U4 represent bare operational amplifier chips, U5, U6, U7, and U8 represent bare analog gate chips, and U9 represents bare ADC chips; bonding points formed by an etching process are arranged on the upper surface of the substrate, and each bare chip is bonded on the substrate through the non-conductive patch glue and then bonded on the bonding points of the substrate in a gold wire bonding mode; the lower surface of the substrate is provided with solder balls in a ball grid array, and the molding compound coats the upper surface of the substrate and the bare chips on the substrate. The pitch, diameter and height of the solder balls are 1.00mm, 0.50mm and 0.38mm respectively. 289-pin solder balls are led out of the SIP chip, and the overall external dimension of the SIP chip is 18mm multiplied by 1.53mm (including the height of the solder balls).
If the AD7606 of 8 channels is adopted to realize 64-channel analog quantity acquisition sampling, 8 AD7606 chips are needed, the number of data and control pins of each AD7606 chip is about 12 (serial output) or 26 (parallel output), the number of pins needed by the matched control chip is 96 (serial output) or 208 (parallel output), and the number of spare IO pins of most ARM, DSP and FPGA is difficult to reach the number; secondly, the repeated use of AD7606 chips occupies a large area of the printed board, the area of one AD7606 chip is 12mm to 12mm, and the area of 8 AD7606 chips is at least 1152mm2。
By adopting the 64-channel analog quantity acquisition SIP chip, the number of IO pins only needs 26 (serial output) or 40 (parallel output), and the area of the packaged SiP chip is only 18mm by 18mm to 324mm2. Compared with the scheme adopting 8 AD7606 chips, the number of IO pins is reduced by about 73% or 81%, and the circuit area is reduced by 72%. The simplification effect on the circuit is obvious. Precision of sampling the analog quantity: the absolute error of measurement is within 0.01V (± 5V mode); the relative error of measurement under the full scale is about two thousandths, and the power consumption is only 0.5W.
Compared with the existing multichannel analog acquisition device, the multichannel analog acquisition SiP chip integrates the analog gate, the operational amplifier and the AD analog-to-digital converter into the SiP chip in a bare chip form through the SiP packaging technology, can realize 32, 64 and 96 sampling channels, and carries out time-sharing gating, conditioning and sampling on a plurality of paths of bipolar analog signals, and simultaneously improves the utilization rate of hardware resources, reduces the volume of the system, and meets the requirements of miniaturization and low power consumption; compared with the traditional repeated stacking of a plurality of AD7606 chips, the SiP chip provided by the invention has the advantages that the number of IO pins is reduced by about 73% or 81%, the circuit area is reduced by 72%, the circuit simplification effect is obvious, and the universality of the chip is improved.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A multichannel analog acquisition SiP chip is characterized by comprising an AD conversion module, an operational amplification module and a gating module; the operational amplification module comprises at least one operational amplifier connected with the AD conversion module, the gating module comprises analog gates with the same number as the operational amplifiers, and one analog gate is correspondingly connected with one operational amplifier;
the analog gate is used for receiving a plurality of paths of analog signals and controlling to output one path of analog signals to the operational amplifier according to a gating address sent by the external controller; the operational amplifier is used for adjusting the voltage amplitude of the analog signal according to a preset amplification factor so as to enable the voltage value of the analog signal to be matched with the input voltage of the AD conversion module; the AD conversion module is used for receiving the analog signals output by the operational amplifiers and converting the analog signals into digital signals;
the AD conversion module, the operational amplifier and the analog gate are packaged by SiP in a bare chip mode to form a SiP chip, the bare chip is bonded on the upper surface of the substrate in a tiled mode, the upper surface of the substrate is provided with bonding points formed by an etching process, and each bare chip is bonded on the substrate through a non-conductive patch adhesive and is bonded on the bonding points through a gold wire bonding mode; solder balls are distributed on the lower surface of the substrate in a ball grid array mode, and the molding compound coats the upper surface of the substrate and the bare chips on the substrate;
the circuit also comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;
one end of the first resistor R1 is connected with the signal output end of the analog gate, and the other end of the first resistor R1 is connected with the input positive end of the operational amplifier and the first end of the second resistor R2; the second end of the second resistor R2 is connected with the analog ground;
the first end of the third resistor R3 is connected with the analog ground, and the second end of the third resistor R3 is connected with the negative input end of the operational amplifier and the first end of the fourth resistor R4; a second end of the fourth resistor R4 is connected to the output end of the operational amplifier and a first end of the fifth resistor R5; a first end of the fifth resistor R5 is connected with the output end of the operational amplifier, and a second end of the fifth resistor R5 is connected with the signal input end of the AD conversion module;
the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the operational amplifier form an in-phase adjustable amplifying circuit, and the relationship between the amplification factor of the in-phase adjustable amplifying circuit and the resistance value of each resistor is as follows:
F＝R2/(R1+R2)(1+R4/R3)
the amplification factor is adjusted by adjusting the resistance of any one or more of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4.
2. The multi-channel analog acquisition SiP chip of claim 1, wherein the AD conversion module outputs digital signals in a serial or parallel manner.
3. The multi-channel analog acquisition SiP chip of claim 1, further comprising a built-in 2.5V reference source provided by the AD conversion module for providing a reference voltage for AD conversion.
4. The multi-channel analog acquisition SiP chip of claim 1, wherein the packaged SiP chip has a power interface for connecting an external power supply and an external reference source.
5. The multi-channel analog acquisition SiP chip of claim 1, wherein the AD conversion module is implemented using a 6-channel bipolar 16-bit ADC bare chip SAD7656 at chongqing 24.
6. The multi-channel analog acquisition SiP chip of claim 1, wherein the operational amplifier is implemented using TLE2071ID bare chip of TI corporation.
7. The multi-channel analog acquisition SiP chip of claim 1, wherein the analog gate is implemented using a 16-channel ADG506A bare chip from AD corporation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811427453.7A CN109388087B (en) | 2018-11-27 | 2018-11-27 | Multichannel analog acquisition SIP chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811427453.7A CN109388087B (en) | 2018-11-27 | 2018-11-27 | Multichannel analog acquisition SIP chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109388087A CN109388087A (en) | 2019-02-26 |
| CN109388087B true CN109388087B (en) | 2021-06-18 |
Family
ID=65429755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811427453.7A Active CN109388087B (en) | 2018-11-27 | 2018-11-27 | Multichannel analog acquisition SIP chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109388087B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111796726A (en) * | 2020-07-07 | 2020-10-20 | 中航华东光电有限公司 | Signal receiving circuit of capacitive touch screen |
| CN112415578B (en) * | 2020-10-20 | 2022-08-09 | 山东大学 | Wireless sensor and method for acquiring tunnel seismic wave signals |
| CN113922821B (en) * | 2021-09-28 | 2024-03-01 | 中国电子科技集团公司第二十四研究所 | Hybrid multichannel time-sharing telemetry acquisition circuit and telemetry device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2721676A1 (en) * | 1977-05-13 | 1978-11-23 | Hans T Noeller | Flashlight spectrophotometer for clinical analyses - uses xenon tube and pulse amplitude detector circuit for absorption and attenuated total reflection measurements |
| US6650614B1 (en) * | 2000-10-30 | 2003-11-18 | Cirrus Logic, Inc. | Optical disk pickup using current mode signal exchanges and systems and methods using the same |
| CN2838130Y (en) * | 2005-07-15 | 2006-11-15 | 中国科学院空间科学与应用研究中心 | Power supply unit for online monitored satellite equipment |
| CN100442657C (en) * | 2006-12-31 | 2008-12-10 | 南京航空航天大学 | Programme-controlled gain charge amplifier based on computer system bus |
| CN101453197B (en) * | 2007-11-30 | 2011-01-26 | 瑞昱半导体股份有限公司 | Gain regulating circuit |
| CN202321576U (en) * | 2011-11-22 | 2012-07-11 | 合肥工大高科信息科技股份有限公司 | Belt type conveyor filed controller with various work modes |
| CN102929836B (en) * | 2012-08-17 | 2015-06-10 | 中国科学院空间科学与应用研究中心 | Special ASIC (Application Specific Integrated Circuit) chip system for spaceflight |
| US9716479B2 (en) * | 2013-02-08 | 2017-07-25 | Analog Devices, Inc. | Variable gain amplifier |
| CN104062937B (en) * | 2014-07-09 | 2017-01-11 | 哈尔滨诺信科技有限公司 | Sixty-four-way low-speed high-precision analog acquisition realizing method |
| CN207008375U (en) * | 2017-08-07 | 2018-02-13 | 长安大学 | A kind of multi-point grid array pressure acquisition circuit |
| CN108681518B (en) * | 2018-05-21 | 2020-12-11 | 中国科学院国家空间科学中心 | Low-speed IO time division multiplexing system |
-
2018
- 2018-11-27 CN CN201811427453.7A patent/CN109388087B/en active Active
Non-Patent Citations (1)
| Title |
|---|
| 十一款可变增益放大器电路设计原理图详解;电子发烧友;《电子发烧友论坛》;20180326;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109388087A (en) | 2019-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109388087B (en) | Multichannel analog acquisition SIP chip | |
| CN101701971A (en) | High-precision multichannel analog signal source | |
| CN104113341A (en) | 12-bit intermediate-rate successive approximation type analog-digital converter | |
| CN105071806A (en) | High-linearity input signal buffer applied to high-speed analog-digital converter | |
| CN201749387U (en) | V/I conversion circuit | |
| CN100589319C (en) | Power amplifier temperature compensation device and method | |
| CN201682485U (en) | Analog-to-digital combined data acquisition device | |
| CN106330122A (en) | FPGA (field programmable gate array) based analog signal acquisition automatic gain circuit | |
| CN201181220Y (en) | Micro-current amplifier for spacing | |
| CN102111125A (en) | Signal generator with current output type amplifying unit | |
| CN204967796U (en) | Be applied to high -speed adc's high linearity incoming signal buffer | |
| CN201813361U (en) | Analog-to-digital conversion (ADC) module calibrating device and mobile terminal | |
| CN103647557B (en) | Adc circuit, ic for energy metering and electric energy metered system | |
| CN204314406U (en) | Module test fixture and programmable interface circuit thereof | |
| Tong et al. | A 0.6 V 10 bit 120 kS/s SAR ADC for implantable multichannel neural recording | |
| CN112992827B (en) | Multi-channel signal multiplexing packaging structure | |
| CN111245371B (en) | Power mixer, radio frequency circuit, device and equipment | |
| CN104300981B (en) | At a high speed, high precision image signal analog to digital conversion circuit | |
| CN207475514U (en) | A kind of Frequency and Amplitude calibrates circuit | |
| CN202503480U (en) | Low distortion gain-controlled circuit | |
| CN201517926U (en) | Redundant analog quantity current signal distributor | |
| CN101726657B (en) | Device for measurement and conversion of voltage signal | |
| CN111669128A (en) | Weak signal sampling circuit for electrochemical detection | |
| CN206117640U (en) | High accuracy analog signal sampling circuit | |
| CN201956979U (en) | PGA circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |