CN104062937A - Sixty-four-way low-speed high-precision analog acquisition realizing method - Google Patents
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Abstract
The invention provides a sixty-four-way low-speed high-precision analog acquisition realizing method and belongs to the field of testing control. The method aims to solve the problems that acquisition interfaces of an existing data acquisition card are often small in number, and the acquisition precision is not high. According to the method, an operational amplifier circuit, an AD conversion chip, an FPGA and eight multiplexers are adopted for realization, sixty-four-way analog data are connected into input ends of the eight multiplexers through the operational amplifier circuit together, eight-way data output ends of all the multiplexers are connected with the eight-way data input end of the AD conversion chip, the data and control signal output end of the AD conversion chip is connected with the data and control signal input end of the FPGA, and gating signal input ends of all the multiplexers are respectively connected with one gating signal output end of the FPGA. The sixty-four-way low-speed high-precision analog acquisition realizing method is logically controlled through the FPGA.
Description
Technical field
The present invention relates to a kind of multi pass acquisition method, belong to test control field.
Background technology
In space equipment test, testing apparatus need to be carried out high precision collecting to the equipment under test output multi-channel simulating signal of different model and function, as pressure, temperature, flow, sound, electrical quantity etc., existing data collecting card acquisition interface is often fewer, and acquisition precision is not high.
Summary of the invention
The present invention seeks in order to solve existing data collecting card acquisition interface often fewerly, and the not high problem of acquisition precision, provides a kind of 64 road low-speed highly precise analog acquisition implementation methods.
64 road low-speed highly precise analog acquisition implementation methods of the present invention, the method adopts discharge circuit, AD conversion chip, FPGA and 8 MUX realize, the input end of 8 MUX accesses 64 tunnel simulated datas by discharge circuit jointly, 8 circuit-switched data output terminals of every MUX are all connected with 8 circuit-switched data input ends of AD conversion chip, the data of the data of AD conversion chip and control signal output terminal FPGA and control signal input end are connected, the gating signal input end of every MUX is connected with a gating signal output terminal of FPGA respectively,
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA, are carrying out after logic initialization, and the detailed process of fpga logic control is:
State 1: it is complete whether the current MUX being strobed is switched, if switch completely, proceeds to state 2; If do not switch completely, continue state 1;
State 2: send AD conversion sign on, and maintain a clock period high level, then proceed to state 3
State 3: whether the analog to digital conversion that judges AD conversion chip is complete, if change completely, proceeds to state; If do not change complete, continuation state 3;
State 4:FPGA reads the data of 8 passages collections of AD conversion chip successively, the data of collection is write successively in the RAM of 16 built-in 128 bytes of FPGA; Complete after the data that read the transmission of a slice MUX, proceed to state 5;
State 5: judge whether to carry out passage switching to MUX, if desired carry out passage switching, memory ram is stored up to address increment, and control a slice MUX under gating, carry out passage switching, then proceed to state 1.
Advantage of the present invention: the present invention is applicable to, in different field tests, can provide high-precision multi-path analog acquisition, can adjust parameter according to reality test simultaneously and meet different testing requirements, and steering logic possesses portability.Realize the collection of 64 tunnel analog quantitys; Acquisition precision reaches 16.Functional circuit of the present invention and configuration logic are applicable to different bus interface.
Brief description of the drawings
Fig. 1 is the hardware elementary diagram that 64 road low-speed highly precise analog acquisition implementation methods of the present invention relate to;
Fig. 2 is logic control constitutional diagram;
Fig. 3 is the process flow diagram of 64 road low-speed highly precise analog acquisition implementation methods of the present invention.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1 to Fig. 3, 64 road low-speed highly precise analog acquisition implementation methods described in present embodiment, the method adopts discharge circuit 1, AD conversion chip 3, FPGA4 and 8 MUX 2 realize, the input end of 8 MUX 2 accesses 64 tunnel simulated datas by discharge circuit 1 jointly, 8 circuit-switched data output terminals of every MUX 2 are all connected with 8 circuit-switched data input ends of AD conversion chip 3, the data of the data of AD conversion chip 3 and control signal output terminal FPGA4 and control signal input end are connected, the gating signal input end of every MUX 2 is connected with a gating signal output terminal of FPGA4 respectively,
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA4, are carrying out after logic initialization, and the detailed process of FPGA4 logic control is:
State 1: it is complete whether the current MUX being strobed 2 is switched, if switch completely, proceeds to state 2; If do not switch completely, continue state 1;
State 2: send AD conversion sign on, and maintain a clock period high level, then proceed to state 3
State 3: whether the analog to digital conversion that judges AD conversion chip 3 is complete, if change completely, proceeds to state 4; If do not change complete, continuation state 3;
State 4:FPGA4 reads the data of 8 passages collections of AD conversion chip 3 successively, the data of collection is write successively in the RAM of 16 built-in 128 bytes of FPGA4; Complete and read after the data that a slice MUX 2 transmits, proceed to state 5;
State 5: judge whether to carry out passage switching to MUX 2, if desired carry out passage switching, memory ram is stored up to address increment, and control a slice MUX 2 under gating, carry out passage switching, then proceed to state 1.
The trigger clock of 3 and 8 MUX 2 of AD conversion chip is connected in a common clock signal, and state change occurs in the clock hopping edge moment.
This method as master controller, adopts Verilog language to programme based on FPGA, is applicable to different bus interface.Hardware principle as shown in Figure 1.
It is the MUX of MAX308 that MUX 2 adopts model.
It is the AD conversion chip of AD7606 that AD conversion chip 3 adopts model.
Adopt the ADC of AD7606 as signals collecting.AD7606 is 16 8 Channel Synchronous sampling modulus data acquisition system (DAS)s (DAS).The all built-in analog input clamper protections of each device, second order frequency overlapped-resistable filter, follow the tracks of hold amplifier, 16 electric charge reallocation gradual approaching A/D converters (ADC), digital filter, 2.5V reference voltage source, reference voltage buffering and high speed serialization and parallel interface flexibly.AD7606 adopts 5V Power supply, can process ± 10V and ± the true bipolarity input signal of 5V, input clamping protective circuit simultaneously and can tolerate the voltage of be up to ± 16.5V.No matter with which kind of sample frequency work, the analog input impedance of AD7606 is 1M Ω.It adopts single supply working method, has filtering and high input impedance in sheet, therefore without driving operational amplifier and outside bipolar power supply.The voltage follower adopting in circuit is made up of AD8677, and this amplifier performance and common OP07 amplifier are similar, and indices is better than OP07.
In order to realize the collection of 64 tunnel analog quantitys, adopt 8 MAX308 and 1 AD7606 design simulation Acquisition Circuit, each modulus conversion chip AD7606 input channel has been carried out × 8 expansions, can realize the collection to 1～64 tunnel analog quantity, sampling rate is about 25kSPS.
MAX308 is a high precision of Maxim company of U.S. production, the analog multiplexer chip of 8 passages, its conducting resistance is less than 100 Ω, each interchannel conducting resistance difference is less than 5 Ω, passage is less than 250ns switching time, power consumption is less than 300 μ w, single phase power supply 5～30V, two-phase power supply ± 5～± 20V.
This analog quantity acquisition circuit, can conveniently realize the collection of 1～64 low frequency amount, has extraordinary dirigibility, versatility and transplantability.In actual applications, in the time that acquisition channel number is different, the steering logic of FPGA only need be changed the address parameter setting of MAX308 wherein.
In order to meet distinct device testing requirement, AD7606 and MAX308 steering logic adopt state machine structure, and all trigger clocks are all connected in a common clock signal, and whether the changing of state can only occur in the saltus step time delay of clock and carve.This steering logic is made up of 5 limited state machines, and as shown in Figure 2, process flow diagram as shown in Figure 3 in constitutional diagram.
Embodiment two: present embodiment is described further embodiment one, the program parameter channel_count that logic initialization arranges FPGA4 by host computer completes, and realizes sheet number, the memory address space of RAM and the initialization of sampling rate of gating MUX 2:
When channel_count=1, the memory address space that the sheet number of gating MUX 2 is 1, RAM is 1h～8h, and sampling rate is 200kSPS;
When channel_count=2, the memory address space that the sheet number of gating MUX 2 is 2, RAM is 1h～16h, and sampling rate is 100kSPS;
When channel_count=3, the memory address space that the sheet number of gating MUX 2 is 3, RAM is 1h～24h, and sampling rate is 66kSPS;
When channel_count=4, the memory address space that the sheet number of gating MUX 2 is 4, RAM is 1h～32h, and sampling rate is 50kSPS;
When channel_count=5, the memory address space that the sheet number of gating MUX 2 is 5, RAM is 1h～40h, and sampling rate is 40kSPS;
When channel_count=6, the memory address space that the sheet number of gating MUX 2 is 6, RAM is 1h～48h, and sampling rate is 33kSPS;
When channel_count=7, the memory address space that the sheet number of gating MUX 2 is 7, RAM is 1h～56h, and sampling rate is 28kSPS;
When channel_count=8, the memory address space that the sheet number of gating MUX 2 is 8, RAM is 1h～64h, and sampling rate is 25kSPS.
The sheet of gating MUX 2 is counted difference, i.e. port number difference, and 1 corresponding 8 passage of MUX 2, present embodiment can realize at most the data acquisition of 64 passages.
Claims (5)
1.64 road low-speed highly precise analog acquisition implementation methods, it is characterized in that, the method adopts discharge circuit (1), AD conversion chip (3), FPGA (4) and 8 MUX (2) realize, the input end of 8 MUX (2) is jointly by discharge circuit (1) access 64 tunnel simulated datas, 8 circuit-switched data output terminals of every MUX (2) are all connected with 8 circuit-switched data input ends of AD conversion chip (3), the data of the data of AD conversion chip (3) and control signal output terminal FPGA (4) and control signal input end are connected, the gating signal input end of every MUX (2) is connected with a gating signal output terminal of FPGA (4) respectively,
Described 64 road low-speed highly precise analog acquisition implementation methods are carried out logic control by FPGA (4), are carrying out after logic initialization, and the detailed process of FPGA (4) logic control is:
State 1: it is complete whether the current MUX being strobed (2) is switched, if switch completely, proceeds to state 2; If do not switch completely, continue state 1;
State 2: send AD conversion sign on, and maintain a clock period high level, then proceed to state 3
State 3: whether the analog to digital conversion that judges AD conversion chip (3) is complete, if change completely, proceeds to state 4; If do not change complete, continuation state 3;
State 4:FPGA (4) reads the data of 8 passages collections of AD conversion chip (3) successively, the data of collection is write successively in the RAM of 16 built-in 128 bytes of FPGA (4); Complete after the data that read a slice MUX (2) transmission, proceed to state 5;
State 5: judge whether to carry out passage switching to MUX (2), if desired carry out passage switching, memory ram is stored up to address increment, and control a slice MUX (2) under gating, carry out passage switching, then proceed to state 1.
2. 64 road low-speed highly precise analog acquisition implementation methods according to claim 1, it is characterized in that, the trigger clock of AD conversion chip (3) and 8 MUX (2) is connected in a common clock signal, and state change occurs in the clock hopping edge moment.
3. 64 road low-speed highly precise analog acquisition implementation methods according to claim 1, it is characterized in that, the program parameter channel_count that logic initialization arranges FPGA (4) by host computer completes, and realizes sheet number, the memory address space of RAM and the initialization of sampling rate of gating MUX (2):
When channel_count=1, the memory address space that the sheet number of gating MUX (2) is 1, RAM is 1h～8h, and sampling rate is 200kSPS;
When channel_count=2, the memory address space that the sheet number of gating MUX (2) is 2, RAM is 1h～16h, and sampling rate is 100kSPS;
When channel_count=3, the memory address space that the sheet number of gating MUX (2) is 3, RAM is 1h～24h, and sampling rate is 66kSPS;
When channel_count=4, the memory address space that the sheet number of gating MUX (2) is 4, RAM is 1h～32h, and sampling rate is 50kSPS;
When channel_count=5, the memory address space that the sheet number of gating MUX (2) is 5, RAM is 1h～40h, and sampling rate is 40kSPS;
When channel_count=6, the memory address space that the sheet number of gating MUX (2) is 6, RAM is 1h～48h, and sampling rate is 33kSPS;
When channel_count=7, the memory address space that the sheet number of gating MUX (2) is 7, RAM is 1h～56h, and sampling rate is 28kSPS;
When channel_count=8, the memory address space that the sheet number of gating MUX (2) is 8, RAM is 1h～64h, and sampling rate is 25kSPS.
4. 64 road low-speed highly precise analog acquisition implementation methods according to claim 1, is characterized in that, MUX (2) adopts the MUX that model is MAX308.
5. 64 road low-speed highly precise analog acquisition implementation methods according to claim 1, is characterized in that, AD conversion chip (3) adopts the AD conversion chip that model is AD7606.
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| CN105607520A (en) * | 2016-02-19 | 2016-05-25 | 北京空间飞行器总体设计部 | Remote measurement acquisition control device for general extensible spacecraft |
| CN108036872A (en) * | 2017-11-23 | 2018-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of multi-channel high-accuracy temperature acquisition method |
| CN109062095A (en) * | 2018-07-27 | 2018-12-21 | 杭州电子科技大学 | A kind of high-precision multi-channel data acquisition board and acquisition method |
| CN109388087A (en) * | 2018-11-27 | 2019-02-26 | 湖北三江航天险峰电子信息有限公司 | A kind of multichannel analog amount acquisition SIP chip |
| CN109411436A (en) * | 2018-09-05 | 2019-03-01 | 湖北三江航天险峰电子信息有限公司 | A kind of 64 road analog acquisition chip bgas |
| CN110955628A (en) * | 2019-11-18 | 2020-04-03 | 上海卫星工程研究所 | Analog quantity telemetering acquisition method and acquisition system based on sampling address |
| CN111796726A (en) * | 2020-07-07 | 2020-10-20 | 中航华东光电有限公司 | Signal receiving circuit of capacitive touch screen |
| CN113311222A (en) * | 2021-05-21 | 2021-08-27 | 中国科学院微小卫星创新研究院 | Satellite analog signal acquisition system |
| CN113341845A (en) * | 2021-06-29 | 2021-09-03 | 北京微纳星空科技有限公司 | Automatic data acquisition method and system |
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| CN113568347A (en) * | 2021-07-27 | 2021-10-29 | 中电科思仪科技股份有限公司 | High-speed digital logic acquisition circuit and acquisition method based on ADC |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105607520B (en) * | 2016-02-19 | 2018-05-01 | 北京空间飞行器总体设计部 | A kind of spacecraft telemetry-acquisition control device of generic Extensible |
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| CN108036872A (en) * | 2017-11-23 | 2018-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of multi-channel high-accuracy temperature acquisition method |
| CN109062095A (en) * | 2018-07-27 | 2018-12-21 | 杭州电子科技大学 | A kind of high-precision multi-channel data acquisition board and acquisition method |
| CN109411436B (en) * | 2018-09-05 | 2021-04-30 | 湖北三江航天险峰电子信息有限公司 | 64-channel analog quantity acquisition BGA (ball grid array) packaging chip |
| CN109411436A (en) * | 2018-09-05 | 2019-03-01 | 湖北三江航天险峰电子信息有限公司 | A kind of 64 road analog acquisition chip bgas |
| CN109388087A (en) * | 2018-11-27 | 2019-02-26 | 湖北三江航天险峰电子信息有限公司 | A kind of multichannel analog amount acquisition SIP chip |
| CN110955628A (en) * | 2019-11-18 | 2020-04-03 | 上海卫星工程研究所 | Analog quantity telemetering acquisition method and acquisition system based on sampling address |
| CN111796726A (en) * | 2020-07-07 | 2020-10-20 | 中航华东光电有限公司 | Signal receiving circuit of capacitive touch screen |
| CN113311222A (en) * | 2021-05-21 | 2021-08-27 | 中国科学院微小卫星创新研究院 | Satellite analog signal acquisition system |
| CN113341845A (en) * | 2021-06-29 | 2021-09-03 | 北京微纳星空科技有限公司 | Automatic data acquisition method and system |
| CN113504847A (en) * | 2021-07-16 | 2021-10-15 | 中航华东光电有限公司 | FPGA-based capacitive touch screen signal sampling system and method |
| CN113568347A (en) * | 2021-07-27 | 2021-10-29 | 中电科思仪科技股份有限公司 | High-speed digital logic acquisition circuit and acquisition method based on ADC |
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