CN104051327A - 用于半导体封装的表面处理方法和装置 - Google Patents

用于半导体封装的表面处理方法和装置 Download PDF

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CN104051327A
CN104051327A CN201310334939.7A CN201310334939A CN104051327A CN 104051327 A CN104051327 A CN 104051327A CN 201310334939 A CN201310334939 A CN 201310334939A CN 104051327 A CN104051327 A CN 104051327A
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substrate
metal level
nano wire
integrated circuit
layer
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CN104051327B (zh
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张志鸿
邓桔程
郭庭豪
陈映予
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了用于半导体封装的表面处理方法和装置。在一个实施例中，对导电层的表面进行处理以生成粗化表面。在一个实例中，在导电层的表面上形成纳米线。在铜导电层的情况中，纳米线可以包含CuO层。在另一个实例中，在导电层的表面上形成络合物。可以使用例如硫醇和亚磷酸三甲酯形成该络合物。

Description

用于半导体封装的表面处理方法和装置
本申请要求下列临时提交的美国专利申请的权益：申请序列号为61/776,544，提交日为2013年3月11日，标题为“Surface Treatment Methodand Apparatus for Semiconductor Packaging”，将该申请结合于此作为参考。
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种用于半导体封装的表面处理方法和装置。
背景技术
半导体器件用于各种电子应用，举例来说，诸如个人电脑、手机、数码相机、以及其他电子设备。通常通过在半导体衬底上方按顺序沉积材料的绝缘层或介电层、导电层和半导体层，并且使用光刻对各种材料层进行图案化以在其上形成电路部件和元件来形成半导体器件。
通常在单个半导体晶圆上生产数十个或数百个集成电路。通过沿着划线切割集成电路来分割个体管芯。然后，举例来说，单独地、以多芯片模式、或者以其他封装类型对个体管芯进行封装。
用于半导体器件的一种封装类型被称为迹线上凸块（BOT）封装。在半导体晶圆的管芯上形成焊料凸块，并且分割管芯。使用焊料回流工艺将管芯或“倒装芯片”连接或焊接到BOT封装件上的迹线。可以将模塑底部填充物（MUF）分散到半导体芯片和封装件部件之间的间隙中以减少焊料凸块或焊球中的碎裂，其中碎裂通常是由热应力导致的。封装件部件可以是包括用于在相对面之间布线电信号的金属连接件的中介层。可以通过直接金属接合、焊料接合等将芯片接合至中介层。在一些情况中，将管芯接合至较大的衬底，然后将该较大的衬底切割成个体封装件。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种形成半导体器件的方法，所述方法包括：提供衬底，所述衬底具有与所述衬底相连接的集成电路管芯，在所述衬底上形成有金属层；对所述金属层的露出表面进行处理，所述处理生成具有纳米线的粗化表面；以及在所述金属层上方施加模塑料或底部填充材料。
在所述方法中，所述金属层包含Cu，并且所述纳米线包含CuO。
在所述方法中，包含CuO的所述纳米线增大表面粗糙度。
在所述方法中，表面粗糙度RA大于50nm，所述纳米线的高度大于120nm，并且所述纳米线的间距小于500nm。
在所述方法中，所述金属层包含介于所述CuO和所述Cu之间的自然氧化物层。
在所述方法中，所述处理包括在所述金属层上方形成络合物层。
在所述方法中，所述处理包括将所述衬底放置在化学浴中。
在所述方法中，所述化学浴包含硫醇或亚磷酸三甲酯。
在所述方法中，所述化学浴包括在乙醇中冲洗。
在所述方法中，所述处理包括在包含NaClO2、NaOH、Na3PO4*12H2O和H2O的溶液中的化学浴。
在所述方法中，所述处理包括加热到85℃至95℃之间的温度的化学浴。
根据本发明的另一方面，提供了一种半导体器件，包括：衬底；位于所述衬底上的金属层；以及在所述金属层上形成的氧化物层，所述氧化物层具有从所述氧化物层的表面延伸的纳米线。
在所述半导体器件中，所述金属层包含Cu，并且所述氧化物层包含CuO。
在所述半导体器件中，Cu2O层介于所述Cu和所述CuO之间。
在所述半导体器件中，所述纳米线具有小于约500nm的间距。
在所述半导体器件中，平均粗糙度为约60nm。
在所述半导体器件中，所述纳米线具有30nm至140nm的高度。
根据本发明的又一方面，提供了一种半导体器件，包括：衬底；位于所述衬底上的金属层；以及形成在所述金属层上的络合物层，所述络合物层比所述金属层的硫含量更高。
在所述的半导体器件中，所述络合物层比所述金属层的碳含量更高。
在所述的半导体器件中，所述金属层包含铜。
附图说明
为了更充分地理解实施例及其优点，现将结合附图所进行的下列描述作为参考，其中：
图1至图6示出形成实施例的各个中间步骤；
图7A至图7C示出根据一个实施例的对表面的化学处理；
图8A至图8B示出根据实施例使用络合物的键合界面；
图9示出位于导电层上的络合物；以及
图10是示出形成实施例的方法的流程图。
具体实施方式
在下面详细论述本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是制造和使用实施例的示例性具体方式，而不是限制本发明的范围。
首先参照图1，示出了根据一个实施例的多个集成电路管芯102和衬底104的截面图。集成电路管芯102可以是用于具体应用的任何适合的集成电路管芯。例如，集成电路管芯102可以是诸如DRAM、SRAM、NVRAM、和/或APU等的存储器芯片；逻辑电路；或类似物。应当注意到集成电路管芯102可以是相同的或不同的。例如，在一个实施例中，所有的集成电路管芯102都是相同的，诸如是存储器芯片。在另一个实施例中，集成电路管芯102可以是不同的，诸如一个是存储器芯片，一个是逻辑芯片。也可以使用其他配置。
集成电路管芯102包括在其上形成的导电凸块106，其可以由共晶焊料、无铅焊料等形成。图1示出导电凸块106在集成电路管芯102上形成是用于举例说明的目的。在其他实施例中，导电凸块106可以在衬底104上形成。
衬底104可以是任何适合的衬底，诸如1/2/1层压衬底、4层层压衬底、中介层、封装衬底、另一管芯/晶圆、印刷电路板、高密度互连件等。衬底104可以包括沿着衬底104的第一面的第一组电连接件108和沿着衬底104的相对第二面的第二组电连接件112。在衬底104中可以包括通孔（TV）（未示出）以在第一组电连接件108和第二组电连接件112中的对应电连接件之间提供电连接，并因此在衬底104的一面上安装的集成电路管芯102和位于衬底104的相对第二面上的第二组电连接件112之间提供电连接。衬底104可以进一步包括一条或多条再分布线（RDL）以实现不同的引脚配置和/或更大的电连接。
在一个实施例中，将使用迹线上凸块（BOT）技术将集成电路管芯102接合至衬底104。通常，BOT技术利用导电凸块（例如金属或焊料凸块）直接接合到在诸如封装衬底、中介层等另一衬底上形成的窄金属迹线，而非接合到比相应的连接金属迹线具有更大宽度的金属焊盘上。BOT结构需要较小的芯片面积，并且BOT结构的制造成本低。在该实施例中，第一组电连接件108可以包含在衬底104上形成的迹线，其中，焊料凸块106将接合至相对应的第一组电连接件108，如下文参照图2更详细论述的。
衬底104可以进一步包括导电层110，诸如铜箔。导电层110可以起到例如接地屏蔽的作用。还应当注意到本文所包含的附图已被简化用于举例说明的目的。例如，集成电路管芯102上的导电凸块106可以包括凸块下金属（UBM）结构、柱结构或其他结构。作为另一实例，还可以包括各种钝化层、聚合物层等。
图2示出根据一个实施例在接合工艺之后的集成电路管芯102和衬底104。集成电路管芯102（在图2中示出两个）是对准的并被放置成与衬底104相接触。在对准和放置之后，实施接合工艺以将导电凸块106接合到第一组电连接件108中的对应电连接件上。接合工艺可以包括热回流工艺，其中对导电凸块106进行加热以熔化导电凸块106上的材料，从而使得将导电凸块接合到第一组电连接件108中的对应电连接件。
图3示出根据一个实施例的预填充工艺。预填充工艺可以包括使用诸如图3中所示的化学浴300在化学溶液中的浸泡工艺。化学浴300包括加热底板310。喷射输入312提供化学溶液的输入并且喷射输出314提供化学溶液的输出。此外，可以提供喷嘴316和/或推进器318用于进一步搅拌化学溶液并使化学溶液流通。可以以倾斜的角度将集成电路管芯102和衬底104放置到化学浴中。
集成电路管芯102和衬底104之间的间隔可以相当小，尤其是当使用BOT技术时。在这些类型的实施例中，使液体流通可以有助于在集成电路管芯102和衬底104之间推动液体。这样，使用喷射入口312/喷射出口314、喷嘴316和推进器318中的一种或多种可以有利于处理集成电路管芯102和衬底104之间的表面。
在一个实施例中，化学浸泡可以包括在37.5g NaClO2、10g NaOH、100gNa3PO4*12H2O和1升H2O中的浸泡。这些化学物质的浓度可以在0.5摩尔和1.5摩尔之间。可以将该溶液加热到约85℃至约95℃的温度。可以在该溶液中浸泡集成电路管芯102和衬底104约20分钟。之后，可以在去离子水中冲洗集成电路管芯102和衬底104，并用加热到约60℃至约90℃的温度的空气干燥。也可以使用室温空气进行干燥。
可以相信，诸如上面所述的化学处理在迹线上生成均匀的粗化表面。例如，在导电层110和第一组电连接件108包含镀Cu表面的实施例中，镀Cu表面可以可选地具有在其上自然形成的Cu2O层，诸如上面所述的化学处理在Cu2O层上方形成CuO层。CuO层显示出粗化表面，类似于草样表面。图7A是在进行粗化处理之前的镀Cu表面的显微照片，图7B是在进行粗化处理之后的镀Cu表面的显微照片。如图7A所示，粗化处理之前的镀Cu表面显示出具有垂直于主表面的小尺寸的相对平坦的表面。在粗化处理之后，表面显示出草样表面。
这是通过图7C示出的能量色散谱仪（EDS）分析示出的。可选的Cu2O层具有由于上述工艺形成的上覆CuO层。CuO层在Cu2O层上方形成纳米线层或草地样表面。这种类型的表面可以增加Cu表面和上覆的材料（诸如下文参照图4所描述的MUF）之间的机械联锁力。
在一个实施例中，纳米线的草地样表面可能显示出间距小于约500nm、平均粗糙度RA为约50nm至约70nm的以及高度为约30nm至约140nm。例如，在一个实施例中，平均粗糙度RA大于50nm，高度大于约120nm，并且间距小于约500nm。已发现这些尺寸的纳米线在导电层110和后续形成的用于用户环境的大多数典型的半导体应用的MUF之间提供良好的接合特征。然而，根据具体用途和/或材料可以使用其他间距和平均粗糙度。例如，用于迹线的不同材料（诸如金、铝等）和用于MUF的不同材料可以容许不同的间距和平均粗糙度。应当注意到尺寸应当使表面提供足够的机械联锁特征以充分地减少给定环境和材料的分层，从而为具体应用和环境提供具有所需可靠性的产品。
化学处理后的Cu的粗糙度/轮廓能够影响机械联锁力或粘附强度。粘附强度取决于表面粗糙度；高粗糙度提供相对高的粘附强度，而低粗糙度提供相对低的粘附强度。粗糙度的间距也可以影响粘附强度。高粗糙度和小间距可能不会表现出良好的机械性质或高粘附强度。例如，Cu表面的高粗糙度和小间距的轮廓通常表现出深而窄的谷，从而使模塑料（或MUF）可能不能完全填充这些谷。在这些情况中，CuO谷的底部可能是空的，因而有效粗糙度可能低于表面粗糙度。而且，长的CuO晶体可能是易碎的，这样的CuO谷的空底部易受到跌落或冲击损伤。两个CuO晶体之间的大间距降低联锁力，而小间距可能导致深谷问题。在一个实施例中，CuO晶体的间距是100nm至约500nm，而CuO晶体具有小于约180nm的长度。基于MUF的化学组成和填充物尺寸也可以对CuO晶体的间距和长度进行调整。
此外，封装件中的不同材料之间的热膨胀系数（CTE）不匹配是封装件的应力的主要来源，其中相对大的CTE不匹配或大的温度变化可能在封装件的各个部件之间诱导应力。在这些情况中，可以期望MUF/Cu界面处的较高的粘附力来阻止或降低分层或碎裂。改良Cu（或其他类型的材料）的表面粗糙度能够提供增大的机械粘附力。应当注意到，可以对草地样表面的尺寸进行调整以增加机械联锁力。如果草地样表面的尺寸增加得太多，机械联锁力可能降低。例如，如果CuO晶体纳米线之间的间距太小，则MUF可能不能完全填充到微小的间隙中，可能降低机械联锁力。此外，如果纳米线变得太长或太大，长的CuO晶体纳米线可能变得易碎并折断。本领域普通技术人员将意识到可以对长度和间距进行调整以便为具体应用提供足够的机械强度。表面粗糙度（例如纳米线的大小和/或间距）的量也可以取决于材料的类型。
下面的表格示出在上述工艺之前和之后的表面的X射线光电子能谱仪（XPS）分析的结果。如表格中所示，在处理后的样品中CuO和Cu(OH)2+CuCO3的比率增大。
在另一个实施例中，可以将集成电路管芯102和衬底104浸泡在诸如硫醇（C6H7NS）、亚磷酸三甲酯（C3H9O3P）等络合物中。例如，在其中导电层110和第一组电连接件108包含Cu，并在其上具有自然形成的Cu2O的实施例中，在诸如硫醇或亚磷酸三甲酯的络合物中的浸泡提供络合物层，其可以充当粘附层，可以提供化学键合，诸如偶极键合力。
作为一个实例，预填充工艺可以包含在室温下在1摩尔浓度的硫醇中浸泡集成电路管芯102和衬底104约5小时至10小时。浸泡后，可以在乙醇中冲洗集成电路管芯102和衬底104并在室温下使用压缩气体干燥。下面的表格示出在上述这种工艺之前和之后的表面的XPS分析的结果。
衬底104上的导电层110的Cu材料和随后形成的模塑料之间的键合界面在图8A中示出。图8B示出在使用亚磷酸三甲酯作为络合物的实施例中衬底104上的导电层110的Cu材料和随后形成的模塑料之间的键合界面。图9提供在铜表面上方形成的络合物的显微照片。
图4示出根据一个实施例在集成电路管芯102上方和下方施加的MUF410。可以在集成电路管芯102和衬底104之间以及上方的间隔中注入或者以其他方式形成MUF410。MUF410可以例如包含液体环氧树脂、变形凝胶、硅橡胶等，将其分散在集成电路管芯102和衬底104之间，然后固化以变硬。这种MUF410除了其他作用外还用于减少导电凸块320中的碎裂以及保护接合件远离污染物。
已发现，诸如上面参照图3所述的那些处理的处理改进了导电层110的露出部分和MUF410之间的接合，从而减少分层。例如，实验结果表明与未处理的表面相比，在如JEDEC JESD-22-A110修订本D中所限定的强加速温度和湿度应力测试（HAST）的时间零点及之后，诸如本文所述的那些工艺的工艺可以使接合强度的因数增大2。这些工艺还可以容许在施加MUF410之前等候更长时间。
图5示出根据一个实施例在已将第二组电连接件540安装到衬底104之后的集成电路管芯102和衬底104。在一个实施例中，第二组电连接件540可以包含以球栅阵列（BGA）布置安装的球并且可以由共晶焊料、无铅焊料等形成。可以在将第二组电连接件540放置在衬底104上之前实施诸如在含有1%氢氟（HF）酸的磷酸（H3PO4）和过氧化氢（H2O2）的化学溶液中的湿法浸泡（被称为DPP）的清洁工艺或另一清洁工艺从表面去除污染物。
衬底104可以进一步包括其他部件。例如，衬底的第二面可以进一步包括背面再分布层、接触焊盘、凸块下金属、钝化层和/或类似物。
图6示出根据一个实施例的分割工艺。例如，可以使用管芯切割机、激光或其他机构（mechanism）沿着划线650分离集成电路管芯102来分割衬底104，从而形成单独的封装件。，图6示出在每个封装件中具有一个集成电路管芯102是用于举例说明的目的。在其他实施例中，在分割后的每个封装件中可以包括多个集成电路管芯102。然后可以使用第二组电连接件540将单独的封装件连接到印刷电路板（PCB）；另一封装的集成电路、中介层；电气模块或机械模块；或者其他器件。
图10示出根据一个实施例的形成封装件的方法。工艺开始于步骤1002，在步骤1002中提供集成电路管芯和衬底，诸如上面参照图1所论述的。接着，在步骤1004中，将一个或多个集成电路管芯连接到衬底，诸如上面参照图2所论述的。在步骤1006中，实施预填充工艺，诸如上面参照图3所述的工艺。在步骤1008中，在集成电路管芯和衬底之间以及在集成电路管芯上方放置模塑底部填充物，诸如上面参照图5所描述的。在步骤1010中，如上面参照图6所描述的清洁衬底；以及在步骤1012中，可以如上面参照图7所描述的将诸如焊球的电连接件放置在衬底上。之后，在步骤1014中，可以如上面参照图8所述的实施分割工艺。
在一个实施例中，提供了一种形成半导体器件的方法。该方法包括提供衬底，该衬底具有与其相连接的集成电路管芯并具有在其上形成的金属层。对金属层的露出表面进行处理以生成粗糙表面。之后，在金属层上方施加模塑料。
在另一个实施例中，提供了一种半导体器件。该半导体器件包括衬底和位于衬底上的金属层。氧化物层位于金属层上，氧化物层具有从氧化物层的表面延伸的纳米线。
在又一个实施例中，提供了一种半导体器件。该半导体器件包括衬底，在该衬底上具有金属层。络合物层位于金属层上。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种形成半导体器件的方法，所述方法包括：
提供衬底，所述衬底具有与所述衬底相连接的集成电路管芯，在所述衬底上形成有金属层；
对所述金属层的露出表面进行处理，所述处理生成具有纳米线的粗化表面；以及
在所述金属层上方施加模塑料或底部填充材料。
2.根据权利要求1所述的方法，其中，所述金属层包含Cu，并且所述纳米线包含CuO。
3.根据权利要求2所述的方法，其中，包含CuO的所述纳米线增大表面粗糙度。
4.根据权利要求3所述的方法，其中，表面粗糙度RA大于50nm，所述纳米线的高度大于120nm，并且所述纳米线的间距小于500nm。
5.根据权利要求2所述的方法，其中，所述金属层包含介于所述CuO和所述Cu之间的自然氧化物层。
6.根据权利要求1所述的方法，其中，所述处理包括在所述金属层上方形成络合物层。
7.根据权利要求6所述的方法，其中，所述处理包括将所述衬底放置在化学浴中。
8.根据权利要求7所述的方法，其中，所述化学浴包含硫醇或亚磷酸三甲酯。
9.一种半导体器件，包括：
衬底；
位于所述衬底上的金属层；以及
在所述金属层上形成的氧化物层，所述氧化物层具有从所述氧化物层的表面延伸的纳米线。
10.一种半导体器件，包括：
衬底；
位于所述衬底上的金属层；以及
形成在所述金属层上的络合物层，所述络合物层比所述金属层的硫含量更高。
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US10522444B2 (en) * 2013-03-11 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment method and apparatus for semiconductor packaging
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US20170162536A1 (en) 2015-12-03 2017-06-08 International Business Machines Corporation Nanowires for pillar interconnects
US10629454B2 (en) * 2017-11-08 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070262432A1 (en) * 2006-05-11 2007-11-15 Infineon Technologies Ag Semiconductor device comprising semiconductor device components embedded in plastic housing composition
CN101137768A (zh) * 2005-03-11 2008-03-05 日立化成工业株式会社 铜的表面处理方法以及铜
US20090258459A1 (en) * 2006-04-07 2009-10-15 Texas Instruments Incorporated Packaged System of Semiconductor Chips Having a Semiconductor Interposer
CN102237470A (zh) * 2010-04-29 2011-11-09 展晶科技(深圳)有限公司 发光二极管封装结构及其制造方法以及其基座的制造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713304B2 (ja) * 1987-12-14 1995-02-15 日立化成工業株式会社 銅の表面処理法
JPH02198196A (ja) * 1989-01-27 1990-08-06 Hitachi Condenser Co Ltd プリント配線板の製造方法
JP2656622B2 (ja) 1989-07-19 1997-09-24 株式会社日立製作所 銅と樹脂の接着方法
US5622782A (en) * 1993-04-27 1997-04-22 Gould Inc. Foil with adhesion promoting layer derived from silane mixture
US5825042A (en) * 1993-06-18 1998-10-20 Space Electronics, Inc. Radiation shielding of plastic integrated circuits
JPH09246720A (ja) 1996-03-08 1997-09-19 Hitachi Aic Inc 多層印刷配線板およびその製造方法
US6046075A (en) * 1997-12-23 2000-04-04 Vlsi Technology, Inc. Oxide wire bond insulation in semiconductor assemblies
JP3702788B2 (ja) * 1998-07-01 2005-10-05 セイコーエプソン株式会社 半導体装置の製造方法
US6126806A (en) * 1998-12-02 2000-10-03 International Business Machines Corporation Enhancing copper electromigration resistance with indium and oxygen lamination
JP2000282265A (ja) 1999-03-31 2000-10-10 Mec Kk 銅または銅合金のマイクロエッチング剤およびそれを用いる表面処理法
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US6858527B2 (en) * 2003-04-14 2005-02-22 Intel Corporation Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers
JP3883543B2 (ja) * 2003-04-16 2007-02-21 新光電気工業株式会社 導体基材及び半導体装置
US6784093B1 (en) * 2003-06-27 2004-08-31 Texas Instruments Incorporated Copper surface passivation during semiconductor manufacturing
KR100607408B1 (ko) * 2004-07-21 2006-08-02 삼성전자주식회사 반도체 기판의 신뢰성 평가방법
JP2006108512A (ja) * 2004-10-07 2006-04-20 Ses Co Ltd 基板処理装置
KR101042483B1 (ko) * 2005-03-11 2011-06-16 히다치 가세고교 가부시끼가이샤 구리의 표면 처리 방법 및 구리
US8796544B2 (en) * 2005-12-14 2014-08-05 Massachusetts Institute Of Technology Bio-sensitized solar cells (BSSC)
KR100818622B1 (ko) * 2006-08-14 2008-04-01 삼성전기주식회사 광 인쇄회로기판 및 그 제작방법
US8012886B2 (en) * 2007-03-07 2011-09-06 Asm Assembly Materials Ltd Leadframe treatment for enhancing adhesion of encapsulant thereto
TWM393806U (en) * 2010-05-31 2010-12-01 Hon Hai Prec Ind Co Ltd Light emitting diode lead frame
JP5787779B2 (ja) * 2012-01-25 2015-09-30 日東電工株式会社 導電性フィルムロールの製造方法
US8907479B2 (en) * 2013-03-11 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Treating copper surfaces for packaging
US10522444B2 (en) * 2013-03-11 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment method and apparatus for semiconductor packaging

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101137768A (zh) * 2005-03-11 2008-03-05 日立化成工业株式会社 铜的表面处理方法以及铜
US20090258459A1 (en) * 2006-04-07 2009-10-15 Texas Instruments Incorporated Packaged System of Semiconductor Chips Having a Semiconductor Interposer
US20070262432A1 (en) * 2006-05-11 2007-11-15 Infineon Technologies Ag Semiconductor device comprising semiconductor device components embedded in plastic housing composition
CN102237470A (zh) * 2010-04-29 2011-11-09 展晶科技(深圳)有限公司 发光二极管封装结构及其制造方法以及其基座的制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
C.K.Y.WONG等: ""Thiol based chemical treatment as adhesion promoter for Cu-epoxy interface"", 《IN:PROC.INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING,SHANGHAI,2008》 *
H.Y.LEE等: ""Effects of oxidation treatments on the fracture toughness of leadframe/epoxy interfaces"", 《MATERIALS SCIENCE AND ENGINEERING: A》 *

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