CN104010152B - High-definition VPR integrated machine - Google Patents
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- CN104010152B CN104010152B CN201410232054.0A CN201410232054A CN104010152B CN 104010152 B CN104010152 B CN 104010152B CN 201410232054 A CN201410232054 A CN 201410232054A CN 104010152 B CN104010152 B CN 104010152B
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Abstract
The invention discloses a high-definition VPR integrated machine. The high-definition VPR integrated machine comprises a video combiner module and a core processor, wherein the video combiner module comprises a first HDMI interface, a first SDI interface, a second SDI interface, a third SDI interface, an HDMI decoding chip, a first SDI decoding chip, a second SDI decoding chip, a third SDI decoding chip, an FPGA chip, a FLASH chip and an FPGA peripheral circuit, and the core processor comprises an SOC chip, an NANDFLASH chip, an audio encoding and decoding chip, an Ethernet chip, an RS232 chip and an output interface. According to the high-definition VPR integrated machine, the SDI interfaces are additionally arranged based on a traditional HDMI interface, SDI standard signals can be directly received through the cooperation between the SDI interfaces and the FPGA chip and an SOC chip, three SDI-to-HDMI converters are omitted, project installation is facilitated, the overall cost is reduced, and the transmission distance of a video signal is increased. The high-definition VPR integrated machine can be widely applied to the video processing field.
Description
Technical field
The present invention relates to technical field of video processing, especially a kind of VPR high definitions record-broadcast all-in-one machine.
Background technology
Explanation of nouns：
VPR：Video playback and recording；
HDMI：HDMI.
SDI interfaces：Digital component serial line interface.
SoC：The abbreviation of System on Chip, referred to as systems-on-a-chip.
SATA interface：Serial Advanced Technology Attachment, the abbreviation of serial ATA interface.
SD-CARD interfaces：Safe digital card interface.
Bnc interface：Bayonet nut connector, one kind of Coaxial Cable joint.
LINE IN interfaces：Audio input interface.
LINE OUT interfaces：Audio output interface.
DDR2：Second filial generation double data rate Synchronous Dynamic Random Access Memory.
DDR3：Third generation double data rate Synchronous Dynamic Random Access Memory.
At present, most high definition recorded broadcast equipment receives signal using HDMI standard interface, and high-definition camera comes
Signal be usually SDI interface standards.Therefore when recorded broadcast equipment gathers video signal using HDMI, need to connect one
SDI turns the transducer of HDMI, is not easy to project installation, and the transmission range of video signal is shorter.
The content of the invention
In order to solve above-mentioned technical problem, the purpose of the present invention is：A kind of convenient engineering installation is provided and video signal is passed
The longer VPR high definition record-broadcast all-in-one machines of defeated distance.
The technical solution adopted for the present invention to solve the technical problems is：A kind of VPR high definitions record-broadcast all-in-one machine, including video
Combining module and core processor, the video combining module includes that the first HDMI, a SDI interfaces, the 2nd SDI connect
Mouth, the 3rd SDI interfaces, HDMI decoding chips, a SDI decoding chips, the 2nd SDI decoding chips, the 3rd SDI decoding chips,
Fpga chip, FLASH chip and FPGA peripheral circuit；The core processor includes SOC, NAND FLASH chips, sound
Frequency codec chip, Ethernet chip, RS232 chips and output interface；
The first SDI interfaces are connected by a SDI decoding chips and then with the input of fpga chip, and described second
SDI interfaces are connected by the 2nd SDI decoding chips and then with the input of fpga chip；3rd SDI interfaces are solved by the 3rd SDI
Code chip is further connected with the input of fpga chip；First HDMI by HDMI decoding chips so that with FPGA cores
The input connection of piece, the FLASH chip and FPGA peripheral circuit are connected with fpga chip；
The SOC is connected by parallel data bus line with fpga chip, the NAND FLASH chips and SOC
Connection, the audio coding decoding chip, RS232 chips and Ethernet chip are both connected between SOC and output interface.
Further, also including ARM chips, the ARM chips are connected respectively with fpga chip and SOC.
Further, the output interface include the second HDMI, SATA interface, SD-CARD interfaces, microphone interface,
Ethernet interface, RS232 interfaces, RS485 interfaces, bnc interface, LINE IN interfaces, LINE OUT interfaces, USB interface and reset
Button, the reset key is connected with ARM chips, and second HDMI, SATA interface, SD-CARD interfaces, RS485 connect
Mouth, bnc interface and USB interface are connected with SOC, and the microphone interface, LINE IN interfaces and LINE OUT interfaces are equal
It is connected by audio coding decoding chip and then with SOC.
Further, the fpga chip has been also respectively connected with a DDR2 chips, the 2nd DDR2 chips, the 3rd DDR2 chips
With the 4th DDR2 chips.
Further, the SOC has been also respectively connected with a DDR3 chips, the 2nd DDR3 chips, the 3rd DDR3 chips
With the 4th DDR3 chips.
Further, the fpga chip is EP4CE40F23C8N chips, and a SDI decoding chips, the 2nd SDI are solved
Code chip and the 3rd SDI decoding chips are GV7601-IBE3 chips, and the HDMI decoding chips are ADV7441ABSTZ-170
Chip, a DDR2 chips, the 2nd DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 chips are
MT47H32M16HR-25EL:G chips.
Further, the SOC is TMS320DM8148BCYE1 chips, and the audio coding decoding chip is
TLV320AIC3106IRGZT chips, the Ethernet chip is AR8031-AL1A chips, DDR3 chips, second
DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips are K4B1G1646E-BCH9 chips, the NAND FLAH chips
For MT29F2G16ABAEAWP:E chips, the RS232 chips are MAX3232ESE chips.
Further, the HDMI decoding chips, a SDI decoding chips and the 2nd SDI decoding chips are arranged at FPGA
The left side of chip, the 3rd SDI decoding chips are arranged on the right side of fpga chip, a DDR2 chips and the 2nd DDR2
Chip is arranged on the bottom side of fpga chip, and the 3rd DDR2 chips and the 4th DDR2 chips are arranged on the top side of fpga chip.
The invention has the beneficial effects as follows：Connect including the SDI interface, the 2nd SDI being connected in parallel with the first HDMI
Mouthful and the 3rd SDI interfaces, SDI interfaces are additionally arranged on the basis of traditional HDMI, can by SDI interfaces and fpga chip,
The cooperation of SOC directly receives the signal of SDI standards, eliminates the transducer that 3 SDI turn HDMI, facilitates project installation
With reduce totle drilling cost, and extend the transmission range of video signal.
Description of the drawings
With reference to the accompanying drawings and examples the invention will be further described.
Fig. 1 is a kind of theory diagram of VPR high definitions record-broadcast all-in-one machine of the invention；
Fig. 2 is the four direction schematic diagram of fpga chip.
Specific embodiment
With reference to Fig. 1, a kind of VPR high definitions record-broadcast all-in-one machine, including video combining module and core processor, the video is closed
Road module include the first HDMI, a SDI interfaces, the 2nd SDI interfaces, the 3rd SDI interfaces, HDMI decoding chips, first
SDI decoding chips, the 2nd SDI decoding chips, the 3rd SDI decoding chips, fpga chip, FLASH chip and FPGA peripheral circuit；
The core processor includes SOC, NAND FLASH chips, audio coding decoding chip, Ethernet chip, RS232 chips
And output interface；
The first SDI interfaces are connected by a SDI decoding chips and then with the input of fpga chip, and described second
SDI interfaces are connected by the 2nd SDI decoding chips and then with the input of fpga chip；3rd SDI interfaces are solved by the 3rd SDI
Code chip is further connected with the input of fpga chip；First HDMI by HDMI decoding chips so that with FPGA cores
The input connection of piece, the FLASH chip and FPGA peripheral circuit are connected with fpga chip；
The SOC is connected by parallel data bus line with fpga chip, the NAND FLASH chips and SOC
Connection, the audio coding decoding chip, RS232 chips and Ethernet chip are both connected between SOC and output interface.
Wherein, video combining module, for carrying out video pre-filtering and merging superframe.
Core processor, for realize picture show, audio frequency and video format compression, memory module, WEB service, channel parameters
The Core Features such as configuration, access mode, various procotols and remote upgrade.
With reference to Fig. 1, be further used as preferred embodiment, also including ARM chips, the ARM chips respectively with FPGA
Chip and SOC connect.
ARM chips, produce reset signal and carry out parameter configuration to fpga chip and SOC.
It is further used as preferred embodiment, the output interface includes the second HDMI, SATA interface, SD-
CARD interfaces, microphone interface, Ethernet interface, RS232 interfaces, RS485 interfaces, bnc interface, LINE IN interfaces, LINE
OUT interfaces, USB interface and reset key, the reset key is connected with ARM chips, and second HDMI, SATA connect
Mouth, SD-CARD interfaces, RS485 interfaces, bnc interface and USB interface are connected with SOC, the microphone interface, LINE
IN interfaces and LINE OUT interfaces are connected by audio coding decoding chip and then with SOC.
With reference to Fig. 1, it is further used as preferred embodiment, the fpga chip has been also respectively connected with a DDR2 cores
Piece, the 2nd DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 chips.
With reference to Fig. 1, be further used as preferred embodiment, the SOC be also respectively connected with a DDR3 chips,
2nd DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips.
Be further used as preferred embodiment, the fpga chip be EP4CE40F23C8N chips, a SDI
Decoding chip, the 2nd SDI decoding chips and the 3rd SDI decoding chips are GV7601-IBE3 chips, the HDMI decoding chips
For ADV7441ABSTZ-170 chips, a DDR2 chips, the 2nd DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 cores
Piece is MT47H32M16HR-25EL:G chips.
Be further used as preferred embodiment, the SOC be TMS320DM8148BCYE1 chips, the audio frequency
Codec chip be TLV320AIC3106IRGZT chips, the Ethernet chip be AR8031-AL1A chips, described first
DDR3 chips, the 2nd DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips are K4B1G1646E-BCH9 chips, described
NAND FLAH chips are MT29F2G16ABAEAWP:E chips, the RS232 chips are MAX3232ESE chips.
With reference to Fig. 1, it is further used as preferred embodiment, the HDMI decoding chips, a SDI decoding chips and the
Two SDI decoding chips are arranged at the left side of fpga chip, and the 3rd SDI decoding chips are arranged on the right side of fpga chip,
The first DDR2 chips and the 2nd DDR2 chips are arranged on the bottom side of fpga chip, the 3rd DDR2 chips and the 4th DDR2
Chip is arranged on the top side of fpga chip.
Wherein, the left side of fpga chip, right side, top side and bottom side four direction are as shown in Figure 2.
The present invention is described in further detail with reference to specific embodiment.
Embodiment one
The present embodiment is introduced to the concrete structure and function of a kind of VPR high definitions record-broadcast all-in-one machine of the invention.
A kind of VPR high definitions record-broadcast all-in-one machine of the present invention includes two big modules：Video combining processing module and core processor.
（1）, video combining processing module
Video combining processing module mainly realizes video pre-filtering and merges the function of superframe.The module is mainly by one piece
Hold HDMI standard audio/video decoding chip ADV7441ABSTZ-170, three pieces support SDI standards audio/video decoding chip
GV7601-IBE3, four pieces of DDR2 chip MT47H32M16HR-25EL:G, one piece of fpga chip EP4CE40F23C8N and its peripheral hardware
Composition.
The four direction of fpga chip is defined as left side, right side, top side and bottom side（As shown in Figure 2）, per side from it is different
Chip device combination connection, constitute video combining process part.The left side of fpga chip and the part on right side are connected to
One piece of DV7441ABSTZ-170 chip and three pieces of GV7601-IBE3 chips, this four pieces of audio/video decoding chips（HDMI decodes core
Piece, a SDI decoding chips, the 2nd SDI decoding chips, the 3rd SDI decoding chips）It is parallel connection relation, video signal Jing
Cross this four chip block to be input to parallel inside FPGA.It is that a HDMI and a VGA connect before DV7441ABSTZ-170
Mouthful, for receiving with the high-definition video signal of HDMI or USB interface Mixed design.Three pieces of GV7601-IBE3 chips
Above respectively there is a SDI interface, these three SDI interfaces are used to directly receive the high-definition video signal of SDI standards, not only can prolong
The transmission range of long video signal, may be omitted with the transducer that SDI turns HDMI.Four pieces of DDR2 chips（First DDR2 chips,
Two DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 chips）Be placed on the bottom side and top side of fpga chip, for realize with
The functions such as the data interaction of FPGA, data processing and data storage.
（2）, core processor
Core processor mainly realize picture show, audio frequency and video format compression, memory module, WEB server, channel parameters
The Core Features such as configuration, access mode, various procotols and remote upgrade.The module is mainly by one piece of SOC
TMS320DM8148BCYE1, one piece of NAND FLASH chip MT29F2G16ABAEAWP:E, four pieces of DDR3 chips
K4B1G1646E-BCH9, one piece of audio coding decoding chip TLV320AIC3106IRGZT, one piece of gigabit Ethernet chip
AR8031-AL1A, one piece of 232 chip MAX3232ESE composition.
The inner connecting way of core processor can be subdivided into two parts：Data processing section and interface section.In data
Process part, SOC using dedicated pin respectively with one piece of NAND FLASH chip and four pieces of DDR3 chips（First DDR3 cores
Piece, the 2nd DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips）Connection, for realizing data interaction and data processing etc.
Function.In interface section, HDMI, SATA interface, USB interface, SD-CARD interfaces, bnc interface and RS485 interfaces are all straight
SOC is connected in succession；RS232 interfaces are first connected with RS232 chips and then are connected to SOC；Microphone interface, LINE
IN interfaces and LINE OUT interfaces are first connected with audio coding decoding chip TLV320AIC3106IRGZT and then are connected to SOC cores
On piece；Ethernet interface is then first connected with gigabit Ethernet chip AR8031-AL1A and then is connected to SOC.It is all of
Output interface is all concurrency relation, for realizing all of external connection function.
Connection between video combining processing module and core processor, is the connection by fpga chip and SOC
And realize.The fpga chip of video combining processing module is by using the parallel data bus line and core processor in its bottom side
SOC connection, so as to realize the interconnection of difference in functionality intermodule.
Embodiment two
The present embodiment is introduced to the operation principle of the present invention.
The operation principle of the present invention is as follows：
HDMI gathers high-definition video signal and by the video for collecting by one piece of ADV7441ABSTZ-170 chip
Signal transmission carries out Digital Image Processing to fpga chip.ADV7441ABSTZ-170 inside is containing one-component processor and mark
Clear processor, also containing the super self adaptation 2D comb filter of 5 wire type, can be used to carry out noise reduction to picture signal, and can
Outstanding colourity is provided when composite video signal is decoded and brightness is separated, then given with the format transmission of Cyber or RGB
Fpga chip carries out Digital Image Processing.
Three road SDI interfaces inputs are respectively by the audio/video decoding chip GV7601-IBE3 chips of three pieces of support SDI standards
Video decoding is carried out, fpga chip is transferred to after the parallel signal for the video signal for receiving being converted to 27MHz, by fpga chip
Complete the various Digital Image Processing functions such as image filtering.
Fpga chip is removed noise processed to the four tunnel frame of video that HDMI and three road SDI interfaces are uploaded respectively
Afterwards, four tunnel frame of video are synthesized into super frame all the way.Then fpga chip by the super frame with per video signal identical all the way
Form is transferred to SOC by parallel data bus line, and is stored in the DDR3 chips of SOC.
And the core processor that SOC is located then needs the synthesis for completing picture signal to process, comprising single-image, in drawing
The image synthesis of 7 kinds of forms such as picture, picture out picture is processed.The also built-in Web server in core processor, user can pass through
Web server is adjusted to the brightness of each road video signal, saturation, contrast, transparency.Meanwhile, core processor meeting
So that H.264, any one form is to each road encoding video signal in the form such as MPEG-4 or M-JPEG, output is maximum
The video flowing of the frames of 1080P@60, is then encapsulated into the video flowing of output in various agreements.The outputting video streams support that hard disk is deposited
The modes such as storage, USB flash disk storage and the network storage, Web client can check the real-time video by way of asking RTSP and flowing.
Compared with prior art, the present invention includes a SDI interfaces, the 2nd SDI with the first HDMI parallel connection
Interface and the 3rd SDI interfaces, are additionally arranged SDI interfaces on the basis of traditional HDMI, can be by SDI interfaces and FPGA cores
Piece, the cooperation of SOC directly receive the signal of SDI standards, eliminate the transducer that 3 SDI turn HDMI, facilitate engineering peace
Fill and reduce totle drilling cost, and extend the transmission range of video signal.
It is more than that the preferable enforcement to the present invention is illustrated, but the invention is not limited to the enforcement
Example, those of ordinary skill in the art can also make a variety of equivalent variations on the premise of without prejudice to spirit of the invention or replace
Change, the deformation or replacement of these equivalents are all contained in the application claim limited range.
Claims (6)
1. a kind of VPR high definitions record-broadcast all-in-one machine, it is characterised in that：Including video combining module and core processor, the video
Combining module include the first HDMI, a SDI interfaces, the 2nd SDI interfaces, the 3rd SDI interfaces, HDMI decoding chips, the
One SDI decoding chips, the 2nd SDI decoding chips, the 3rd SDI decoding chips, fpga chip, FLASH chip and FPGA periphery electricity
Road；The core processor includes SOC, NAND FLASH chips, audio coding decoding chip, Ethernet chip, RS232 cores
Piece and output interface；
The first SDI interfaces are connected by a SDI decoding chips and then with the input of fpga chip, the 2nd SDI
Interface is connected by the 2nd SDI decoding chips and then with the input of fpga chip；3rd SDI interfaces are decoded by the 3rd SDI
Chip is further connected with the input of fpga chip；First HDMI passes through HDMI decoding chips and then and fpga chip
Input connection, the FLASH chip and FPGA peripheral circuit are connected with fpga chip；
The SOC is connected by parallel data bus line with fpga chip, and the NAND FLASH chips connect with SOC
Connect, the audio coding decoding chip, RS232 chips and Ethernet chip are both connected between SOC and output interface；
Also include ARM chips, the ARM chips are connected respectively with fpga chip and SOC；
The output interface include the second HDMI, SATA interface, SD-CARD interfaces, microphone interface, Ethernet interface,
RS232 interfaces, RS485 interfaces, bnc interface, LINE IN interfaces, LINE OUT interfaces, USB interface and reset key, it is described multiple
Position button be connected with ARM chips, second HDMI, SATA interface, SD-CARD interfaces, RS485 interfaces, bnc interface and
USB interface is connected with SOC, and the microphone interface, LINE IN interfaces and LINE OUT interfaces are compiled by audio frequency and solved
Code chip is further connected with SOC.
2. a kind of VPR high definitions record-broadcast all-in-one machine according to claim 1, it is characterised in that：The fpga chip is also distinguished
It is connected with a DDR2 chips, the 2nd DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 chips.
3. a kind of VPR high definitions record-broadcast all-in-one machine according to claim 2, it is characterised in that：The SOC also connects respectively
It is connected to a DDR3 chips, the 2nd DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips.
4. a kind of VPR high definitions record-broadcast all-in-one machine according to claim 3, it is characterised in that：The fpga chip is
EP4CE40F23C8N chips, a SDI decoding chips, the 2nd SDI decoding chips and the 3rd SDI decoding chips are
GV7601-IBE3 chips, the HDMI decoding chips are ADV7441ABSTZ-170 chips, DDR2 chips, second
DDR2 chips, the 3rd DDR2 chips and the 4th DDR2 chips are MT47H32M16HR-25EL:G chips.
5. a kind of VPR high definitions record-broadcast all-in-one machine according to claim 4, it is characterised in that：The SOC is
TMS320DM8148BCYE1 chips, the audio coding decoding chip be TLV320AIC3106IRGZT chips, the ether web-roll core
Piece be AR8031-AL1A chips, a DDR3 chips, the 2nd DDR3 chips, the 3rd DDR3 chips and the 4th DDR3 chips
K4B1G1646E-BCH9 chips are, the NAND FLAH chips are MT29F2G16ABAEAWP:E chips, the RS232 cores
Piece is MAX3232ESE chips.
6. a kind of VPR high definitions record-broadcast all-in-one machine according to claim 5, it is characterised in that：The HDMI decoding chips,
One SDI decoding chips and the 2nd SDI decoding chips are arranged at the left side of fpga chip, and the 3rd SDI decoding chips are arranged
On the right side of fpga chip, a DDR2 chips and the 2nd DDR2 chips are arranged on the bottom side of fpga chip, and the described 3rd
DDR2 chips and the 4th DDR2 chips are arranged on the top side of fpga chip.
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| CN201410232054.0A CN104010152B (en) | 2014-05-28 | 2014-05-28 | High-definition VPR integrated machine |
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| CN201410232054.0A CN104010152B (en) | 2014-05-28 | 2014-05-28 | High-definition VPR integrated machine |
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| CN104010152B true CN104010152B (en) | 2017-05-03 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201477880U (en) * | 2009-08-24 | 2010-05-19 | 深圳市朗驰欣创科技有限公司 | Hard disk video recorder |
| CN201887894U (en) * | 2010-12-14 | 2011-06-29 | 福建天健电子科技股份有限公司 | High definition input type network DVR |
| CN102630000A (en) * | 2012-04-18 | 2012-08-08 | 天津天地伟业数码科技有限公司 | Eight-path SDI (Serial Digital Interface) embedded digital video recorder |
| CN202617284U (en) * | 2012-04-24 | 2012-12-19 | 深圳锐取信息技术股份有限公司 | VGA encoder for long-distance transmission |
| CN202721755U (en) * | 2012-07-18 | 2013-02-06 | 杭州巨峰科技有限公司 | An audio and video coding and decoding core board of a high-definition digital hard disk video recorder |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060092038A1 (en) * | 2004-11-03 | 2006-05-04 | Unger Robert A | Chameleon button universal remote control with tactile feel |
-
2014
- 2014-05-28 CN CN201410232054.0A patent/CN104010152B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201477880U (en) * | 2009-08-24 | 2010-05-19 | 深圳市朗驰欣创科技有限公司 | Hard disk video recorder |
| CN201887894U (en) * | 2010-12-14 | 2011-06-29 | 福建天健电子科技股份有限公司 | High definition input type network DVR |
| CN102630000A (en) * | 2012-04-18 | 2012-08-08 | 天津天地伟业数码科技有限公司 | Eight-path SDI (Serial Digital Interface) embedded digital video recorder |
| CN202617284U (en) * | 2012-04-24 | 2012-12-19 | 深圳锐取信息技术股份有限公司 | VGA encoder for long-distance transmission |
| CN202721755U (en) * | 2012-07-18 | 2013-02-06 | 杭州巨峰科技有限公司 | An audio and video coding and decoding core board of a high-definition digital hard disk video recorder |
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Denomination of invention: High-definition VPR integrated machine Effective date of registration: 20190422 Granted publication date: 20170503 Pledgee: Guangzhou Bank Co.,Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY CO.,LTD. Registration number: 2019440000160 |
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Denomination of invention: High-definition VPR integrated machine Effective date of registration: 20200512 Granted publication date: 20170503 Pledgee: Guangzhou Bank Co.,Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY Co.,Ltd. Registration number: Y2020440000109 |
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Denomination of invention: A Vpr high definition recorder Effective date of registration: 20210616 Granted publication date: 20170503 Pledgee: Guangzhou Bank Co.,Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY Co.,Ltd. Registration number: Y2021440000204 |
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Denomination of invention: A VPR high-definition recorder and player Effective date of registration: 20230214 Granted publication date: 20170503 Pledgee: Bank of China Limited by Share Ltd. Guangzhou Tianhe branch Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY CO.,LTD. Registration number: Y2023980032554 |