CN104010152A - High-definition VPR integrated machine - Google Patents
High-definition VPR integrated machine Download PDFInfo
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- CN104010152A CN104010152A CN201410232054.0A CN201410232054A CN104010152A CN 104010152 A CN104010152 A CN 104010152A CN 201410232054 A CN201410232054 A CN 201410232054A CN 104010152 A CN104010152 A CN 104010152A
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Abstract
The invention discloses a high-definition VPR integrated machine. The high-definition VPR integrated machine comprises a video combiner module and a core processor, wherein the video combiner module comprises a first HDMI interface, a first SDI interface, a second SDI interface, a third SDI interface, an HDMI decoding chip, a first SDI decoding chip, a second SDI decoding chip, a third SDI decoding chip, an FPGA chip, a FLASH chip and an FPGA peripheral circuit, and the core processor comprises an SOC chip, an NANDFLASH chip, an audio encoding and decoding chip, an Ethernet chip, an RS232 chip and an output interface. According to the high-definition VPR integrated machine, the SDI interfaces are additionally arranged based on a traditional HDMI interface, SDI standard signals can be directly received through the cooperation between the SDI interfaces and the FPGA chip and an SOC chip, three SDI-to-HDMI converters are omitted, project installation is facilitated, the overall cost is reduced, and the transmission distance of a video signal is increased. The high-definition VPR integrated machine can be widely applied to the video processing field.
Description
Technical field
The present invention relates to technical field of video processing, especially a kind of VPR high definition record-broadcast all-in-one machine.
Background technology
Explanation of nouns:
VPR: video playback with record;
HDMI interface: HDMI (High Definition Multimedia Interface).
SDI interface: digital component serial line interface.
The abbreviation of SoC:System on Chip, is called systems-on-a-chip.
SATA interface: Serial Advanced Technology Attachment, the abbreviation of serial ATA interface.
SD-CARD interface: safe digital card interface.
Bnc interface: bayonet nut connector, the one of Coaxial Cable joint.
LINE IN interface: audio input interface.
LINE OUT interface: audio output interface.
DDR2: second generation double data rate Synchronous Dynamic Random Access Memory.
DDR3: third generation double data rate Synchronous Dynamic Random Access Memory.
At present, most high definition recorded broadcast equipment adopts HDMI standard interface to receive signal, and the signal that high-definition camera is come is generally SDI interface standard.Therefore when recorded broadcast equipment adopts HDMI interface to gather vision signal, need to meet a SDI and turn the transducer of HDMI, be not easy to project installation, and the transmission range of vision signal be shorter.
Summary of the invention
In order to solve the problems of the technologies described above, the object of the invention is: a kind of convenient engineering installation and the longer VPR high definition record-broadcast all-in-one machine of video signal transmission distance are provided.
The technical solution adopted for the present invention to solve the technical problems is: a kind of VPR high definition record-broadcast all-in-one machine, comprise that video closes road module and core processor, described video closes road module and comprises a HDMI interface, a SDI interface, the 2nd SDI interface, Three S's DI interface, HDMI decoding chip, a SDI decoding chip, the 2nd SDI decoding chip, Three S's DI decoding chip, fpga chip, FLASH chip and FPGA peripheral circuit; Described core processor comprises SOC chip, NAND FLASH chip, audio coding decoding chip, Ethernet chip, RS232 chip and output interface;
A described SDI interface passes through a SDI decoding chip and then is connected with the input of fpga chip, and described the 2nd SDI interface passes through the 2nd SDI decoding chip and then is connected with the input of fpga chip; Three S's DI interface passes through Three S's DI decoding chip and then is connected with the input of fpga chip; A described HDMI interface passes through HDMI decoding chip and then is connected with the input of fpga chip, and described FLASH chip and FPGA peripheral circuit are all connected with fpga chip;
Described SOC chip is connected with fpga chip by parallel data bus line, and described NAND FLASH chip is connected with SOC chip, and described audio coding decoding chip, RS232 chip and Ethernet chip are all connected between SOC chip and output interface.
Further, also comprise ARM chip, described ARM chip is connected with fpga chip and SOC chip respectively.
Further, described output interface comprises the 2nd HDMI interface, SATA interface, SD-CARD interface, microphone interface, Ethernet interface, RS232 interface, RS485 interface, bnc interface, LINE IN interface, LINE OUT interface, USB interface and reset key, described reset key is connected with ARM chip, described the 2nd HDMI interface, SATA interface, SD-CARD interface, RS485 interface, bnc interface is all connected with SOC chip with USB interface, described microphone interface, LINE IN interface is all connected by audio coding decoding chip and then with SOC chip with LINE OUT interface.
Further, described fpga chip is also connected with respectively a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
Further, described SOC chip is also connected with respectively a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
Further, described fpga chip is EP4CE40F23C8N chip, a described SDI decoding chip, the 2nd SDI decoding chip and Three S's DI decoding chip are GV7601-IBE3 chip, described HDMI decoding chip is ADV7441ABSTZ-170 chip, and a described DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip are MT47H32M16HR-25EL:G chip.
Further, described SOC chip is TMS320DM8148BCYE1 chip, described audio coding decoding chip is TLV320AIC3106IRGZT chip, described Ethernet chip is AR8031-AL1A chip, a described DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip are K4B1G1646E-BCH9 chip, described NAND FLAH chip is MT29F2G16ABAEAWP:E chip, and described RS232 chip is MAX3232ESE chip.
Further, described HDMI decoding chip, a SDI decoding chip and the 2nd SDI decoding chip are all arranged on the left side of fpga chip, described Three S's DI decoding chip is arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are arranged on the bottom side of fpga chip, and described the 3rd DDR2 chip and the 4th DDR2 chip are arranged on the top side of fpga chip.
The invention has the beneficial effects as follows: comprise the SDI interface, the 2nd SDI interface and the Three S's DI interface that are connected with a HDMI interface concurrent, on the basis of traditional HDMI interface, set up SDI interface, can be by SDI interface the signal that directly receives SDI standard that coordinates with fpga chip, SOC chip, save the transducer that 3 SDI turn HDMI, facilitate project installation and reduced total cost, and having extended the transmission range of vision signal.
Brief description of the drawings
Below in conjunction with drawings and Examples, the invention will be further described.
Fig. 1 is the theory diagram of a kind of VPR high definition of the present invention record-broadcast all-in-one machine;
Fig. 2 is the four direction schematic diagram of fpga chip.
Embodiment
With reference to Fig. 1, a kind of VPR high definition record-broadcast all-in-one machine, comprise that video closes road module and core processor, described video closes road module and comprises a HDMI interface, a SDI interface, the 2nd SDI interface, Three S's DI interface, HDMI decoding chip, a SDI decoding chip, the 2nd SDI decoding chip, Three S's DI decoding chip, fpga chip, FLASH chip and FPGA peripheral circuit; Described core processor comprises SOC chip, NAND FLASH chip, audio coding decoding chip, Ethernet chip, RS232 chip and output interface;
A described SDI interface passes through a SDI decoding chip and then is connected with the input of fpga chip, and described the 2nd SDI interface passes through the 2nd SDI decoding chip and then is connected with the input of fpga chip; Three S's DI interface passes through Three S's DI decoding chip and then is connected with the input of fpga chip; A described HDMI interface passes through HDMI decoding chip and then is connected with the input of fpga chip, and described FLASH chip and FPGA peripheral circuit are all connected with fpga chip;
Described SOC chip is connected with fpga chip by parallel data bus line, and described NAND FLASH chip is connected with SOC chip, and described audio coding decoding chip, RS232 chip and Ethernet chip are all connected between SOC chip and output interface.
Wherein, video closes road module, for carrying out video pre-filtering and merging superframe.
Core processor, for realizing the Core Features such as picture disply, audio frequency and video format compression, memory module, WEB service, channel parameters configuration, access mode, talk various network protocols and remote upgrade.
With reference to Fig. 1, be further used as preferred embodiment, also comprise ARM chip, described ARM chip is connected with fpga chip and SOC chip respectively.
ARM chip, produces reset signal and carries out parameter configuration fpga chip and SOC chip.
Be further used as preferred embodiment, described output interface comprises the 2nd HDMI interface, SATA interface, SD-CARD interface, microphone interface, Ethernet interface, RS232 interface, RS485 interface, bnc interface, LINE IN interface, LINE OUT interface, USB interface and reset key, described reset key is connected with ARM chip, described the 2nd HDMI interface, SATA interface, SD-CARD interface, RS485 interface, bnc interface is all connected with SOC chip with USB interface, described microphone interface, LINE IN interface is all connected by audio coding decoding chip and then with SOC chip with LINE OUT interface.
With reference to Fig. 1, be further used as preferred embodiment, described fpga chip is also connected with respectively a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
With reference to Fig. 1, be further used as preferred embodiment, described SOC chip is also connected with respectively a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
Be further used as preferred embodiment, described fpga chip is EP4CE40F23C8N chip, a described SDI decoding chip, the 2nd SDI decoding chip and Three S's DI decoding chip are GV7601-IBE3 chip, described HDMI decoding chip is ADV7441ABSTZ-170 chip, and a described DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip are MT47H32M16HR-25EL:G chip.
Be further used as preferred embodiment, described SOC chip is TMS320DM8148BCYE1 chip, described audio coding decoding chip is TLV320AIC3106IRGZT chip, described Ethernet chip is AR8031-AL1A chip, a described DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip are K4B1G1646E-BCH9 chip, described NAND FLAH chip is MT29F2G16ABAEAWP:E chip, and described RS232 chip is MAX3232ESE chip.
With reference to Fig. 1, be further used as preferred embodiment, described HDMI decoding chip, a SDI decoding chip and the 2nd SDI decoding chip are all arranged on the left side of fpga chip, described Three S's DI decoding chip is arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are arranged on the bottom side of fpga chip, and described the 3rd DDR2 chip and the 4th DDR2 chip are arranged on the top side of fpga chip.
Wherein, the left side of fpga chip, right side, top side and bottom side four direction are as shown in Figure 2.
Below in conjunction with specific embodiment, the present invention is described in further detail.
Embodiment mono-
The present embodiment is introduced concrete structure and the function of a kind of VPR high definition of the present invention record-broadcast all-in-one machine.
A kind of VPR high definition of the present invention record-broadcast all-in-one machine comprises two large modules: video closes road processing module and core processor.
(1), video closes road processing module
The road processing module of closing video mainly realizes video pre-filtering and merges the function of superframe.This module is mainly made up of an audio/video decoding chip ADV7441ABSTZ-170 who supports HDMI standard, three audio/video decoding chip GV7601-IBE3 that support SDI standards, four DDR2 chip MT47H32M16HR-25EL:G, fpga chip EP4CE40F23C8N and peripheral hardware thereof.
The four direction of fpga chip is defined as left side, right side, top side and bottom side (as shown in Figure 2), and each side is connected from different chip devices, has formed video He Lu processing section.The left side of fpga chip has been connected a DV7441ABSTZ-170 chip and three GV7601-IBE3 chips with the part on right side, these four audio/video decoding chips (HDMI decoding chip, a SDI decoding chip, the 2nd SDI decoding chip, Three S's DI decoding chip) are parallel join relations, and vision signal is through the parallel FPGA inside that is input to of this four chip block.DV7441ABSTZ-170's is a HDMI interface and a VGA interface above, for receiving the high-definition video signal that mixes input with HDMI interface or VGA interface.Three GV7601-IBE3 chips respectively have above a SDI interface, these three SDI interfaces, for the direct high-definition video signal of reception SDI standard, not only can extend the transmission range of vision signal, can also save SDI and turn the transducer of HDMI.Four DDR2 chips (a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip) are placed on bottom side and the top side of fpga chip, for realizing the functions such as data interaction, data processing and data storage with FPGA.
(2), core processor
Core processor is mainly realized the Core Features such as picture disply, audio frequency and video format compression, memory module, WEB server, channel parameters configuration, access mode, talk various network protocols and remote upgrade.This module is mainly made up of a SOC chip TMS320DM8148BCYE1, NAND FLASH chip MT29F2G16ABAEAWP:E, four DDR3 chip K4B1G1646E-BCH9, audio coding decoding chip TLV320AIC3106IRGZT, gigabit Ethernet chip AR8031-AL1A, 232 chip MAX3232ESE.
The inner connecting way of core processor can be subdivided into two parts: data processing section and interface section.At data processing section, SOC chip uses dedicated pin to be connected with a NAND FLASH chip and four DDR3 chips (a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip) respectively, for realizing the function such as data interaction and data processing.In interface section, HDMI interface, SATA interface, USB interface, SD-CARD interface, bnc interface and RS485 interface are all directly connected to SOC chip; RS232 interface is first connected with RS232 chip and then is connected to SOC chip; Microphone interface, LINE IN interface and LINE OUT interface are first connected with audio coding decoding chip TLV320AIC3106IRGZT and then are connected on SOC chip; Ethernet interface is first connected with gigabit Ethernet chip AR8031-AL1A and then is connected to SOC chip.All output interfaces are all concurrency relations, for realizing all external linkage functions.
Video closes the connection between road processing module and core processor, is to realize by fpga chip and being connected of SOC chip.The fpga chip that video closes road processing module is connected at the parallel data bus line of its bottom side and the SOC chip of core processor by using, thereby realizes the interconnection of difference in functionality intermodule.
Embodiment bis-
The present embodiment is introduced operation principle of the present invention.
Operation principle of the present invention is as follows:
HDMI interface is gathered high-definition video signal and the video signal transmission collecting is carried out to Digital Image Processing to fpga chip by an ADV7441ABSTZ-170 chip.ADV7441ABSTZ-170 contains inside one-component processor and SD processor, also contain a super self adaptation 2D comb filter of 5 line formula, can be used for picture signal to carry out noise reduction, and can in the time of decoding composite video signal, provide outstanding colourity to separate with brightness, be then transferred to fpga chip with the form of Cyber or RGB and carry out Digital Image Processing.
Three road SDI interface inputs support the audio/video decoding chip GV7601-IBE3 chip of SDI standard to carry out video decode by three respectively, after the vision signal receiving is converted to the parallel signal of 27MHz, be transferred to fpga chip, completed the various Digital Image Processing functions such as image filtering by fpga chip.
Fpga chip is uploaded Si road frame of video to HDMI interface He San road SDI interface respectively and is removed after noise processed, and Jiang Si road frame of video is synthesized a road super frame.Then fpga chip is transferred to SOC chip with the form identical with each road vision signal by parallel data bus line by this super frame, and leaves in the DDR3 chip of SOC chip.
The core processor at SOC chip place has needed the synthetic processing of picture signal, and the image that comprises 7 kinds of forms such as single-image, picture-in-picture, picture out picture is synthetic to be processed.Also built-in Web server in core processor, user can adjust by brightness, saturation, contrast, the transparency of Web server Dui Ge road vision signal.Meanwhile, core processor can with H.264, any one form Dui Ge road encoding video signal in the form such as MPEG-4 or M-JPEG, export the video flowing of maximum 1080P 60 frames, then the video flowing of output is encapsulated in variety of protocol.This outputting video streams is supported the modes such as hard-disc storage, USB flash disk storage and the network storage, and Web client can be checked this video in real time by the mode of request RTSP stream.
Compared with prior art, the present invention includes the SDI interface, the 2nd SDI interface and the Three S's DI interface that are connected with a HDMI interface concurrent, on the basis of traditional HDMI interface, set up SDI interface, can be by SDI interface the signal that directly receives SDI standard that coordinates with fpga chip, SOC chip, save the transducer that 3 SDI turn HDMI, facilitate project installation and reduced total cost, and having extended the transmission range of vision signal.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and the distortion that these are equal to or replacement are all included in the application's claim limited range.
Claims (8)
1. a VPR high definition record-broadcast all-in-one machine, it is characterized in that: comprise that video closes road module and core processor, described video closes road module and comprises a HDMI interface, a SDI interface, the 2nd SDI interface, Three S's DI interface, HDMI decoding chip, a SDI decoding chip, the 2nd SDI decoding chip, Three S's DI decoding chip, fpga chip, FLASH chip and FPGA peripheral circuit; Described core processor comprises SOC chip, NAND FLASH chip, audio coding decoding chip, Ethernet chip, RS232 chip and output interface;
A described SDI interface passes through a SDI decoding chip and then is connected with the input of fpga chip, and described the 2nd SDI interface passes through the 2nd SDI decoding chip and then is connected with the input of fpga chip; Three S's DI interface passes through Three S's DI decoding chip and then is connected with the input of fpga chip; A described HDMI interface passes through HDMI decoding chip and then is connected with the input of fpga chip, and described FLASH chip and FPGA peripheral circuit are all connected with fpga chip;
Described SOC chip is connected with fpga chip by parallel data bus line, and described NAND FLASH chip is connected with SOC chip, and described audio coding decoding chip, RS232 chip and Ethernet chip are all connected between SOC chip and output interface.
2. a kind of VPR high definition record-broadcast all-in-one machine according to claim 1, is characterized in that: also comprise ARM chip, described ARM chip is connected with fpga chip and SOC chip respectively.
3. a kind of VPR high definition record-broadcast all-in-one machine according to claim 2, it is characterized in that: described output interface comprises the 2nd HDMI interface, SATA interface, SD-CARD interface, microphone interface, Ethernet interface, RS232 interface, RS485 interface, bnc interface, LINE IN interface, LINE OUT interface, USB interface and reset key, described reset key is connected with ARM chip, described the 2nd HDMI interface, SATA interface, SD-CARD interface, RS485 interface, bnc interface is all connected with SOC chip with USB interface, described microphone interface, LINE IN interface is all connected by audio coding decoding chip and then with SOC chip with LINE OUT interface.
4. a kind of VPR high definition record-broadcast all-in-one machine according to claim 3, is characterized in that: described fpga chip is also connected with respectively a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
5. a kind of VPR high definition record-broadcast all-in-one machine according to claim 4, is characterized in that: described SOC chip is also connected with respectively a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
6. a kind of VPR high definition record-broadcast all-in-one machine according to claim 5, it is characterized in that: described fpga chip is EP4CE40F23C8N chip, a described SDI decoding chip, the 2nd SDI decoding chip and Three S's DI decoding chip are GV7601-IBE3 chip, described HDMI decoding chip is ADV7441ABSTZ-170 chip, and a described DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip are MT47H32M16HR-25EL:G chip.
7. a kind of VPR high definition record-broadcast all-in-one machine according to claim 6, it is characterized in that: described SOC chip is TMS320DM8148BCYE1 chip, described audio coding decoding chip is TLV320AIC3106IRGZT chip, described Ethernet chip is AR8031-AL1A chip, a described DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip are K4B1G1646E-BCH9 chip, described NAND FLAH chip is MT29F2G16ABAEAWP:E chip, and described RS232 chip is MAX3232ESE chip.
8. a kind of VPR high definition record-broadcast all-in-one machine according to claim 7, it is characterized in that: described HDMI decoding chip, a SDI decoding chip and the 2nd SDI decoding chip are all arranged on the left side of fpga chip, described Three S's DI decoding chip is arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are arranged on the bottom side of fpga chip, and described the 3rd DDR2 chip and the 4th DDR2 chip are arranged on the top side of fpga chip.
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