CN103928523B - A kind of test device group's field-effect transistor and test device group's method of testing thereof - Google Patents
A kind of test device group's field-effect transistor and test device group's method of testing thereof Download PDFInfo
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- CN103928523B CN103928523B CN201410143407.XA CN201410143407A CN103928523B CN 103928523 B CN103928523 B CN 103928523B CN 201410143407 A CN201410143407 A CN 201410143407A CN 103928523 B CN103928523 B CN 103928523B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
A kind of test device group's field-effect transistor, including: substrate；Source area, is positioned among described substrate；Drain region, is positioned among described substrate, and positioned opposite with described source area in the horizontal direction of described substrate；Dielectric layer, is covered in described substrate in the vertical direction of described substrate；And gate regions, described vertical direction is positioned on described dielectric layer, and in described horizontal direction between described source area and described drain region, wherein, described gate regions is away from the axis of the central area pointing to described drain region in described horizontal direction from the central area of described source area.A kind of test device group's method of testing, is used for testing described field-effect transistor.Reliability and the operating characteristic of the edge of test device group's field-effect transistor can be measured, it is possible to be appreciated more fully from the product quality of semiconductor device, the beneficially raising of semiconductor device product quality.
Description
Technical field
It relates to a kind of field-effect transistor, particularly relate to a kind of for testing device group (TEG:Test
Element Group) field-effect transistor, and survey for test device group that this field-effect transistor is tested
Method for testing.
Background technology
In semiconductor device production process, through frequently with tester part group monitor semiconductor device product attribute or
Technical expression.
Such as, Fig. 1 illustrates the top view of a kind of test device group's field-effect transistor of the prior art.Figure
2A and Fig. 2 B illustrate respectively the hatching a-a from Fig. 1 upwards as viewed from profile and hatching b-from Fig. 1
The profile that b looks to the left, wherein, hatching a-a is current channel (i.e. raceway groove) side of test device group's field-effect transistor
To, hatching b-b is positioned on the width of test device group's field-effect transistor, and is mutually perpendicular to hatching a-a.
In conjunction with Fig. 1, Fig. 2 A and Fig. 2 B, it can be seen that test device group field-effect transistor FT of the prior art includes:
Source area S, is connected to testing cushion Ps of outside by outside lead (outside lead) M；Drain region D, by another outside
Portion lead-in wire M is connected to testing cushion Pd of outside；Gate regions G, is connected to the testing cushion of outside by another outside lead M again
Pg。
As shown in fig. 1, gate regions G is positioned at source area S in the channel direction of test device group field-effect transistor FT
And between the D of drain region, the width of test device group field-effect transistor FT runs through test device group's field effect transistor
The whole width of pipe FT.
Wherein, Fig. 2 A example shows the profile as viewed from the hatching a-a from Fig. 1 is upwards.As shown in Figure 2 A, survey
The source area S and drain region D of examination device group field-effect transistor FT generally extend among substrate B from the upper surface of substrate B, its
On covered by dielectric layer I, gate regions G is positioned on dielectric layer I.
Wherein, Fig. 2 B illustrate the hatching b-b from Fig. 1 to the left as viewed from profile.In order to highlight
Gate regions G and test device group field-effect transistor FT position on the width of test device group field-effect transistor FT
Relation, in fig. 2b, it is assumed that dielectric layer I is transparent, so as to see source area S, and, eliminate each outside lead M.
As shown in Figure 2 B, gate regions G runs through test device group field effect on the width of test device group field-effect transistor FT
Answer the whole width of transistor FT.As Fig. 2 B is also shown for the channel edge E near test device group field-effect transistor FT.
Fig. 3 A and Fig. 3 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 1 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION.
As shown in fig. 3, between the gate regions G and source area S at test device group field-effect transistor FT, electricity is applied
During pressure, such as, can produce Electric Field Distribution as shown by arrows in FIG., owing to the three-dimensional shape of gate regions G and source area S has one
Fixed corner angle, so, can higher one near electric field produced by the channel edge E place of test device group field-effect transistor FT
A bit.
As shown in Figure 3 B, between the source area S and drain region D of test device group field-effect transistor FT, there is conducting
During electric current, such as, can produce CURRENT DISTRIBUTION as shown by arrows in FIG..Electric current is by a fixed width between source area S and drain region D
The stereo channel of degree flows through.It is additionally, since and is produced at the channel edge E near test device group field-effect transistor FT
Electric field more higher, so the electric current that flow through is also at the channel edge E near test device group field-effect transistor FT
The most some larger.
On the other hand, due to technologic reason, at the channel edge of test device group's field-effect transistor, ratio is logical
It is easier in the middle part of road there is defective workmanship, so the reliability of the edge of test device group's field-effect transistor and operating characteristic
Can be more weaker.When test device group's field-effect transistor of the prior art used as shown in Figure 1-Figure 3 carries out tester
When part group tests, owing to not differentiating between edge and middle part reliability and the operating characteristic testing device group's field-effect transistor
Difference, therefore can not fully understand the product quality of semiconductor device, thus be unfavorable for carrying of semiconductor device product quality
High.
Summary of the invention
In order to solve one of above-mentioned technical problem, present disclose provides a kind of test device group's field-effect transistor, including:
Substrate；Source area, is positioned among described substrate；Drain region, is positioned among described substrate, and in the horizontal direction of described substrate
Positioned opposite with described source area；Dielectric layer, is covered in described substrate in the vertical direction of described substrate；And grid
District, is positioned on described dielectric layer in described vertical direction, and is positioned at described source area and described in described horizontal direction
Between drain region, wherein, described gate regions is described away from pointing to from the central area of described source area in described horizontal direction
The axis of the central area of drain region.
Wherein, described gate regions includes first grid polar region and second gate polar region, described first grid polar region and described second gate
Polar region is arranged in the both sides of described axis.
Wherein, described source area is walked around by wiring connection in chip in described first grid polar region and described second gate polar region.
Wherein, described drain region is walked around by wiring connection in chip in described first grid polar region and described second gate polar region.
Wherein, described first grid polar region and described second gate polar region are connected by outside lead.
Wherein, described source area, described drain region and described gate regions are connected to respective outside survey by outside lead
Examination pad.
Wherein, described source area, described drain region, described first grid polar region and described second gate polar region pass through outside lead
It is connected to respective external testing pad.
The disclosure additionally provides a kind of test device group's method of testing, is used for testing device group's field-effect transistor,
Described test device group's field-effect transistor, including: substrate；Source area, is positioned among described substrate；Drain region, is positioned at described
Among substrate and positioned opposite with described source area in the horizontal direction of described substrate；Dielectric layer, vertical at described substrate
Described substrate it is covered on direction；And gate regions, described vertical direction is positioned on described dielectric layer, and in institute
Stating in horizontal direction between described source area and described drain region, wherein, described gate regions is away from described horizontal direction
On point to the axis of central area of described drain region from the central area of described source area, wherein, described test device group surveys
Method for testing includes: step S100, apply the first voltage in the described gate regions of described field-effect transistor and described source area it
Between, and stop applying described first voltage after scheduled time length, in order to measure the reliability of described field-effect transistor；
And step S200, apply the second voltage between the described gate regions and described source area of described field-effect transistor, in order to
Measure the operating characteristic of described field-effect transistor.
Wherein, the first voltage described in described step S100 is that between described gate regions and described source area, maximum can be born
The expected value of voltage, and the second voltage described in described step S200 is the electricity that works between described gate regions and described source area
A class value in pressure scope.
Wherein, the first voltage described in described step S100 is 20V, and described second voltage of described step S200 is
A class value in operating voltage range-10V to+10V between described gate regions and described source area.
Wherein, in described step S100 and gate regions described in described step S200 includes first grid polar region and second grid
District, described first grid polar region and described second grid district are arranged in the both sides of described axis.
Wherein, in described step S100 and first grid polar region and described second gate polar region described in described step S200 is walked around
Described source area is connected by wiring in chip.
Wherein, in described step S100 and first grid polar region and described second gate polar region described in described step S200 is walked around
Described drain region is connected by wiring in chip.
Wherein, in described step S100 and first grid polar region and described second gate polar region described in described step S200 passes through
Outside lead connects.
Wherein, described source area, described drain region and described gate regions are connected to respective outside survey by outside lead
Examination pad.
Wherein, described source area, described drain region, described first grid polar region and described second gate polar region pass through outside lead
It is connected to respective external testing pad.
By using test device group's field-effect transistor and test device group's method of testing thereof of the disclosure, due to can
Measure reliability and the operating characteristic of the edge of test device group's field-effect transistor, therefore, it is possible to be appreciated more fully from partly leading
The product quality of body device, thus the raising of beneficially semiconductor device product quality.
Accompanying drawing explanation
Describe below with reference to appended accompanying drawing and embodiment of the disclosure, wherein:
Fig. 1 illustrates the top view of a kind of test device group's field-effect transistor of the prior art；
Fig. 2 A and Fig. 2 B illustrate respectively the hatching a-a from Fig. 1 upwards as viewed from profile and from Fig. 1
The profile looked to the left of hatching b-b；
Fig. 3 A and Fig. 3 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 1 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION；
Fig. 4 illustrates the top view of the test device group's field-effect transistor according to one embodiment of the disclosure；
Fig. 5 A and Fig. 5 B illustrate respectively the hatching a-a from Fig. 4 upwards as viewed from profile and from Fig. 4
The profile looked to the left of hatching b-b；
Fig. 6 A and Fig. 6 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 4 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION；
Fig. 7 illustrates the vertical view of the test device group's field-effect transistor according to another embodiment of the disclosure
Figure；
Fig. 8 A and Fig. 8 B illustrate respectively the hatching a-a from Fig. 7 upwards as viewed from profile and from Fig. 7
The profile looked to the left of hatching b-b；
Fig. 9 A and Fig. 9 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 7 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION；And
Figure 10 illustrates the flow chart of test device group's method of testing of the disclosure.
Detailed description of the invention
Describing the disclosure in detail below in conjunction with Fig. 4 to Figure 10, the most identical reference represents same or analogous
Equipment, unit, material or structure.
Fig. 4 illustrates the top view of the test device group's field-effect transistor according to one embodiment of the disclosure.
Fig. 5 A and Fig. 5 B illustrate respectively the hatching a-a from Fig. 4 upwards as viewed from profile and hatching from Fig. 4
The profile that b-b looks to the left, wherein, hatching a-a is the current channel direction of test device group's field-effect transistor, section
Line b-b is positioned on the width of test device group's field-effect transistor, and is mutually perpendicular to hatching a-a.
In conjunction with Fig. 4, Fig. 5 A and Fig. 5 B, it can be seen that the test device group field-effect transistor FT1 of the disclosure includes: lining
End B；Source area S, is positioned among substrate B；Drain region D, is positioned among substrate B, and at horizontal direction (the i.e. tester of substrate B
The current channel direction of part group field-effect transistor FT1) upper and source area S-phase is to layout；Dielectric layer I, at the Vertical Square of substrate B
Upwards it is covered on substrate B, is i.e. covered on source area S and drain region D；And gate regions G1, in described vertical direction
On be positioned on dielectric layer I, and in described horizontal direction between source area S and drain region D, wherein, gate regions G1 is remote
From axis (i.e. hatching a-from the central area of sensing drain region, the central area D of source area S in described horizontal direction
A), say, that gate regions G1 is deviation test device group field effect on the width of test device group field-effect transistor FT1
Answer the middle part of the passage of transistor FT1, and at the channel edge E of test device group field-effect transistor FT1.
Wherein, source area S is connected to testing cushion Ps of outside by outside lead M, and drain region D is drawn by another outside
Line M is connected to testing cushion Pd of outside, and gate regions G1 is connected to testing cushion Pg of outside by another outside lead M again.
Wherein, Fig. 5 B illustrate the hatching b-b from Fig. 4 to the left as viewed from profile.In order to highlight
Gate regions G1 and test device group field-effect transistor FT1 is on the width of test device group field-effect transistor FT1
Position relationship, in figure 5b, it is assumed that dielectric layer I is transparent, so as to see source area S, and, eliminate each outside and draw
Line M.As shown in Figure 5 B, gate regions G1 deviation test device on the width of test device group field-effect transistor FT1
The middle part of the passage of group field-effect transistor FT1, and at the channel edge E of test device group field-effect transistor FT1.
Fig. 6 A and Fig. 6 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 4 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION.
As shown in FIG, apply between the gate regions G1 and source area S at test device group field-effect transistor FT1
During voltage, such as, can produce Electric Field Distribution as shown by arrows in FIG., electric field is primarily present near test device group's field effect
At the edge E of the passage side of transistor FT1.
As depicted in figure 6b, exist and lead between the source area S and drain region D of test device group field-effect transistor FT1
During galvanization, such as, can produce CURRENT DISTRIBUTION as shown by arrows in FIG., electric current is primarily present near test device group field effect
Answer at the edge E of passage side of transistor FT1.
Fig. 7 illustrates the vertical view of the test device group's field-effect transistor according to another embodiment of the disclosure
Figure.Fig. 8 A and Fig. 8 B illustrate respectively the hatching a-a from Fig. 7 upwards as viewed from profile and cuing open from Fig. 7
The profile that upper thread b-b looks to the left, wherein, hatching a-a is the current channel direction of test device group's field-effect transistor,
Hatching b-b is positioned on the width of test device group's field-effect transistor, and is mutually perpendicular to hatching a-a.
In conjunction with Fig. 7, Fig. 8 A and Fig. 8 B, it can be seen that the test device of the disclosure as shown in Fig. 7, Fig. 8 A and Fig. 8 B
Group field-effect transistor FT2 and the test device group field-effect transistor FT1 of the disclosure as shown in Fig. 4, Fig. 5 A and Fig. 5 B
Difference be, the gate regions of the test device group field-effect transistor FT2 of the disclosure as shown in Fig. 7, Fig. 8 A and Fig. 8 B
In addition to including gate regions G1, also include that gate regions G2, gate regions G1 and gate regions G2 are respectively arranged and (i.e. survey in the horizontal direction
Examination device group field-effect transistor FT2 current channel direction) on from the center of sensing drain region, the central area D of source area S
The both sides of the axis (i.e. hatching a-a) in region, say, that gate regions G1 and gate regions G2 is brilliant in test device group's field effect
The middle part of the passage of test device group field-effect transistor FT2 it is respectively offset from the width of body pipe FT2, and near tester
At the channel edge E of part group field-effect transistor FT2.As shown in Fig. 7, Fig. 8 A and Fig. 8 B, the test device group field of the disclosure
The source area S of effect transistor FT2, drain region D, gate regions G1 and gate regions G2 are connected to respective outside by outside lead
Testing cushion.
As an embodiment, as shown in Fig. 7, Fig. 8 A and Fig. 8 B, test device group's field-effect transistor of the disclosure
The gate regions G1 and gate regions G2 of FT2 can be walked around drain region D and be connected by wiring (on-chip wire) in chip.
Additionally, as an embodiment, the gate regions G1 of the test device group field-effect transistor FT2 of the disclosure and grid
District G2 can also be walked around source area S and be connected by wiring in chip.
Additionally, as an embodiment, the gate regions G1 of the test device group field-effect transistor FT2 of the disclosure and grid
District G2 can also be linked together by outside lead respectively.
Fig. 9 A and Fig. 9 B illustrates the Electric Field Distribution in the test device group's field-effect transistor in Fig. 7 respectively
Schematic diagram and the schematic diagram of CURRENT DISTRIBUTION.
As illustrated in figure 9 a, between gate regions G1, G2 and the source area S at test device group field-effect transistor FT2
When applying voltage, such as, can produce Electric Field Distribution as shown by arrows in FIG., electric field is primarily present near test device group field
At the edge E of the passage both sides of effect transistor FT2.
As shown in fig. 9b, exist and lead between the source area S and drain region D of test device group field-effect transistor FT2
During galvanization, such as, can produce CURRENT DISTRIBUTION as shown by arrows in FIG., electric current is primarily present near test device group field effect
Answer at the edge E of passage both sides of transistor FT2.
Use test device group's field-effect transistor of the disclosure as above, the test device of the disclosure can be carried out
Group's test.
Figure 10 illustrates the flow chart of test device group's method of testing of the disclosure.As shown in Figure 10, these public affairs
The test device group's method of testing opened for test test device group's field-effect transistor as shown in Fig. 4 to Fig. 9, including:
Step S100, applies the first voltage between gate regions and the source area of scene effect transistor, and in the scheduled time
Stop after length applying the first voltage, in order to measuring the reliability of field-effect transistor, the voltage of such as oxide layer bears energy
Power.The most such as first voltage is the maximum expected value that can bear voltage, the unidirectional current of such as 20V between gate regions and source area
Pressure.
Step S200, applies the second voltage between gate regions and the source area of scene effect transistor, in order to measure field effect
The transfer characteristic of operating characteristic when answering transistor normally to use, such as field-effect transistor.The most such as second voltage is grid
A class value in operating voltage range between polar region and source area, such as from the one of-10V to+10V group of DC voltage value.
Additionally, as an embodiment, with described in step S100 described in test device group's method of testing of the disclosure
Gate regions described in step S200 includes first grid polar region and second gate polar region, described first grid polar region and described second gate polar region
It is arranged in the both sides of described axis.
Additionally, as an embodiment, with described in step S100 described in test device group's method of testing of the disclosure
First grid polar region described in step S200 and described second gate polar region are walked around described source area and are connected by wiring in chip.
Additionally, as an embodiment, with described in step S100 described in test device group's method of testing of the disclosure
First grid polar region described in step S200 and described second gate polar region are walked around described drain region and are connected by wiring in chip.
Additionally, as an embodiment, with described in step S100 described in test device group's method of testing of the disclosure
First grid polar region described in step S200 and described second gate polar region are connected by outside lead.
Additionally, as an embodiment, source area, described drain region described in test device group's method of testing of the disclosure
It is connected to respective external testing pad by outside lead with described gate regions.
Additionally, as an embodiment, source area, described drain electrode described in test device group's method of testing of the disclosure
District, described first grid polar region and described second gate polar region are connected to respective external testing pad by outside lead.
By using test device group's field-effect transistor and test device group's method of testing thereof of the disclosure, due to can
Measure reliability and the operating characteristic of the edge of test device group's field-effect transistor, therefore, it is possible to be appreciated more fully from partly leading
The product quality of body device, thus the raising of beneficially semiconductor device product quality.
Although with reference to exemplary embodiment describing the disclosure, it is to be understood that, term used be explanation and exemplary,
And nonrestrictive term.Owing to the disclosure can be embodied as in a variety of forms, it should therefore be appreciated that above-described embodiment does not limits
In any aforesaid details, and should explain widely in appended claims limited range, therefore fall into claim
Or whole changes and the remodeling in its equivalency range all should be appended claims and contained.
Claims (18)
1. test device group's field-effect transistor, including:
Substrate；
Source area, is positioned among described substrate；
Drain region, is positioned among described substrate, and positioned opposite with described source area in the horizontal direction of described substrate；
Dielectric layer, is covered in described substrate in the vertical direction of described substrate；And
Gate regions, is positioned on described dielectric layer in described vertical direction, and is positioned at described source electrode in described horizontal direction
Between district and described drain region,
Wherein, described gate regions is away from pointing to described drain region in described horizontal direction from the central area of described source area
The axis of central area.
Test device group's field-effect transistor the most according to claim 1, wherein,
Described gate regions includes first grid polar region and second gate polar region, described first grid polar region and described second grid district cloth respectively
Put the both sides at described axis.
Test device group's field-effect transistor the most according to claim 2, wherein,
Described first grid polar region and described second gate polar region are walked around described source area and are connected by wiring in chip.
Test device group's field-effect transistor the most according to claim 2, wherein,
Described first grid polar region and described second gate polar region are walked around described drain region and are connected by wiring in chip.
Test device group's field-effect transistor the most according to claim 2, wherein,
Described first grid polar region and described second gate polar region are connected by outside lead.
Test device group's field-effect transistor the most according to claim 1, wherein,
Described source area, described drain region and described gate regions are connected to respective external testing pad by outside lead.
7. according to the test device group's field-effect transistor according to any one of claim 2-5, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to respectively by outside lead
From external testing pad.
8. test device group's method of testing, is used for testing device group's field-effect transistor, described test device group field
Effect transistor, including: substrate；Source area, is positioned among described substrate；Drain region, is positioned among described substrate, and described
In the horizontal direction of substrate positioned opposite with described source area；Dielectric layer, is covered in described in the vertical direction of described substrate
Substrate；And gate regions, described vertical direction is positioned on described dielectric layer, and is positioned in described horizontal direction
Between described source area and described drain region, wherein, described gate regions away from described horizontal direction from described source area
The axis of the central area of described drain region is pointed in central area, and wherein, described test device group's method of testing includes:
Step S100, applies the first voltage between the described gate regions and described source area of described field-effect transistor, and
Stop after scheduled time length applying described first voltage, in order to measure the reliability of described field-effect transistor；And
Step S200, applies the second voltage between the described gate regions and described source area of described field-effect transistor, in order to
Measure the operating characteristic of described field-effect transistor.
Test device group's method of testing the most according to claim 8, wherein,
First voltage described in described step S100 is the maximum phase that can bear voltage between described gate regions and described source area
Prestige value, and the second voltage described in described step S200 is between described gate regions and described source area in operating voltage range
A class value.
Test device group's method of testing the most according to claim 9, wherein,
First voltage described in described step S100 is 20V, and described second voltage of described step S200 is described grid
A class value in operating voltage range-10V to+10V between district and described source area.
11. test device group's method of testings according to any one of-10 according to Claim 8, wherein,
In described step S100 and gate regions described in described step S200 includes first grid polar region and second gate polar region, described the
One gate regions and described second grid district are arranged in the both sides of described axis.
12. test device group's method of testings according to claim 11, wherein,
Described source electrode is walked around in described step S100 and first grid polar region and described second gate polar region described in described step S200
District is connected by wiring in chip.
13. test device group's method of testings according to claim 11, wherein,
Described drain electrode is walked around in described step S100 and first grid polar region and described second gate polar region described in described step S200
District is connected by wiring in chip.
14. test device group's method of testings according to claim 11, wherein,
In described step S100 and first grid polar region and described second gate polar region described in described step S200 passes through outside lead
Connect.
15. test device group's method of testings according to any one of-10 according to Claim 8, wherein,
Described source area, described drain region and described gate regions are connected to respective external testing pad by outside lead.
16. test device group's method of testings according to claim 11, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to respectively by outside lead
From external testing pad.
17. according to the test device group's method of testing according to any one of claim 12-14, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to respectively by outside lead
From external testing pad.
18. test device group's method of testings according to claim 15, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to respectively by outside lead
From external testing pad.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410143407.XA CN103928523B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's field-effect transistor and test device group's method of testing thereof |
| TW104111168A TWI552246B (en) | 2014-04-10 | 2015-04-07 | Test element group field-effect transistor and ?the testing method thereof |
| KR1020150050157A KR20150117615A (en) | 2014-04-10 | 2015-04-09 | TEG-FET and METHOD for TESTING TEG |
| JP2015080092A JP2015204460A (en) | 2014-04-10 | 2015-04-09 | Teg-fet, and teg test method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410143407.XA CN103928523B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's field-effect transistor and test device group's method of testing thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103928523A CN103928523A (en) | 2014-07-16 |
| CN103928523B true CN103928523B (en) | 2016-08-24 |
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| CN106653641B (en) * | 2017-01-10 | 2019-05-10 | 京东方科技集团股份有限公司 | A kind of electrical performance test method of TFT making technology |
| CN108470728B (en) * | 2018-03-13 | 2020-03-31 | 西安交通大学 | Pad structure compatible with electrical test and optical interconnection simultaneously and test method thereof |
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| CN102176442A (en) * | 2011-02-22 | 2011-09-07 | 北京大学 | Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device |
| CN102393501A (en) * | 2011-10-14 | 2012-03-28 | 哈尔滨工业大学 | MOSFET reliability test analysis system and method thereof |
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| CN102393501A (en) * | 2011-10-14 | 2012-03-28 | 哈尔滨工业大学 | MOSFET reliability test analysis system and method thereof |
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| CN103928523A (en) | 2014-07-16 |
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| KR20150117615A (en) | 2015-10-20 |
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