CN103928523A - Test device group field effect transistor and test device group test method thereof - Google Patents
Test device group field effect transistor and test device group test method thereof Download PDFInfo
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- CN103928523A CN103928523A CN201410143407.XA CN201410143407A CN103928523A CN 103928523 A CN103928523 A CN 103928523A CN 201410143407 A CN201410143407 A CN 201410143407A CN 103928523 A CN103928523 A CN 103928523A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
A test device group field effect transistor comprises a substrate, a source electrode region, a drain electrode region, a dielectric layer and a gate electrode region, wherein the source electrode region is located in the substrate; the drain electrode region is located in the substrate and opposite to the source electrode region in the horizontal direction of the substrate; the substrate is covered with the dielectric layer in the vertical direction of the substrate; the gate electrode region is located on the dielectric layer in the vertical direction and located between the source electrode region and the drain electrode region in the horizontal direction, and the gate electrode region is far away from the axis, oriented to the central area of the drain electrode region from the central area of the source electrode region in the direction. A test device group test method is used for testing the field effect transistor. Reliability and work characteristics of the edge of the test device group field effect transistor can be tested, product quality of semiconductor devices can be known more comprehensively, and improvement on product quality of the semiconductor devices is facilitated.
Description
Technical field
The disclosure relates to a kind of field-effect transistor, relates in particular to a kind of field-effect transistor for test component group (TEG:Test Element Group), and test component group method of testing for this field-effect transistor is tested.
Background technology
In semiconductor device production process, often adopt test component group to monitor product performance or the technique performance of semiconductor device.
For example, Fig. 1 illustrates a kind of vertical view of test component group field-effect transistor of the prior art.Fig. 2 A and Fig. 2 B illustrate respectively the profile that profile that the hatching a-a from Fig. 1 upwards looks and the hatching b-b from Fig. 1 look left, wherein, hatching a-a is current channel (the being raceway groove) direction of test component group field-effect transistor, hatching b-b is positioned on the Width of test component group field-effect transistor, and mutually vertical with hatching a-a.
In conjunction with Fig. 1, Fig. 2 A and Fig. 2 B, can see, test component group field-effect transistor FT of the prior art comprises: source area S, by outside lead (outside lead), M is connected to outside testing cushion Ps; Drain region D, by another outside lead, M is connected to outside testing cushion Pd; Gate regions G, is connected to outside testing cushion Pg by another outside lead M again.
As shown in fig. 1, gate regions G between source area S and drain region D, runs through the whole width of test component group field-effect transistor FT in the channel direction of test component group field-effect transistor FT on the Width of test component group field-effect transistor FT.
Wherein, Fig. 2 A example shows the profile that the hatching a-a from Fig. 1 upwards looks.As shown in Figure 2 A, source area S and the drain region D of test component group field-effect transistor FT extend among substrate B from the upper surface of substrate B conventionally, on it, are covered by dielectric layer I, and gate regions G is positioned on dielectric layer I.
Wherein, Fig. 2 B illustrates the profile that the hatching b-b from Fig. 1 looks left.In order to highlight gate regions G and the position relationship of test component group field-effect transistor FT on the Width of test component group field-effect transistor FT, in Fig. 2 B, suppose that dielectric layer I is transparent, to can see source area S, and, omitted each outside lead M.As shown in Figure 2 B, gate regions G runs through the whole width of test component group field-effect transistor FT on the Width of test component group field-effect transistor FT.As also shown the channel edge E near test component group field-effect transistor FT in Fig. 2 B.
Fig. 3 A and Fig. 3 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 1.
As shown in Fig. 3 A, when apply voltage between the gate regions G of test component group field-effect transistor FT and source area S time, for example can produce Electric Field Distribution as shown by arrows in FIG., because the three-dimensional shape of gate regions G and source area S has certain corner angle, so the electric field producing in the channel edge E place near test component group field-effect transistor FT can be stronger.
As shown in Figure 3 B, in the time there is On current between the source area S of test component group field-effect transistor FT and drain region D, for example, can produce CURRENT DISTRIBUTION as shown by arrows in FIG..In the stereo channel of electric current by certain width between source area S and drain region D, flow through.And the electric field producing due to the channel edge E place near test component group field-effect transistor FT is stronger, so also correspondingly larger at the electric current flowing through near the channel edge E place of test component group field-effect transistor FT.
On the other hand, due to technologic reason, more easily there is defective workmanship near the channel edge place of test component group field-effect transistor than channel middle, so the reliability of the edge of test component group field-effect transistor and operating characteristic can be more weaker.When adopting the test component group field-effect transistor of prior art as shown in Figure 1-Figure 3 to carry out test component group while testing, due to the difference between edge and middle part reliability and the operating characteristic of distinguishing tests device group field-effect transistor not, therefore can not fully understand the product quality of semiconductor device, thereby be unfavorable for the raising of semiconductor device product quality.
Summary of the invention
In order one of to solve the problems of the technologies described above, the disclosure provides a kind of test component group field-effect transistor, comprising: substrate; Source area, is positioned among described substrate; Drain region, is positioned among described substrate, and in the horizontal direction of described substrate with described source area positioned opposite; Dielectric layer is covered on described substrate in the vertical direction of described substrate; And gate regions, in described vertical direction, be positioned on described dielectric layer, and in described horizontal direction between described source area and described drain region, wherein, the axis of the central area of described drain region is pointed in described gate regions away from the central area from described source area in described horizontal direction.
Wherein, described gate regions comprises first grid polar region and second gate polar region, and described first grid polar region and described second grid district are arranged in the both sides of described axis.
Wherein, described source area is walked around by connecting up and be connected in chip with described second gate polar region in described first grid polar region.
Wherein, described drain region is walked around by connecting up and be connected in chip with described second gate polar region in described first grid polar region.
Wherein, described first grid polar region is connected by outside lead with described second gate polar region.
Wherein, described source area, described drain region and described gate regions are connected to external testing pad separately by outside lead.
Wherein, described source area, described drain region, described first grid polar region and described second gate polar region are connected to external testing pad separately by outside lead.
The disclosure also provides a kind of test component group method of testing, and for testing test component group field-effect transistor, described test component group field-effect transistor, comprising: substrate, source area, is positioned among described substrate, drain region, is positioned among described substrate, and in the horizontal direction of described substrate with described source area positioned opposite, dielectric layer is covered on described substrate in the vertical direction of described substrate, and gate regions, in described vertical direction, be positioned on described dielectric layer, and in described horizontal direction between described source area and described drain region, wherein, the axis of the central area of described drain region is pointed in described gate regions away from the central area from described source area in described horizontal direction, wherein, described test component group method of testing comprises: step S100, apply the first voltage between the described gate regions and described source area of described field-effect transistor, and after scheduled time length, stop applying described the first voltage, to measure the reliability of described field-effect transistor, and step S200, apply second voltage between the described gate regions and described source area of described field-effect transistor, to measure the operating characteristic of described field-effect transistor.
Wherein, the first voltage described in described step S100 is the maximum desired value that can bear voltage between described gate regions and described source area, and second voltage described in described step S200 is the class value in operating voltage range between described gate regions and described source area.
Wherein, the first voltage described in described step S100 is 20V, and the described second voltage of described step S200 be between described gate regions and described source area operating voltage range-10V to the class value in+10V.
Wherein, in described step S100 and gate regions described in described step S200 comprises first grid polar region and second gate polar region, and described first grid polar region and described second grid district are arranged in the both sides of described axis.
Wherein, in described step S100, walking around described source area with first grid polar region described in described step S200 and described second gate polar region is connected by wiring in chip.
Wherein, in described step S100, walking around described drain region with first grid polar region described in described step S200 and described second gate polar region is connected by wiring in chip.
Wherein, in described step S100, be connected by outside lead with described second gate polar region with first grid polar region described in described step S200.
Wherein, described source area, described drain region and described gate regions are connected to external testing pad separately by outside lead.
Wherein, described source area, described drain region, described first grid polar region and described second gate polar region are connected to external testing pad separately by outside lead.
By adopting test component group field-effect transistor of the present disclosure and test component group method of testing thereof, owing to can measuring reliability and the operating characteristic of edge of test component group field-effect transistor, therefore can more fully understand the product quality of semiconductor device, thereby be conducive to the raising of semiconductor device product quality.
Brief description of the drawings
Below with reference to appended accompanying drawing, embodiment of the present disclosure is described, wherein:
Fig. 1 illustrates a kind of vertical view of test component group field-effect transistor of the prior art;
Fig. 2 A and Fig. 2 B illustrate respectively the profile that profile that the hatching a-a from Fig. 1 upwards looks and the hatching b-b from Fig. 1 look left;
Fig. 3 A and Fig. 3 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 1;
Fig. 4 illustrates according to the vertical view of the test component group field-effect transistor of an embodiment of the disclosure;
Fig. 5 A and Fig. 5 B illustrate respectively the profile that profile that the hatching a-a from Fig. 4 upwards looks and the hatching b-b from Fig. 4 look left;
Fig. 6 A and Fig. 6 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 4;
Fig. 7 illustrates according to the vertical view of the test component group field-effect transistor of another embodiment of the disclosure;
Fig. 8 A and Fig. 8 B illustrate respectively the profile that profile that the hatching a-a from Fig. 7 upwards looks and the hatching b-b from Fig. 7 look left;
Fig. 9 A and Fig. 9 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 7; And
Figure 10 illustrates the flow chart of test component group method of testing of the present disclosure.
Embodiment
Describe the disclosure in detail below in conjunction with Fig. 4 to Figure 10, wherein identical Reference numeral represents same or analogous equipment, unit, material or structure.
Fig. 4 illustrates according to the vertical view of the test component group field-effect transistor of an embodiment of the disclosure.Fig. 5 A and Fig. 5 B illustrate respectively the profile that profile that the hatching a-a from Fig. 4 upwards looks and the hatching b-b from Fig. 4 look left, wherein, hatching a-a is the current channel direction of test component group field-effect transistor, hatching b-b is positioned on the Width of test component group field-effect transistor, and mutually vertical with hatching a-a.
In conjunction with Fig. 4, Fig. 5 A and Fig. 5 B, can see, test component group field-effect transistor FT1 of the present disclosure comprises: substrate B; Source area S, is positioned among substrate B; Drain region D, is positioned among substrate B, and goes up and source area S positioned opposite in the horizontal direction (being the current channel direction of test component group field-effect transistor FT1) of substrate B; Dielectric layer I is covered on substrate B in the vertical direction of substrate B, is covered on source area S and drain region D; And gate regions G1, in described vertical direction, be positioned on dielectric layer I, and in described horizontal direction between source area S and drain region D, wherein, gate regions G1 is away from the axis (being hatching a-a) from the central area of sensing drain region, the central area D of source area S in described horizontal direction, that is to say, gate regions G1 departs from the middle part of the passage of test component group field-effect transistor FT1 on the Width of test component group field-effect transistor FT1, and the channel edge E place of close test component group field-effect transistor FT1.
Wherein, source area S is connected to outside testing cushion Ps by outside lead M, and drain region D is connected to outside testing cushion Pd by another outside lead M, and gate regions G1 is connected to outside testing cushion Pg by another outside lead M again.
Wherein, Fig. 5 B illustrates the profile that the hatching b-b from Fig. 4 looks left.In order to highlight gate regions G1 and the position relationship of test component group field-effect transistor FT1 on the Width of test component group field-effect transistor FT1, in Fig. 5 B, suppose that dielectric layer I is transparent, to can see source area S, and, omitted each outside lead M.As shown in Figure 5 B, gate regions G1 departs from the middle part of the passage of test component group field-effect transistor FT1 on the Width of test component group field-effect transistor FT1, and the channel edge E place of close test component group field-effect transistor FT1.
Fig. 6 A and Fig. 6 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 4.
As shown in Fig. 6 A, when apply voltage between the gate regions G1 of test component group field-effect transistor FT1 and source area S time, for example can produce Electric Field Distribution as shown by arrows in FIG., electric field is mainly present in the E place, edge near passage one side of test component group field-effect transistor FT1.
As shown in Fig. 6 B, in the time there is On current between the source area S of test component group field-effect transistor FT1 and drain region D, for example can produce CURRENT DISTRIBUTION as shown by arrows in FIG., electric current is mainly present in the E place, edge near passage one side of test component group field-effect transistor FT1.
Fig. 7 illustrates according to the vertical view of the test component group field-effect transistor of another embodiment of the disclosure.Fig. 8 A and Fig. 8 B illustrate respectively the profile that profile that the hatching a-a from Fig. 7 upwards looks and the hatching b-b from Fig. 7 look left, wherein, hatching a-a is the current channel direction of test component group field-effect transistor, hatching b-b is positioned on the Width of test component group field-effect transistor, and mutually vertical with hatching a-a.
In conjunction with Fig. 7, Fig. 8 A and Fig. 8 B, can see, as Fig. 7, test component group field-effect transistor FT2 of the present disclosure shown in Fig. 8 A and Fig. 8 B with as Fig. 4, the difference of test component group field-effect transistor FT1 of the present disclosure shown in Fig. 5 A and Fig. 5 B is, as Fig. 7, the gate regions of test component group field-effect transistor FT2 of the present disclosure shown in Fig. 8 A and Fig. 8 B is except comprising gate regions G1, also comprise gate regions G2, gate regions G1 and gate regions G2 are arranged in the both sides of the axis (being hatching a-a) of the central area of upper sensing drain region, the central area D from source area S of horizontal direction (being the current channel direction of test component group field-effect transistor FT2), that is to say, gate regions G1 and gate regions G2 depart from respectively the middle part of the passage of test component group field-effect transistor FT2 on the Width of test component group field-effect transistor FT2, and the channel edge E place of close test component group field-effect transistor FT2.As shown in Fig. 7, Fig. 8 A and Fig. 8 B, source area S, drain region D, gate regions G1 and the gate regions G2 of test component group field-effect transistor FT2 of the present disclosure are connected to external testing pad separately by outside lead.
As an embodiment, as shown in Fig. 7, Fig. 8 A and Fig. 8 B, the gate regions G1 of test component group field-effect transistor FT2 of the present disclosure can walk around drain region D with gate regions G2 and be connected by wiring (on-chip wire) in chip.
In addition,, as an embodiment, the gate regions G1 of test component group field-effect transistor FT2 of the present disclosure also can walk around source area S with gate regions G2 and be connected by wiring in chip.
In addition,, as an embodiment, gate regions G1 and the gate regions G2 of test component group field-effect transistor FT2 of the present disclosure also can link together by outside lead respectively.
Fig. 9 A and Fig. 9 B illustrate respectively the schematic diagram of Electric Field Distribution and the schematic diagram of CURRENT DISTRIBUTION in the test component group field-effect transistor in Fig. 7.
As shown in Fig. 9 A, when apply voltage between gate regions G1, the G2 of test component group field-effect transistor FT2 and source area S time, for example can produce Electric Field Distribution as shown by arrows in FIG., electric field is mainly present in the E place, edge near the passage both sides of test component group field-effect transistor FT2.
As shown in Fig. 9 B, in the time there is On current between the source area S of test component group field-effect transistor FT2 and drain region D, for example can produce CURRENT DISTRIBUTION as shown by arrows in FIG., electric current is mainly present in the E place, edge near the passage both sides of test component group field-effect transistor FT2.
Adopt test component group field-effect transistor of the present disclosure as above, can carry out test component group test of the present disclosure.
Figure 10 illustrates the flow chart of test component group method of testing of the present disclosure.As shown in Figure 10, test component group method of testing of the present disclosure, for testing the test component group field-effect transistor as shown in Fig. 4 to Fig. 9, comprising:
Step S100, applies the first voltage between the transistorized gate regions of being on the scene effect and source area, and stop applying the first voltage after scheduled time length, so as the reliability of measurement field effect transistor, the voltage ability to bear of for example oxide layer.Wherein for example the first voltage is the maximum desired value that can bear voltage between gate regions and source area, the direct voltage of for example 20V.
Step S200, applies second voltage between the transistorized gate regions of being on the scene effect and source area, so as the operating characteristic of measurement field effect transistor while normally using, the transfer characteristic of for example field-effect transistor.Wherein for example second voltage is the class value in operating voltage range between gate regions and source area, for example one group of DC voltage value from 10V to+10V.
In addition, as an embodiment, described in test component group method of testing of the present disclosure, in step S100 and gate regions described in described step S200 comprises first grid polar region and second gate polar region, and described first grid polar region and described second grid district are arranged in the both sides of described axis.
In addition,, as an embodiment, described in test component group method of testing of the present disclosure, in step S100, walk around described source area with first grid polar region described in described step S200 and described second gate polar region and be connected by wiring in chip.
In addition,, as an embodiment, described in test component group method of testing of the present disclosure, in step S100, walk around described drain region with first grid polar region described in described step S200 and described second gate polar region and be connected by wiring in chip.
In addition, as an embodiment, described in test component group method of testing of the present disclosure, in step S100, be connected by outside lead with described second gate polar region with first grid polar region described in described step S200.
In addition,, as an embodiment, described in test component group method of testing of the present disclosure, source area, described drain region and described gate regions are connected to external testing pad separately by outside lead.
In addition,, as an embodiment, described in test component group method of testing of the present disclosure, source area, described drain region, described first grid polar region and described second gate polar region are connected to external testing pad separately by outside lead.
By adopting test component group field-effect transistor of the present disclosure and test component group method of testing thereof, owing to can measuring reliability and the operating characteristic of edge of test component group field-effect transistor, therefore can more fully understand the product quality of semiconductor device, thereby be conducive to the raising of semiconductor device product quality.
Although described the disclosure with reference to exemplary embodiments, should be appreciated that term used is explanation and exemplary and nonrestrictive term.Because the disclosure can specifically be implemented in a variety of forms, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and should explain widely enclosing in claim limited range, therefore fall into whole variations in claim or its equivalency range and remodeling and all should be the claim of enclosing and contain.
Claims (16)
1. a test component group field-effect transistor, comprising:
Substrate;
Source area, is positioned among described substrate;
Drain region, is positioned among described substrate, and in the horizontal direction of described substrate with described source area positioned opposite;
Dielectric layer is covered on described substrate in the vertical direction of described substrate; And
Gate regions is positioned on described dielectric layer in described vertical direction, and in described horizontal direction between described source area and described drain region,
Wherein, the axis of the central area of described drain region is pointed in described gate regions away from the central area from described source area in described horizontal direction.
2. test component group field-effect transistor according to claim 1, wherein,
Described gate regions comprises first grid polar region and second gate polar region, and described first grid polar region and described second grid district are arranged in the both sides of described axis.
3. test component group field-effect transistor according to claim 2, wherein,
Described first grid polar region is walked around described source area with described second gate polar region and is connected by wiring in chip.
4. test component group field-effect transistor according to claim 2, wherein,
Described first grid polar region is walked around described drain region with described second gate polar region and is connected by wiring in chip.
5. test component group field-effect transistor according to claim 2, wherein,
Described first grid polar region is connected by outside lead with described second gate polar region.
6. test component group field-effect transistor according to claim 1, wherein,
Described source area, described drain region and described gate regions are connected to external testing pad separately by outside lead.
7. according to the test component group field-effect transistor described in any one in claim 2-5, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to external testing pad separately by outside lead.
8. a test component group method of testing, for testing test component group field-effect transistor, described test component group field-effect transistor, comprising: substrate; Source area, is positioned among described substrate; Drain region, is positioned among described substrate, and in the horizontal direction of described substrate with described source area positioned opposite; Dielectric layer is covered on described substrate in the vertical direction of described substrate; And gate regions, in described vertical direction, be positioned on described dielectric layer, and in described horizontal direction between described source area and described drain region, wherein, the axis of the central area of described drain region is pointed in described gate regions away from the central area from described source area in described horizontal direction, wherein, described test component group method of testing comprises:
Step S100, applies the first voltage between the described gate regions and described source area of described field-effect transistor, and after scheduled time length, stops applying described the first voltage, to measure the reliability of described field-effect transistor; And
Step S200, applies second voltage between the described gate regions and described source area of described field-effect transistor, to measure the operating characteristic of described field-effect transistor.
9. test component group method of testing according to claim 8, wherein,
The first voltage described in described step S100 is the maximum desired value that can bear voltage between described gate regions and described source area, and second voltage described in described step S200 is the class value in operating voltage range between described gate regions and described source area.
10. test component group method of testing according to claim 9, wherein,
The first voltage described in described step S100 is 20V, and the described second voltage of described step S200 be between described gate regions and described source area operating voltage range-10V to the class value in+10V.
Test component group method of testing in 11. according to Claim 8-10 described in any one, wherein,
In described step S100 and gate regions described in described step S200 comprises first grid polar region and second gate polar region, and described first grid polar region and described second grid district are arranged in the both sides of described axis.
12. test component group method of testings according to claim 11, wherein,
In described step S100, walking around described source area with first grid polar region described in described step S200 and described second gate polar region is connected by wiring in chip.
13. test component group method of testings according to claim 11, wherein,
In described step S100, walking around described drain region with first grid polar region described in described step S200 and described second gate polar region is connected by wiring in chip.
14. test component group method of testings according to claim 11, wherein,
In described step S100, be connected by outside lead with described second gate polar region with first grid polar region described in described step S200.
Test component group method of testing in 15. according to Claim 8-10 described in any one, wherein,
Described source area, described drain region and described gate regions are connected to external testing pad separately by outside lead.
16. according to the test component group method of testing described in any one in claim 11-15, wherein,
Described source area, described drain region, described first grid polar region and described second gate polar region are connected to external testing pad separately by outside lead.
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| CN201410143407.XA CN103928523B (en) | 2014-04-10 | 2014-04-10 | A kind of test device group's field-effect transistor and test device group's method of testing thereof |
| TW104111168A TWI552246B (en) | 2014-04-10 | 2015-04-07 | Test element group field-effect transistor and ?the testing method thereof |
| KR1020150050157A KR20150117615A (en) | 2014-04-10 | 2015-04-09 | TEG-FET and METHOD for TESTING TEG |
| JP2015080092A JP2015204460A (en) | 2014-04-10 | 2015-04-09 | Teg-fet, and teg test method thereof |
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| CN106653641B (en) * | 2017-01-10 | 2019-05-10 | 京东方科技集团股份有限公司 | A kind of electrical performance test method of TFT making technology |
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| CN102176442B (en) * | 2011-02-22 | 2012-12-05 | 北京大学 | Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device |
| TWI520244B (en) * | 2011-09-20 | 2016-02-01 | 聯華電子股份有限公司 | Circuit structure of testkey and method for testing testkey |
| CN102393501B (en) * | 2011-10-14 | 2013-11-13 | 哈尔滨工业大学 | MOSFET reliability test analysis system and method thereof |
-
2014
- 2014-04-10 CN CN201410143407.XA patent/CN103928523B/en active Active
-
2015
- 2015-04-07 TW TW104111168A patent/TWI552246B/en not_active IP Right Cessation
- 2015-04-09 KR KR1020150050157A patent/KR20150117615A/en not_active Application Discontinuation
- 2015-04-09 JP JP2015080092A patent/JP2015204460A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810137A (en) * | 2016-05-31 | 2016-07-27 | 京东方科技集团股份有限公司 | Array substrate and detection method thereof |
| CN105810137B (en) * | 2016-05-31 | 2019-01-04 | 京东方科技集团股份有限公司 | Array substrate and its detection method |
| CN108470728A (en) * | 2018-03-13 | 2018-08-31 | 西安交通大学 | The pad structure and its test method of compatible electrical testing and optics interconnection simultaneously |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI552246B (en) | 2016-10-01 |
| JP2015204460A (en) | 2015-11-16 |
| CN103928523B (en) | 2016-08-24 |
| TW201539603A (en) | 2015-10-16 |
| KR20150117615A (en) | 2015-10-20 |
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