TWI552246B - Test element group field-effect transistor and ?the testing method thereof - Google Patents

Description

Test device group field effect transistor and test device group test method thereof

The present disclosure relates to a field effect transistor, and more particularly to a field effect transistor for a test device group (TEG: Test Element Group), and a test device group test method for testing such a field effect transistor.

In the production of semiconductor devices, test device groups are often used to monitor the product characteristics or process performance of semiconductor devices.

For example, FIG. 1 exemplarily shows a top view of a prior art test device group field effect transistor. 2A and 2B are respectively a cross-sectional view as seen from the hatching aa of FIG. 1 and a cross-sectional view looking left from the section line bb in FIG. 1, wherein the hatching aa is a test device. The current channel (ie, channel) direction of the group field effect transistor is located in the width direction of the field-effect transistor of the test device group and is perpendicular to the hatching aa.

1, 2A and 2B, it can be seen that the prior art test device group field effect transistor FT includes: a source region S connected to an external test pad Ps through an external lead M; The region D is connected to the external test pad Pd through another external lead M; the gate region G is connected to the external test pad Pg through yet another external lead M.

As shown in FIG. 1, the gate region G is located between the source region S and the drain region D in the channel direction of the test device group field effect transistor FT, and is tested throughout the width direction of the test device group FET FT. The entire width of the device group FET FT.

Here, FIG. 2A exemplarily shows a cross-sectional view as seen from the section line a-a in FIG. As shown in FIG. 2A, the source region S and the drain region D of the test device group field effect transistor FT generally extend from the upper surface of the substrate B into the substrate B, which is covered by the dielectric layer I, and the gate region G is located above the dielectric layer I.

2B exemplarily shows a cross-sectional view seen from the section line b-b in FIG. 1 to the left. In order to highlight the positional relationship between the gate region G and the test device group field effect transistor FT in the width direction of the test device group field effect transistor FT, in FIG. 2B, it is assumed that the dielectric layer I is transparent so that the source can be seen. The pole region S, and each of the outer leads M is omitted. As shown in FIG. 2B, the gate region G penetrates the entire width of the test device group field effect transistor FT in the width direction of the test device group field effect transistor FT. The channel edge E near the test device group field effect transistor FT is also shown in Fig. 2B.

3A and 3B are schematic views respectively showing a schematic diagram of a electric field distribution and a current distribution in the test device group field effect transistor of Fig. 1.

As shown in FIG. 3A, when a voltage is applied between the gate region G and the source region S of the test device group field effect transistor FT, for example, an electric field distribution as indicated by an arrow in the figure is generated, due to the gate region G The three-dimensional shape of the source region S has a certain angular angle, so that the electric field generated at the edge E of the channel close to the field-effect transistor FT of the test device group is stronger.

As shown in FIG. 3B, when there is an on current between the source region S and the drain region D of the test device group field effect transistor FT, for example, a current distribution as indicated by an arrow in the figure is generated. The current flows through a three-dimensional channel of a certain width between the source region S and the drain region D. Moreover, since the electric field generated near the channel edge E of the field-effect transistor FT of the test device group is stronger, the current flowing near the channel edge E of the field-effect transistor FT of the test device group is correspondingly larger.

On the other hand, for process reasons, process defects near the channel edge of the test device group FET are more likely to occur than the middle of the channel, so the reliability and operating characteristics at the edge of the test device group FET are worse. . When the test device group test is performed using the prior art test device group field effect transistor as shown in FIGS. 1 to 3, since the edge between the test device group field effect transistor and the middle reliability and the operation characteristic are not distinguished. Differences, therefore, can not fully understand the product quality of semiconductor devices, which is not conducive to the improvement of the quality of semiconductor device products.

In order to solve one of the above technical problems, the present disclosure provides a test device group field effect transistor comprising: a substrate; a source region located in the substrate; a drain region located in the substrate, and in the a substrate is disposed opposite to the source region in a horizontal direction; a dielectric layer overlying the substrate in a vertical direction of the substrate; and a gate region located in the vertical direction Above the layer, and in the horizontal direction between the source region and the drain region, wherein the gate region is away from the central region of the source region in the horizontal direction The axis of the central region of the drain region.

The gate region includes a first gate region and a second gate region, and the first gate region and the second gate region are respectively disposed on both sides of the axis.

Wherein, the first gate region and the second gate region are connected by the internal circuit of the wafer bypassing the source region.

Wherein, the first gate region and the second gate region are connected by the internal circuit of the wafer bypassing the drain region.

Wherein the first gate region and the second gate region are connected by external leads.

Wherein the source region, the drain region and the gate region are connected to respective external test pads by external leads.

Wherein, the source region, the drain region, the first gate region and the second gate region are connected to respective external test pads by external leads.

The present disclosure also provides a test device group test method for testing a test device group field effect transistor, the test device group field effect transistor, comprising: a substrate; a source region located in the substrate; a drain region, Located in the substrate and disposed opposite to the source region in a horizontal direction of the substrate; a dielectric layer overlying the substrate in a vertical direction of the substrate; and a gate region, Located above the dielectric layer in the vertical direction and between the source region and the drain region in the horizontal direction, wherein the gate region is away from the horizontal direction An axis from a central region of the source region to a central region of the drain region, wherein the test device group testing method includes: in step S100, applying a first voltage to the gate of the field effect transistor Between the polar region and the source region, and stopping applying the first voltage after a predetermined length of time to measure the reliability of the field effect transistor; and in step S200, applying a second voltage to the field effect crystal Between the gate region and the source region, so as to measure the operating characteristics of the field effect transistor.

The first voltage in the step S100 is a desired value of a maximum withstand voltage between the gate region and the source region, and the second voltage in the step S200 is the gate region. And a set of values in the range of operating voltages between the source regions.

The first voltage in the step S100 is 20V, and the second voltage in the step S200 is in an operating voltage range of -10V to +10V between the gate region and the source region. A set of values.

Wherein, in the step S100 and the step S200, the gate region includes a first gate region and a second gate region, and the first gate region and the second gate region are respectively disposed in the Said on both sides of the axis.

Wherein, in the step S100 and in the step S200, the first gate region and the second gate region bypass the source region and are connected by a chip internal circuit.

Wherein, in the step S100 and in the step S200, the first gate region and the second gate region bypass the gate region and are connected by a chip internal circuit.

Wherein, in the step S100 and in the step S200, the first gate region and the second gate region are connected by external leads.

Wherein the source region, the drain region and the gate region are connected to respective external test pads by external leads.

Wherein, the source region, the drain region, the first gate region and the second gate region are connected to respective external test pads by external leads.

By using the test device group field effect transistor of the present disclosure and its test device group test method, since the reliability and operating characteristics at the edge of the test device group field effect transistor can be measured, the product quality of the semiconductor device can be more fully understood. Thereby, it is beneficial to improve the quality of the semiconductor device product.

The present disclosure will be described in detail below with reference to FIGS. 4 through 10, wherein like reference numerals refer to the same or similar devices, elements, materials or structures.

FIG. 4 exemplarily shows a top view of a test device group field effect transistor in accordance with one embodiment of the present disclosure. 5A and 5B are respectively a cross-sectional view as seen from the hatching aa of FIG. 4 and a cross-sectional view looking left from the section line bb in FIG. 4, wherein the hatching aa is a test device The direction of the current channel of the group field effect transistor, the hatching line bb is located in the width direction of the field-effect transistor of the test device group, and is perpendicular to the hatching line aa.

4, FIG. 5A and FIG. 5B, it can be seen that the test device group field effect transistor FT1 of the present disclosure includes: a substrate B; a source region S located in the substrate B; and a drain region D located in the substrate B And is disposed opposite to the source region S in the horizontal direction of the substrate B (ie, the current channel direction of the test device group FET FT1); the dielectric layer I covers the substrate B in the vertical direction of the substrate B, That is, covering the source region S and the drain region D; and the gate region G1, which is located above the dielectric layer I in the vertical direction, and is located in the source region S and the drain in the horizontal direction. Between the regions D, wherein the gate region G1 is away from the axis (ie, the hatching aa) of the central region of the source region S from the central region of the source region S in the horizontal direction, that is, the gate region G1 is offset from the middle of the channel of the test device group field effect transistor FT1 in the width direction of the test device group field effect transistor FT1, and is close to the channel edge E of the test device group field effect transistor FT1.

Wherein, the source region S is connected to the external test pad Ps through the external lead M, the drain region D is connected to the external test pad Pd through the other external lead M, and the gate region G1 is connected to the outside through the other external lead M Test pad Pg.

Here, FIG. 5B exemplarily shows a cross-sectional view seen from the section line b-b in FIG. 4 to the left. In order to highlight the positional relationship between the gate region G1 and the test device group field effect transistor FT1 in the width direction of the test device group field effect transistor FT1, in FIG. 5B, it is assumed that the dielectric layer I is transparent so that the source can be seen. The pole region S, and each of the outer leads M is omitted. As shown in FIG. 5B, the gate region G1 is offset from the middle of the channel of the test device group field effect transistor FT1 in the width direction of the test device group field effect transistor FT1, and is close to the channel edge E of the test device group field effect transistor FT1. .

6A and 6B are diagrams each schematically showing a schematic diagram of a electric field distribution and a current distribution in the test device group field effect transistor of Fig. 4.

As shown in FIG. 6A, when a voltage is applied between the gate region G1 and the source region S of the test device group field effect transistor FT1, for example, an electric field distribution as indicated by an arrow in the figure is generated, and the electric field mainly exists in the vicinity. The edge E of the channel side of the field-effect transistor FT1 of the device group is tested.

As shown in FIG. 6B, when there is an on current between the source region S and the drain region D of the test device group field effect transistor FT1, for example, a current distribution as indicated by an arrow in the figure is generated, and the current mainly exists in the vicinity. The edge E of the channel side of the field-effect transistor FT1 of the device group is tested.

FIG. 7 exemplarily shows a top view of a test device group field effect transistor in accordance with another embodiment of the present disclosure. 8A and 8B are respectively a cross-sectional view as seen from the hatching aa of Fig. 7 and a cross-sectional view looking left from the section line bb in Fig. 7, wherein the hatching aa is a test device The direction of the current channel of the group field effect transistor, the hatching line bb is located in the width direction of the field-effect transistor of the test device group, and is perpendicular to the hatching line aa.

7 , 8A and 8B, it can be seen that the test device group field effect transistor FT2 of the present disclosure as shown in FIGS. 7, 8A and 8B is as shown in FIGS. 4, 5A and 5B. The test device group field effect transistor FT1 of the present disclosure is different in that the gate region of the test device group field effect transistor FT2 of the present disclosure as shown in FIGS. 7, 8A and 8B includes, in addition to the gate region G1. Further, the gate region G2 is further included, and the gate region G1 and the gate region G2 are respectively arranged in the horizontal direction (ie, the direction of the current channel of the test device group field effect transistor FT2) from the central region of the source region S to the drain region D. The two sides of the axis of the central region (ie, the hatching aa), that is, the gate region G1 and the gate region G2 are respectively deviated from the test device group field effect transistor FT2 in the width direction of the test device group field effect transistor FT2. The middle of the channel is near the channel edge E of the test device group FET FT2. As shown in FIG. 7, FIG. 8A and FIG. 8B, the source region S, the drain region D, the gate region G1 and the gate region G2 of the test device group field effect transistor FT2 of the present disclosure are connected to respective ones by external leads. External test pad.

As an embodiment, as shown in FIG. 7, FIG. 8A and FIG. 8B, the gate region G1 and the gate region G2 of the test device group field effect transistor FT2 of the present disclosure may bypass the drain region D through the internal circuit of the wafer ( On-chip wire) connection.

In addition, as an embodiment, the gate region G1 and the gate region G2 of the test device group field effect transistor FT2 of the present disclosure may also be connected through the internal circuit of the wafer bypassing the source region S.

Further, as an embodiment, the gate region G1 and the gate region G2 of the test device group field effect transistor FT2 of the present disclosure may also be connected together by external leads, respectively.

9A and 9B are diagrams each schematically showing a schematic diagram of a electric field distribution and a current distribution in the test device group field effect transistor of Fig. 7.

As shown in FIG. 9A, when a voltage is applied between the gate regions G1, G2 and the source region S of the test device group field effect transistor FT2, for example, an electric field distribution as indicated by an arrow in the figure is generated, and the electric field mainly exists. Near the edge E on both sides of the channel of the test device group FET FT2.

As shown in FIG. 9B, when there is an on current between the source region S and the drain region D of the test device group field effect transistor FT2, for example, a current distribution as indicated by an arrow in the figure is generated, and the current mainly exists in the vicinity. The edge E of both sides of the channel of the field device transistor FT2 is tested.

The test device group test of the present disclosure can be performed using the test device group field effect transistor of the present disclosure as described above.

FIG. 10 exemplarily shows a flowchart of a test device group test method of the present disclosure. As shown in FIG. 10, the test device group test method of the present disclosure is used to test the test device group field effect transistor as shown in FIGS. 4 to 9, including:

Step S100, applying a first voltage between the gate region and the source region of the field effect transistor, and stopping applying the first voltage after a predetermined length of time to measure the reliability of the field effect transistor, such as the voltage withstand capability of the oxide layer. . Where, for example, the first voltage is a desired value of the maximum withstand voltage between the gate region and the source region, such as a DC voltage of 20V.

In step S200, a second voltage is applied between the gate region and the source region of the field effect transistor to measure the operational characteristics of the field effect transistor in normal use, such as the transfer characteristics of the field effect transistor. Where, for example, the second voltage is a set of values in the range of operating voltages between the gate region and the source region, such as a set of DC voltage values from ‒10V to +10V.

In addition, as an embodiment, in the step S100 and the step S200 in the test device group testing method of the present disclosure, the gate region includes a first gate region and a second gate region, and the first gate The pole region and the second gate region are respectively disposed on both sides of the axis.

In addition, as an embodiment, the first gate region and the second gate region bypass the source region in the step S100 and the step S200 in the test device group test method of the present disclosure. The internal circuit of the chip is connected.

In addition, as an embodiment, the first gate region and the second gate region bypass the bucking region in the step S100 and the step S200 in the test device group testing method of the present disclosure. The internal circuit of the chip is connected.

In addition, as an embodiment, the first gate region and the second gate region are connected by external leads in the step S100 and the step S200 in the test device group test method of the present disclosure.

Moreover, as an embodiment, in the test device group test method of the present disclosure, the source region, the drain region, and the gate region are connected to respective external test pads by external leads.

Moreover, as one embodiment, in the test device group testing method of the present disclosure, the source region, the drain region, the first gate region, and the second gate region are connected to respective ones by external leads External test pad.

By using the test device group field effect transistor of the present disclosure and its test device group test method, since the reliability and operating characteristics at the edge of the test device group field effect transistor can be measured, the product quality of the semiconductor device can be more fully understood. Thereby, it is beneficial to improve the quality of the semiconductor device product.

The present disclosure has been described with reference to the exemplary embodiments, and it is understood that the terms used are illustrative and exemplary and not restrictive. Since the present disclosure can be embodied in a variety of forms, it is to be understood that the above-described embodiments are not limited to the details of the foregoing, but are to be construed broadly within the scope of the appended claims All changes and modifications are intended to be covered by the appended claims.

Aa , bb‧‧‧ hatching
B‧‧‧Substrate
I‧‧‧ dielectric layer
D‧‧‧Bungee Area
G, G1, G2‧‧‧ gate area
S‧‧‧ Source Area
FT, FT1, FT2‧‧‧ test device group field effect transistor
E‧‧‧ edge
M‧‧‧External lead
Ps, Pg, Pd‧‧‧ external test pads
S100‧‧‧ steps
S200‧‧‧ steps

Embodiments of the present disclosure will be described below with reference to the accompanying drawings in which: FIG. 1 exemplarily shows a top view of a prior art test device group field effect transistor; FIGS. 2A and 2B exemplarily show A cross-sectional view of the section line aa in FIG. 1 and a cross-sectional view from the section line bb in FIG. 1; FIG. 3A and FIG. 3B respectively illustrate the field effect of the test device in FIG. Schematic diagram of electric field distribution and current distribution in a transistor; FIG. 4 exemplarily shows a top view of a test device group field effect transistor according to an embodiment of the present disclosure; FIGS. 5A and 5B are exemplarily shown from FIG. 4 The cross-sectional view of the hatched line aa in the upward direction and the cross-sectional view seen from the hatching line bb in FIG. 4; FIGS. 6A and 6B respectively illustrate the test device group field effect transistor in FIG. 4 Schematic diagram of electric field distribution and schematic diagram of current distribution; FIG. 7 exemplarily shows a top view of a test device group field effect transistor according to another embodiment of the present disclosure; FIGS. 8A and 8B are exemplarily shown from FIG. Profile Aa looking up the cross-sectional view and a cross-sectional view looking left from the section line bb in FIG. 7; FIGS. 9A and 9B exemplarily showing the electric field distribution in the test device group field effect transistor of FIG. 7, respectively Schematic diagram of schematic and current distribution; and FIG. 10 exemplarily shows a flow chart of a test device group testing method of the present disclosure.

A-a, b-b‧‧‧ hatching

D‧‧‧Bungee Area

G1‧‧‧Bridge area

S‧‧‧ Source Area

FT1‧‧‧ test device group field effect transistor

E‧‧‧ edge

M‧‧‧External lead

Ps, Pg, Pd‧‧‧ external test pads

Claims (10)

A test device group field effect transistor includes: a substrate; a source region located in the substrate; a drain region located in the substrate and opposite to the source region in a horizontal direction of the substrate Arranging; a dielectric layer overlying the substrate in a vertical direction of the substrate; and a gate region located above the dielectric layer in the vertical direction and located in the horizontal direction Between the source region and the drain region, wherein the gate region is away from an axis that is directed from a central region of the source region to a central region of the drain region in the horizontal direction. The test device group field effect transistor of claim 1, wherein the gate region comprises a first gate region and a second gate region, the first gate region and the second gate The pole regions are respectively arranged on both sides of the axis. The test device group field effect transistor of claim 2, wherein the first gate region and the second gate region are connected by the internal circuit of the wafer bypassing the source region. The test device group field effect transistor of claim 2, wherein the first gate region and the second gate region are connected by the internal circuit of the wafer bypassing the drain region. The test device group field effect transistor of claim 2, wherein the first gate region and the second gate region are connected by external leads. The test device group field effect transistor of claim 1, wherein the source region, the drain region, and the gate region are connected to respective external test pads by external leads. A test device group test method for testing a test device group field effect transistor, the test device group field effect transistor comprising: a substrate; a source region located in the substrate; and a drain region located on the substrate And disposed opposite to the source region in a horizontal direction of the substrate; a dielectric layer overlying the substrate in a vertical direction of the substrate; and a gate region in the vertical direction Located above the dielectric layer and between the source region and the drain region in the horizontal direction, wherein the gate region is away from the source in the horizontal direction a central region of the polar region is directed to an axis of a central region of the drain region, wherein the test device group testing method includes: applying a first voltage to the gate region and the source region of the field effect transistor And applying the first voltage to stop measuring the reliability of the field effect transistor after a predetermined length of time; and applying a second voltage to the gate region and the source of the field effect transistor Between districts To measure operating characteristics of the field effect transistor. The test device group test method of claim 7, wherein the first voltage is a desired value of a maximum withstand voltage between the gate region and the source region, and the second voltage Is a set of values in a range of operating voltages between the gate region and the source region. The test device group test method of claim 8, wherein the first voltage is 20 volts, and the second voltage is an operating voltage range between the gate region and the source region Between positive 10 volts and negative 10 volts. The test device group test method of claim 9, wherein the gate region includes a first gate region and a second gate region, the first gate region and the second gate The zones are respectively arranged on both sides of the axis.