CN103916122B - Configurable voltage-controlled oscillator applied to FPGA - Google Patents
Configurable voltage-controlled oscillator applied to FPGA Download PDFInfo
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- CN103916122B CN103916122B CN201410086118.0A CN201410086118A CN103916122B CN 103916122 B CN103916122 B CN 103916122B CN 201410086118 A CN201410086118 A CN 201410086118A CN 103916122 B CN103916122 B CN 103916122B
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- pipe
- grid
- pmos pipe
- drain electrode
- nmos pipe
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Abstract
Provided is a configurable voltage-controlled oscillator applied to an FPGA. A ring oscillator serves as a core part of the voltage-controlled oscillator and is provided with extra digital control signals used for controlling frequency of an oscillation center. The control signals are configured by means of configuration information of the FPGA, center frequency of the voltage-controlled oscillator can be adjusted, and therefore output frequency of the voltage-controlled oscillator can be continuously adjusted within a large range.
Description
Technical field
The present invention relates to a kind of voltage controlled oscillator, wider can configure of particularly a kind of frequency range being applied in fpga
Voltage controlled oscillator.
Background technology
Voltage controlled oscillator (hereinafter referred to as vco) is substantially a kind of agitator, and the frequency controlled voltage processed of concussion controls and can
The difference being vco with ordinary oscillator is adjusted in certain scope.This characteristic makes vco in phaselocked loop (hereinafter referred to as
Pll have a wide range of applications in).
Fig. 1 is typical pll structural representation, and its operation principle is as follows: phase frequency detector comparison reference clock and feedback clock
Frequency and phase relation, charge pump and low pass filter adjust control voltage, adjusts the frequency of oscillation of vco it is ensured that during output
Clock and reference clock have accurate frequency and phase relation.In general, the frequency range that pll can work is subject to the work frequency of vco
Rate scope limits.
It is integrated with substantial amounts of programmable logic resource it is necessary to make in field programmable gate array (hereinafter referred to as fpga)
Ensured clock quality, improved systematic entirety energy with pll.On the other hand, different users may need fpga to be operated in difference
Clock frequency under it is therefore desirable to pll reliably can work in extremely wide frequency range.However, traditional vco only may be used
To be adjusted near some specific frequency, limit the adaptable scope of pll and occasion.The vco master of the present invention
In fpga to be integrated in, using the programmable features of fpga, by the adjustable extent of frequency of oscillation greatly extension so that pll
Reliably can work in extremely wide frequency range.
Content of the invention
The technology solve problem of the present invention is: overcomes the deficiencies in the prior art, there is provided a kind of be applied to joining of fpga
Put voltage controlled oscillator device.
The technical solution of the present invention is:
A kind of configurable voltage controlled oscillator device being applied to fpga, comprising: nmos pipe m1, m2, m3, m4, m11, m12,
M13, m14, m31, m32, m42, pmos pipe m21, m22, m23, m41, electric capacity c43, schmitt inverter g51 and NAND gate g61；
The source ground of nmos pipe m1, m2, m3, m4, grid meets the frequency control voltage v of outside inputcontrol, drain electrode point
Do not connect the source electrode of nmos pipe m11, m12, m13, m14；
The grid of nmos pipe m11, m12, m13, m14 connects configuration signal dcontrol, the grid of drain electrode and pmos pipe m21,
The grid of the drain electrode of pmos pipe m21, the grid of pmos pipe m22 and pmos pipe m23 links together；
The source electrode of pmos pipe m21 connects power supply, and the source electrode of pmos pipe m22 connects power supply, and the source electrode of pmos pipe m23 connects power supply,
The drain electrode of pmos pipe m23 connects the source electrode of pmos pipe m41, the source ground of nmos pipe m31, the grid of nmos pipe m31, nmos pipe
The drain electrode of m31, the drain electrode of pmos pipe m22, the grid of nmos pipe m32 link together；
The source ground of nmos pipe m32, drain electrode connects the source electrode of nmos pipe m42；The grid of pmos pipe m41 and nmos pipe m42
Grid connect, meanwhile, the grid of pmos pipe m41 is also linked together with the outfan of NAND gate g61；
The drain electrode of pmos pipe m41 is connected with the drain electrode of nmos pipe m42, and meanwhile, the drain electrode of pmos pipe m41 is also by electric capacity
C43 is grounded, and the drain electrode of pmos pipe m41 is connected to an outfan of NAND gate g61, pmos also by schmitt inverter g51
The drain electrode of pipe m41 connects the input of schmitt inverter g51；Another input of NAND gate g61 connects enable signal en,
The output of NAND gate g61 had both been the described output clock clk_out that entirely can configure voltage controlled oscillator device.
Frequency control voltage vcontrolWith configuration signal dcontrolCo- controlling electric capacity c43 charge-discharge velocity, when controlling output
The frequency of clock clk_out.
Present invention advantage compared with prior art is:
The present invention utilizes the programmable features of fpga, changes the hardware effort bar of voltage controlled oscillator vco by configuration information
Part is realizing the extension of reference frequency output.Compared with traditional vco, the vco of the present invention has broader frequency-tuning range.
Brief description
Fig. 1 is traditional pll structural representation；
Fig. 2 is the pll structural representation using vco of the present invention；
Fig. 3 is vco circuit theory schematic diagram of the present invention；
Fig. 4 each node voltage waveform diagram when working for vco of the present invention.
Specific embodiment
The vco of the present invention introduces extra control signal, and the configuration information using fpga is controlled, by changing
The extension to realize output frequency range of accommodation for the hardware effort condition of vco.
A kind of pll circuit of the use present invention is as shown in Figure 2.As the vco using Fig. 2, according to the difference of configuration information,
The output frequency of vco can be adjusted respectively in a series of intervals, and the adjustable extent of each minizone is suitable with vco in Fig. 1.Make
Reference frequency output with the pll of vco shown in Fig. 2 is all interval sum totals, and such frequency adjustment interval is by configuration feature
Extended.
Fig. 3 show the circuit of the voltage controlled oscillator designed by the present invention.Including nmos pipe m1, m2, m3, m4,
Nmos pipe m11, m12, m13, m14, pmos pipe m21, m22, m23, nmos pipe m31, m32, pmos pipe m41, nmos pipe m42, electricity
Hold c43, schmitt inverter g51, NAND gate g61.
Annexation is as shown in Figure 3.The source ground of nmos pipe m1, m2, m3, m4, grid connects the frequency control of outside input
Voltage v processedcontrol, drain and connect the source electrode of nmos pipe m11, m12, m13, m14 respectively；
The grid of nmos pipe m11, m12, m13, m14 connects configuration signal dcontrol, the grid of drain electrode and pmos pipe m21,
The grid of the drain electrode of pmos pipe m21, the grid of pmos pipe m22 and pmos pipe m23 links together；
The source electrode of pmos pipe m21 connects power supply, and the source electrode of pmos pipe m22 connects power supply, and the source electrode of pmos pipe m23 connects power supply,
The drain electrode of pmos pipe m23 connects the source electrode of pmos pipe m41, the source ground of nmos pipe m31, the grid of nmos pipe m31, nmos pipe
The drain electrode of m31, the drain electrode of pmos pipe m22, the grid of nmos pipe m32 link together；
The source ground of nmos pipe m32, drain electrode connects the source electrode of nmos pipe m42；The grid of pmos pipe m41 and nmos pipe m42
Grid connect, meanwhile, the grid of pmos pipe m41 is also linked together with the outfan of NAND gate g61；
The drain electrode of pmos pipe m41 is connected with the drain electrode of nmos pipe m42, and meanwhile, the drain electrode of pmos pipe m41 is also by electric capacity
C43 is grounded, and the drain electrode of pmos pipe m41 is connected to an input of NAND gate g61, pmos also by schmitt inverter g51
The drain electrode of pipe m41 connects the input of schmitt inverter g51；Another input of NAND gate g61 connects enable signal en,
The output of NAND gate g61 is the described output clock clk_out that entirely can configure voltage controlled oscillator device.
The output of NAND gate g61 is the output of whole circuit, is designated as clk_out；The drain electrode of note connection pmos pipe m41,
The drain electrode of nmos pipe m42, one end of electric capacity c43, the node of schmitt inverter g51 input are n1；N2 node is Schmidt
Node between the output of phase inverter g51 and an input of NAND gate g61.
The function of pmos pipe m41, nmos pipe m42 is similar to a phase inverter, and its input is pmos pipe m41 and nmos pipe m42
Grid, output is the drain electrode of pmos pipe m41 and nmos pipe m42, and its current drive strength is subject to pmos pipe m23 and nmos pipe m32
Control.When en is 1, the function of NAND gate g61 is equivalent to a phase inverter, anti-with pmos pipe m41 and nmos pipe m42, Schmidt
Phase device g51 constitutes 3 grades of rings and shakes, and realizes the function of agitator.Sequentially there is following event: clk_out by 1 in en after enabling
It is changed into 0, n1 and slowly rises to 1, n2 by 0 being changed into 0, clk_out from 1 and be changed into 1, n1 from 0 slowly dropping to 0, n2 by 0 by 1
It is changed into 1.Constantly repeat this process afterwards, stop oscillation until en is changed into 0 loop, circuit returns to original state.
The speed that n1 voltage changes is determined by electric capacity c43 charge/discharge rates, and electric capacity c43 charging current is managed by pmos
M23 controls, and discharge current size is controlled by nmos pipe m32.Pmos pipe m21, m22, m23 and nmos pipe m31, m32 separately constitute
Current mirror, electric capacity c43 charging and discharging currents are finally by the work of nmos pipe m1, m2, m3, m4 and nmos pipe m11, m12, m13, m14
State determines.dcontrolFor 4 bit wide signals, each determines whether nmso pipe m11, m12, m13, m14 allow electric current to lead to respectively
Cross, determine the frequency separation of vco work；vcontrolIn each nmos pipe in decision nmos pipe m1, m2, m3, m4, electric current is big
Little, so that the output frequency of vco can be continuously adjusted in certain interval.vcontrolWith dcontrolFinal decision electric capacity c43 discharge and recharge
Speed, also just determines the cycle of oscillation of vco.For purposes of illustration only, the present invention takes dcontrolFor 4 bit wide signals, 4 can be controlled
The switching of branch road.dcontrolCan be any bit wide signal, one branch road of every control.
Fig. 4 show dcontrolVco surge frequency range when different, the frequency of oscillation that vco can work is each discrete interval
Summation.Note, for ensureing frequency of oscillation interval continuously, different dcontrolThe frequency of oscillation interval specified must have overlap.
Claims (3)
1. a kind of configurable voltage controlled oscillator being applied to fpga it is characterised in that include: nmos pipe m1, m2, m3, m4, m11,
M12, m13, m14, m31, m32, m42, pmos pipe m21, m22, m23, m41, electric capacity c43, schmitt inverter g51 and NAND gate
g61；
The source ground of nmos pipe m1, m2, m3, m4, grid meets the frequency control voltage v of outside inputcontrol, drain and connect respectively
The source electrode of nmos pipe m11, m12, m13, m14；
The grid of nmos pipe m11, m12, m13, m14 connects configuration signal dcontrol, the grid of drain electrode and pmos pipe m21, pmos pipe
The grid of the drain electrode of m21, the grid of pmos pipe m22 and pmos pipe m23 links together；
The source electrode of pmos pipe m21 connects power supply, and the source electrode of pmos pipe m22 connects power supply, and the source electrode of pmos pipe m23 connects power supply, and pmos manages
The drain electrode of m23 connects the source electrode of pmos pipe m41, the source ground of nmos pipe m31, the grid of nmos pipe m31, the leakage of nmos pipe m31
Pole, the drain electrode of pmos pipe m22, the grid of nmos pipe m32 link together；
The source ground of nmos pipe m32, drain electrode connects the source electrode of nmos pipe m42；The grid of pmos pipe m41 and the grid of nmos pipe m42
Pole connects, and meanwhile, the grid of pmos pipe m41 is also linked together with the outfan of NAND gate g61；
The drain electrode of pmos pipe m41 is connected with the drain electrode of nmos pipe m42, and meanwhile, the drain electrode of pmos pipe m41 connects also by electric capacity c43
Ground, the drain electrode of pmos pipe m41 is connected to an input of NAND gate g61, pmos pipe m41 also by schmitt inverter g51
Drain electrode connect schmitt inverter g51 input；Another input of NAND gate g61 connects and enables signal en, and non-
The output of door g61 as entirely can configure the output clock clk_out of voltage controlled oscillator.
2. a kind of configurable voltage controlled oscillator being applied to fpga according to claim 1 it is characterised in that: bit wide configuration
Signal dcontrolFor 4 bit wide signals, each determines whether nmso pipe m11, m12, m13, m14 allow electric current to pass through respectively；Frequently
Rate control voltage vcontrolDetermine the size of electric current in each nmos pipe in nmos pipe m1, m2, m3, m4.
3. a kind of configurable voltage controlled oscillator being applied to fpga according to claim 2 it is characterised in that: FREQUENCY CONTROL
Voltage vcontrolWith configuration signal dcontrolThe charge-discharge velocity of co- controlling electric capacity c43, controls the frequency of output clock clk_out
Rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410086118.0A CN103916122B (en) | 2014-03-10 | 2014-03-10 | Configurable voltage-controlled oscillator applied to FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410086118.0A CN103916122B (en) | 2014-03-10 | 2014-03-10 | Configurable voltage-controlled oscillator applied to FPGA |
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| CN103916122B true CN103916122B (en) | 2017-02-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602260B1 (en) * | 2007-11-21 | 2009-10-13 | Altera Corporation | Programmable supply voltage regulator for oscillator |
| CN101626238A (en) * | 2008-07-07 | 2010-01-13 | 矽创电子股份有限公司 | Method for controlling voltage-controlled oscillator |
| CN102668382A (en) * | 2009-11-19 | 2012-09-12 | 意法爱立信有限公司 | Generating an oscillator signal having a desired frequency in a continuous frequency range |
| CN103036558A (en) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Voltage-controlled oscillator |
-
2014
- 2014-03-10 CN CN201410086118.0A patent/CN103916122B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602260B1 (en) * | 2007-11-21 | 2009-10-13 | Altera Corporation | Programmable supply voltage regulator for oscillator |
| CN101626238A (en) * | 2008-07-07 | 2010-01-13 | 矽创电子股份有限公司 | Method for controlling voltage-controlled oscillator |
| CN102668382A (en) * | 2009-11-19 | 2012-09-12 | 意法爱立信有限公司 | Generating an oscillator signal having a desired frequency in a continuous frequency range |
| CN103036558A (en) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Voltage-controlled oscillator |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的电压控制LC振荡器的设计研究;万留杰等;《数字技术与应用》;20090930(第9期);第56~57页 * |
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