CN101572540B - Pre-emphasis circuit with configurable emphasis intensity - Google Patents

Pre-emphasis circuit with configurable emphasis intensity Download PDF

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Publication number
CN101572540B
CN101572540B CN2009100436471A CN200910043647A CN101572540B CN 101572540 B CN101572540 B CN 101572540B CN 2009100436471 A CN2009100436471 A CN 2009100436471A CN 200910043647 A CN200910043647 A CN 200910043647A CN 101572540 B CN101572540 B CN 101572540B
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China
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nmos pass
pass transistor
output
circuit
links
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CN2009100436471A
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Chinese (zh)
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CN101572540A (en
Inventor
徐炜遐
王永文
白创
马卓
陈怒兴
李少青
赵振宇
陈吉华
张民选
方粮
肖海鹏
唐李红
石大勇
蒋仁杰
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中国人民解放军国防科学技术大学
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Abstract

The invention discloses a pre-emphasis circuit with configurable emphasis intensity for high-speed I/O interfaces. The pre-emphasis circuit comprises a regulation circuit and an emphasis circuit, wherein the core of the regulation circuit is a delay unit variable in time delay, and the emphasis circuit comprises a fast charge-discharge unit and a four-pipe logic inverter. The regulation circuit receives a full-width random data signal and a feedback low-swing-amplitude output data signal, and generates two paths of pulse control signals adjustable in pulse width according to different input selection signals. When different inputs jump, the emphasis circuit determines the time to fast charge or discharge an output node according to the pulse width of the two paths of control signals generated by the regulation circuit so as to realize pre-emphasis effects different in intensity, and simultaneously limits output swing amplitude through self-feedback so as to realize output signals high in speed and low in swing amplitude. The pre-emphasis circuit has the advantages of simple structure, configurable pre-emphasis intensity and capability of being used for single-end or double-end high-speed I/O interfaces.

Description

Increase the weight of the configurable preemphasis circuit of intensity

Technical field

The present invention is mainly concerned with the design field of transmitter in the high-speed i/o interface, refers in particular to a kind of configurable preemphasis circuit of intensity that increases the weight of.

Background technology

At high-speed i/o interface, USB especially, SATA is in the serial data interfaces such as PCIE, because data transmission rate is very high, so the intersymbol interference that produces in the data transmission procedure is very serious.Therefore in the design process of its transmitter circuit, need carry out preemphasis to the radio-frequency component of signal usually, to reduce the error rate that receives data that causes owing to the decay of transmission course medium-high frequency; And traditional high speed preemphasis circuit complex structure, power consumption is very big, and it is constant to increase the weight of intensity; Can not change with the difference of transmission medium; Therefore cause or increase the weight of insufficient strength, or increase the weight of the excessive and waste power consumption of intensity, this has brought stern challenge for design of preemphasis circuit.

Summary of the invention

The problem that the present invention will solve just is: to the technical problem that prior art exists, it is a kind of simple in structure that the present invention provides, and preemphasis intensity is configurable, can be used for preemphasis circuit single-ended or the both-end high-speed i/o interface.

For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity, it comprises regulating circuit and emphasizer two parts.Wherein the core of regulating circuit is the variable delay cell of time-delay, and emphasizer comprises fast charging and discharging unit and four pipe logic inverters.It is characterized in that: described regulating circuit comprises the first inverter INV1, the second inverter INV2, variable delay cell, NAND gate NAND and the NOR gate NOR of time-delay; Output Data_out links to each other with NOR gate NOR with NAND gate NAND respectively through after inverter INV1 and the variable delay cell of delaying time; Input Data_in links to each other with NAND gate NAND, NOR gate NOR and the second inverter INV2 respectively, and the output of NAND gate NAND, NOR gate NOR and the second inverter INV2 is respectively as the output of regulating circuit; The variable delay cell of wherein delaying time is composed in parallel by a plurality of time-delay subelements; Described time-delay subelement comprises input in, control end en, output out, the 3rd inverter INV3, the 4th PMOS transistor M7, the 5th PMOS transistor M8 and the 4th nmos pass transistor M9, the 5th nmos pass transistor M10; Input in links to each other respectively with the grid of the 5th PMOS transistor M8 and the 4th nmos pass transistor M9; Control end en directly links to each other with the grid of the 5th nmos pass transistor M10; Control end en links to each other with the grid of the 4th PMOS transistor M7 through the 3rd inverter INV3; The drain electrode of the 5th PMOS transistor M8 and the 4th nmos pass transistor M9 links to each other as the output out of time-delay subelement, and the source electrode of the 5th PMOS transistor M8 links to each other with the drain electrode of the 4th PMOS transistor M7, and the source electrode of the 4th PMOS transistor M7 links to each other with power supply; The source electrode of the 4th nmos pass transistor M9 links to each other the source ground of the 5th nmos pass transistor M10 with the drain electrode of the 5th nmos pass transistor M10.

Described fast charging and discharging unit comprises a PMOS transistor M1 and the first nmos pass transistor M2; Respectively output is discharged and recharged fast; The drain electrode of the one PMOS transistor M1 and the first nmos pass transistor M2 links to each other and is attached to the output Data_out of preemphasis; The source electrode of the one PMOS transistor M1 links to each other with power supply; The source ground of the first nmos pass transistor M2, the output of the NAND gate NAND in the grid people having the same aspiration and interest economize on electricity road of a PMOS transistor M1 links to each other, and the output of the NOR gate NOR in the grid people having the same aspiration and interest economize on electricity road of the first nmos pass transistor M2 links to each other.

Described four pipe logic inverters comprise the 2nd PMOS transistor M3, the 3rd PMOS transistor M4 and the second nmos pass transistor M5, the 3rd nmos pass transistor M6; The drain electrode of the 3rd PMOS transistor M4 and the second nmos pass transistor M5 links to each other and is attached to the grid of the 2nd PMOS transistor M3 and the 3rd nmos pass transistor M6; Output Data_out as preemphasis; The drain electrode of the 2nd PMOS transistor M3 links to each other with the source electrode of the 3rd PMOS transistor M4; The source electrode of the 2nd PMOS transistor M3 links to each other with power supply, and the drain electrode of the 3rd nmos pass transistor M6 links to each other the source ground of the 3rd nmos pass transistor M6 with the source electrode of the second nmos pass transistor M5; The grid of the 3rd PMOS transistor M4 and the second nmos pass transistor M5 links the input as four pipe logic inverters, and is continuous with the output of the second inverter INV2.

Compared with prior art, advantage of the present invention just is:

1, circuit structure is simple.Compare with traditional emphasizer level with tail current source, the present invention realizes that the core component of preemphasis only comprises six metal-oxide-semiconductors, the bias-voltage generating circuit of the tail current source steady operation of also need not giving security.

2, increase the weight of the adjustability of intensity.Increase the weight of the constant emphasizer of intensity with tradition and compare, the present invention is based on the pulse signal that variable delay unit produces distinct pulse widths, control discharging and recharging the time of fast charging and discharging unit, realize the effect that increases the weight of the varying strength of output signal.

3, reduce circuit power consumption.Compare with traditional emphasizer, the present invention is not owing to there is tail current source, thus the work that the big electric current that need not continue to provide stable keeps preemphasis circuit.

4, be applicable to the transmission of high data rate.Compare with traditional preemphasis circuit, the present invention realizes the output of the low amplitude of oscillation through the self feed back effect, thereby satisfies the requirement that high data rate sends.

5, has better process transplanting performance.Emphasizer such as the Fig. 1 range upon range of with traditional multistage metal-oxide-semiconductor compare, and the present invention has reduced the range upon range of progression of the metal-oxide-semiconductor from the power supply to ground, thereby have reduced the consumption to voltage margin, more help under low supply voltage, realizing.

Description of drawings

Fig. 1 is traditional range upon range of emphasizer sketch map of multistage metal-oxide-semiconductor;

Fig. 2 is a frame structure sketch map of the present invention;

Fig. 3 is the circuit theory sketch map of time-delay subelement among the present invention;

Fig. 4 is the structural representation of the variable delay cell of time-delay among the present invention;

Fig. 5 is a circuit theory sketch map of the present invention.

Embodiment

Below will combine accompanying drawing and specific embodiment that the present invention is explained further details.

Like Fig. 2, Fig. 3, Fig. 4 and shown in Figure 5, a kind of be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity, it comprises regulating circuit and emphasizer two parts.Wherein the core of regulating circuit is the variable delay cell of time-delay, and emphasizer comprises fast charging and discharging unit and four pipe logic inverters.It is characterized in that: described regulating circuit comprises the first inverter INV1, the second inverter INV2, variable delay cell, NAND gate NAND and the NOR gate NOR of time-delay; Output Data_out links to each other with NOR gate NOR with NAND gate NAND respectively through after inverter INV1 and the variable delay cell of delaying time; Input Data_in links to each other with NAND gate NAND, NOR gate NOR and the second inverter INV2 respectively, and the output of NAND gate NAND, NOR gate NOR and the second inverter INV2 is respectively as the output of regulating circuit; The variable delay cell of wherein delaying time is composed in parallel by a plurality of time-delay subelements; Described time-delay subelement comprises input in, control end en, output out, the 3rd inverter INV3, the 4th PMOS transistor M7, the 5th PMOS transistor M8 and the 4th nmos pass transistor M9, the 5th nmos pass transistor M10; Input in links to each other respectively with the grid of the 5th PMOS transistor M8 and the 4th nmos pass transistor M9; Control end en directly links to each other with the grid of the 5th nmos pass transistor M10; Control end en links to each other with the grid of the 4th PMOS transistor M7 through the 3rd inverter INV3; The drain electrode of the 5th PMOS transistor M8 and the 4th nmos pass transistor M9 links to each other as the output out of time-delay subelement, and the source electrode of the 5th PMOS transistor M8 links to each other with the drain electrode of the 4th PMOS transistor M7, and the source electrode of the 4th PMOS transistor M7 links to each other with power supply; The source electrode of the 4th nmos pass transistor M9 links to each other the source ground of the 5th nmos pass transistor M10 with the drain electrode of the 5th nmos pass transistor M10.Described fast charging and discharging unit comprises a PMOS transistor M1 and the first nmos pass transistor M2; Respectively output is discharged and recharged fast; The drain electrode of the one PMOS transistor M1 and the first nmos pass transistor M2 links to each other and is attached to the output Data_out of preemphasis; The source electrode of the one PMOS transistor M1 links to each other with power supply; The source ground of the first nmos pass transistor M2, the output of the NAND gate NAND in the grid people having the same aspiration and interest economize on electricity road of a PMOS transistor M1 links to each other, and the output of the NOR gate NOR in the grid people having the same aspiration and interest economize on electricity road of the first nmos pass transistor M2 links to each other.Described four pipe logic inverters comprise the 2nd PMOS transistor M3, the 3rd PMOS transistor M4 and the second nmos pass transistor M5, the 3rd nmos pass transistor M6; The drain electrode of the 3rd PMOS transistor M4 and the second nmos pass transistor M5 links to each other and is attached to the grid of the 2nd PMOS transistor M3 and the 3rd nmos pass transistor M6; Output Data_out as preemphasis; The drain electrode of the 2nd PMOS transistor M3 links to each other with the source electrode of the 3rd PMOS transistor M4; The source electrode of the 2nd PMOS transistor M3 links to each other with power supply, and the drain electrode of the 3rd nmos pass transistor M6 links to each other the source ground of the 3rd nmos pass transistor M6 with the source electrode of the second nmos pass transistor M5; The grid of the 3rd PMOS transistor M4 and the second nmos pass transistor M5 links the input as four pipe logic inverters, and is continuous with the output of the second inverter INV2.

The present invention realizes that the core component of preemphasis is an emphasizer; It comprises fast charging and discharging unit and four pipe logic inverter two parts, and the 2nd PMOS transistor M3 of four pipe logic inverters and the grid of the 3rd nmos pass transistor M6 link to each other with increasing the weight of output, are equivalent to a feedback effect; Thereby the amplitude of oscillation of restriction output; Realize the signal output of the at a high speed low amplitude of oscillation, the charging or the metal-oxide-semiconductor that discharges are opened fast in the fast charging and discharging unit when different input saltus steps; Output node is carried out quick charge or discharge, thereby realize preemphasis effect output signal hopping edge.And realize that increasing the weight of the configurable core component of intensity is regulating circuit; The selection signal different according to the outside; The delay cell of delaying time variable produces the time delayed signal with respect to the different time of delays of input; And then the pulse signal of generation distinct pulse widths, control discharging and recharging the time of fast charging and discharging unit, realize the effect that increases the weight of of varying strength.

When input produce one jump down along the time, NAND gate output perseverance be high level, makes PMOS pipe M1 maintenance shutoff; Pulse signal of NOR gate output, in the time period of high level pulse, NMOS pipe M2 opens; The emphasizer output node is discharged fast, realize the effect that increases the weight of of jumping down, in the low level time section; The one NMOS pipe M2 turn-offs, and the input of afterbody four pipe logic inverters is slowly risen, so make the 2nd PMOS pipe M3 and the 3rd PMOS manage the conducting of the M4 degree of depth; Charging current is greater than discharging current, and the result charges to output node, thereby realizes the signal output of the low amplitude of oscillation.

When input produce one go up jump along the time, NOR gate output perseverance be low level, makes NMOS pipe M2 maintenance shutoff; Pulse signal of NAND gate output, in the time period of low level pulse, PMOS pipe M1 opens; The emphasizer output node is charged fast, and that jumps in the realization increases the weight of effect, in the high level time section; The one PMOS pipe M1 turn-offs, and the input of afterbody four pipe logic inverters slowly descends, so make the 2nd NMOS pipe M5 and the 3rd NMOS manage the conducting of the M6 degree of depth; Discharging current is greater than charging current, and the result discharges to output node, thereby realizes the signal output of the low amplitude of oscillation.

Claims (5)

  1. One kind be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity; It is characterized in that: comprise that two parts are regulating circuit part and emphasizer part; Wherein regulating circuit partly comprises the delay cell that time-delay is variable; Emphasizer partly comprises fast charging and discharging unit and four pipe logic inverters; Regulating circuit partly receives the random data signals Data_in of a full width and the outputting data signals Data_out of a feedback, according to the different selection signal of input, produces the adjustable pulse control signal of two-way pulse duration; Wherein said outputting data signals Data_out is the signal at output node place, and said output node is the output of emphasizer part; The emphasizer part is when the different saltus step of said random data signals Data_in; Pulse duration according to the adjustable pulse control signal of said two-way pulse duration; The time of fast charging and discharging is carried out in decision to said output node; Thereby realize the preemphasis effect of varying strength, limit the amplitude of oscillation of said outputting data signals Data_out simultaneously through self feed back, obtain the said outputting data signals Data_out of the at a high speed low amplitude of oscillation.
  2. 2. according to claim 1 be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity; It is characterized in that: said regulating circuit partly comprises first inverter, second inverter, variable delay cell, NAND gate and the NOR gate of said time-delay; The outputting data signals Data_out at said output node place is connected respectively to an input of said NAND gate and an input of said NOR gate after through the variable delay cell of first inverter and said time-delay, and said random data signals Data_in is connected respectively to another input and second inverter of another input of said NAND gate, said NOR gate; The output of said NAND gate, said NOR gate and said second inverter is respectively as the output partly of said regulating circuit; Said regulating circuit part produces the adjustable pulse control signal of said two-way pulse duration according to said different selection signal.
  3. 3. according to claim 2 be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity; It is characterized in that: said fast charging and discharging unit is when the different saltus step of said random data signals Data_in; Pulse duration according to the adjustable pulse control signal of said two-way pulse duration; Decision is carried out the time of fast charging and discharging to said output node, thereby realizes the preemphasis effect of varying strength; The input reception one of four pipe logic inverters and the signal of said random data signals Data_in anti-phase; Limit the amplitude of oscillation of said outputting data signals Data_out through self feed back; Realize the said outputting data signals Data_out of the at a high speed low amplitude of oscillation, the signal of wherein said anti-phase is obtained through said second inverter by said random data signals Data_in.
  4. 4. according to claim 3 be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity; It is characterized in that: said fast charging and discharging unit comprises a PMOS transistor and first nmos pass transistor; The fast charging and discharging unit discharges and recharges said output node fast; The drain electrode of the one PMOS transistor drain and first nmos pass transistor links to each other and is connected to said output node, and the transistorized source electrode of a PMOS links to each other with power supply, the source ground of first nmos pass transistor; The transistorized grid of the one PMOS links to each other with the output of said NAND gate, and the grid of first nmos pass transistor links to each other with the output of said NOR gate.
  5. 5. according to claim 4 be used for high-speed i/o interface increase the weight of the configurable preemphasis circuit of intensity, it is characterized in that: said four pipe logic inverters comprise the 2nd PMOS transistor, the 3rd PMOS transistor, second nmos pass transistor and the 3rd nmos pass transistor; Wherein, The grid of the drain electrode of the 3rd PMOS transistor drain, second nmos pass transistor, the transistorized grid of the 2nd PMOS, the 3rd nmos pass transistor all is connected to said output node; The 2nd PMOS transistor drain links to each other with the transistorized source electrode of the 3rd PMOS; The transistorized source electrode of the 2nd PMOS links to each other with said power supply, and the drain electrode of the 3rd nmos pass transistor links to each other with the source electrode of second nmos pass transistor, the source ground of the 3rd nmos pass transistor; The grid of the transistorized grid of the 3rd PMOS and second nmos pass transistor link to each other and as four the pipe logic inverters input, said four the pipe logic inverters input link to each other with the output of second inverter.
CN2009100436471A 2009-06-09 2009-06-09 Pre-emphasis circuit with configurable emphasis intensity CN101572540B (en)

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Publication number Priority date Publication date Assignee Title
CN102164103B (en) * 2010-12-15 2013-12-25 烽火通信科技股份有限公司 Programmable differential continuous-time pre-emphasis driver
CN103368553B (en) * 2012-04-10 2018-04-27 深圳市中兴微电子技术有限公司 Half rate preemphasis circuit
CN102624374B (en) * 2012-04-18 2014-12-03 烽火通信科技股份有限公司 Current-mode logic (CML) level driving circuit with pre-emphasis function

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CN101295976A (en) * 2007-04-27 2008-10-29 扬粹半导体(上海)有限公司 Transmitter and method for high-speed I/O mixed pre-weighing equalization

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US7265587B1 (en) * 2005-07-26 2007-09-04 Altera Corporation LVDS output buffer pre-emphasis methods and apparatus
CN101295976A (en) * 2007-04-27 2008-10-29 扬粹半导体(上海)有限公司 Transmitter and method for high-speed I/O mixed pre-weighing equalization

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