CN103905039B - A kind of linear wide scope digital controlled oscillator being applied to FPGA - Google Patents
A kind of linear wide scope digital controlled oscillator being applied to FPGA Download PDFInfo
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- CN103905039B CN103905039B CN201410100574.6A CN201410100574A CN103905039B CN 103905039 B CN103905039 B CN 103905039B CN 201410100574 A CN201410100574 A CN 201410100574A CN 103905039 B CN103905039 B CN 103905039B
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Abstract
A kind of linear wide scope digital controlled oscillator being applied to FPGA, the core of this digital controlled oscillator is a ring oscillator, control word can be selected to select oscillator output frequencies by frequency.Utilize the configurable feature of FPGA, the output center frequency of digital controlled oscillator can be changed neatly so that the output frequency of this digital controlled oscillator can continuously linear ground regulation in a wide range.
Description
Technical field
The present invention relates to a kind of digital controlled oscillator, a kind of frequency range being applied in FPGA is wider
Digital controlled oscillator.
Background technology
Digital controlled oscillator (hereinafter referred to as DCO) is substantially a kind of agitator, and frequency of oscillation is selected by frequency
The control of control word, using digital control code to be controlled output frequency is DCO and other agitator
The main distinction.This characteristic makes DCO have a wide range of applications in digital frequency synthesizer.
One typical ring oscillator generally uses the phase inverter that odd number is identical, Fig. 1 be one typical
Three-level annular oscillator structure schematic diagram, the phase inverter in agitator is used for providing fixing time delay, agitator
Frequency of oscillation be given by formula (1).
In formula, TdReferring to the time delay that each inverter module provides, N represents that ring oscillator includes phase inverter
The number of unit.Therefore, by changing number N or the size of every grade of phase inverter offer time delay of phase inverter
TdThe frequency of oscillation of agitator can be changed.The time delay Td of each delay unit can be obtained by formula (2),
In formula, CLBeing the load capacitance of phase inverter, Δ V is the output voltage swing of phase inverter, and Id refers to bear
Carry the driving electric current of electric capacity.From formula (2) it is found that before number N not changing delay unit
Put, by changing load capacitance CLOr drive the size of electric current, it is possible to achieve to oscillator output frequencies
The control of size.Load capacitance CLExpression formula can be obtained by formula (3).
In formula, g, s, d, b represent the grid of metal-oxide-semiconductor, source, leakage and substrate, C respectivelywRepresent line capacitance.
Under normal circumstances, phase inverter output load capacitance can by MIM capacitor, or metal-oxide-semiconductor electric capacity realize,
But, along with the development of semiconductor process technique, the company under the process conditions of current submicron, between device
The proportion that line capacitance accounts for is increasing, so change the side of oscillator frequency by changing load capacitance size
Method is increasingly difficult to realize.Therefore the present invention is by controlling to drive the driving electric current I of load capacitancedSize, come
Realize digital controlled oscillator DCO.Which ensures that the DCO of the present invention has the fabulous linearity.
Field programmable gate array (hereinafter referred to as FPGA) is integrated with substantial amounts of programmable logic resource,
Using DCO can be that system provides high-quality clock.On the other hand, different users may need
FPGA is operated under different clock frequencies, it is therefore desirable to DCO can be in the widest frequency range
Reliably work.But, traditional agitator may only be adjusted near some specific frequency,
Limit the adaptable scope of frequency synthesizer and occasion.
Summary of the invention
The technology of the present invention solves problem: overcome the deficiencies in the prior art, it is provided that one is applied to FPGA
In the wider digital controlled oscillator of frequency range, DCO is mainly integrated in FPGA, utilizes FPGA's
Programmable features, can modify to the frequency selection control word of DCO neatly, thus greatly expand
Open up the reference frequency output of agitator so that DCO reliably can work in the widest frequency range.
The technical solution of the present invention is:
A kind of linear wide scope digital controlled oscillator circuit being applied to FPGA, including buffer, multi-path choice
Device, SRAM and at least two tristate inverter chain；
The structure of each tristate inverter chain is the most identical, including the end to end tristate inverter of at least five；
The output of last tristate inverter is the output of tristate inverter chain belonging to it, each tristate inverter
The output of chain is both connected to together, and delivers to the input of MUX；
In n-th tristate inverter chain, the first Enable Pin of each tristate inverter is both connected to together, by
N-th control of the control signal of outside input, the second Enable Pin of each tristate inverter is both connected to one
Rising, by n-th control of the inverted signal of the control signal of described outside input, n more than or equal to 1 is just
Integer, i.e. n=1,2,3,4,5 ...；
The tri-state that each tristate inverter in tristate inverter chain is all corresponding with other tristate inverter chains
Phase inverter is parallel with one another；In tristate inverter chain, the output of m-th tristate inverter is connected to MUX
Input, m=3+i, i are the even number more than or equal to 0, i.e. i=0,2,4,6,8 ...
SRAM is connected to the selection of MUX and controls end, for selecting the length of tristate inverter chain,
The output feedback link of MUX, to the input of tristate inverter chain, makes tristate inverter chain constitute annular
Agitator, meanwhile, the output of MUX exports after buffer buffering shaping, is described number
The output of controlled oscillator circuit.
The quantity of described tristate inverter chain is identical with the figure place of external input control signal.
Described tristate inverter includes PMOS M1, M3, M4, NMOS tube M2, M5 and M6；
The source electrode of PMOS M3 is connected with the drain electrode of NMOS tube M5 the input as tristate inverter,
PMOS M1, the source electrode of M4 connect power supply, NMOS tube M2, the source ground of M6, PMOS
The grid of M4 and the grid of NMOS tube M5 are connected to external input control signal, PMOS M3
The grid of grid and NMOS tube M6 is connected to the inverted signal of external input control signal；
The drain electrode of PMOS M3, the drain electrode of PMOS M4, the grid of PMOS M1 are connected to
Together, the source electrode of NMOS tube M5, the drain electrode of NMOS tube M6, the grid of NMOS tube M2 connect
Together, the drain electrode of PMOS M1 is connected as described tristate inverter with the drain electrode of NMOS tube M2
Output.
Present invention advantage compared with prior art is:
The DCO of the present invention is all-digitized demodulator agitator, utilizes the programmable features of FPGA, Ke Yiling
The mid frequency of agitator is set alively, and can by frequency selection control word D [7:0] changing DCO
The rate-adaptive pacemaker wanted with acquisition.Compared with traditional agitator, the DCO of the present invention has broader frequency
Rate range of accommodation and the more preferable linearity.
Accompanying drawing explanation
Fig. 1 is traditional ring oscillator structure schematic diagram；
Fig. 2 is DCO circuit theory schematic diagram of the present invention；
Fig. 3 is the tri-state inverter circuits principle schematic of the present invention；
Fig. 4 is the output frequency schematic diagram with frequency selection control word relation of DCO of the present invention.
Detailed description of the invention
The DCO of the present invention introduces special frequency and selects control signal, utilizes the configuration code of FPGA to enter
Row controls, and is realized the output of different frequency by the control word changing DCO.
A kind of linear wide scope digital controlled oscillator circuit such as Fig. 2 institute being applied to FPGA that the present invention provides
Show.When using the DCO of Fig. 2, according to the difference of configuration register information, the output frequency of DCO can
To regulate in a series of intervals respectively, reference frequency output is the summation in all intervals, shaking of final realization
Swing device to regulate a wider interval range internal linear.
As in figure 2 it is shown, DCO of the present invention includes buffer 210, MUX 220, SRAM230
With at least two tristate inverter chain, the first tristate inverter chain include tristate inverter 201,202,203,
204,205 ... the second tristate inverter chain includes tristate inverter 211,212,213,214,215 ...；
The structure of each tristate inverter chain is the most identical, including the end to end tristate inverter of at least five,
Such as, the output of tristate inverter 201 is connected to the input of tristate inverter 202, tristate inverter 202
Output be re-used as the input of tristate inverter 203, the rest may be inferred, tristate inverter 201,202,203,
204,205,206 and 207 successively join end to end composition the first tristate inverter chain, in like manner, tri-state is anti-phase
The output of device 211 is as the input of tristate inverter 212, and the output of tristate inverter 212 is connected to three
The input of state phase inverter 213, so, tristate inverter 211,212,213,214,215,216
The composition that joins end to end successively with 217 second tristate inverter chain；
In n-th tristate inverter chain, the first Enable Pin of each tristate inverter is both connected to together, by
N-th control of the control signal of outside input, the second Enable Pin of each tristate inverter is both connected to one
Rising, by n-th control of the inverted signal of the control signal of described outside input, n more than or equal to 1 is just
Integer, i.e. n=1,2,3,4,5 ... such as, tristate inverter 201,202,203,204,205,206
With 207 the first Enable Pin be connected with control signal D0, tristate inverter 201,202,203,204,
205,206 with 207 the second Enable Pin be connected with control signal Db0；
The tri-state that each tristate inverter in tristate inverter chain is all corresponding with other tristate inverter chains
Phase inverter is parallel with one another, i.e. tristate inverter 201 with 211 input be connected, tristate inverter 201 He
The output of 211 be connected, in like manner, tristate inverter 202 with 212 input be connected, tristate inverter 202
With 212 output be connected, the rest may be inferred；
The output of last tristate inverter of each tristate inverter chain is tristate inverter chain belonging to it
Output, in tristate inverter chain, the output of m-th tristate inverter is connected to the defeated of MUX 220
Entering end, m=3+i, i are the even number more than or equal to 0, i.e. i=0,2,4,6,8 ... such as, tristate inverter 203,
The output of 205 and 207 is connected to the data input pin of MUX 220；
SRAM230 is connected to the selection of MUX and controls end, for selecting the length of tristate inverter chain
Degree, the figure place of SRAM230 is determined by the length of tristate inverter chain, and the output of MUX 220 is anti-
Feedback is connected to the input of tristate inverter chain, makes tristate inverter chain constitute ring oscillator, meanwhile, multichannel
The output of selector 220 exports after buffer 210 buffers shaping, is described digital controlled oscillator electricity
The output OUT on road；
The quantity of described tristate inverter chain is identical with the figure place of external input control signal；
Described tristate inverter all uses the tristate inverter structure shown in Fig. 3, in same chain of inverters
Tristate inverter 201,202,203,204,205 ... width, length (W, L) equally, different chains
The varying in size of tristate inverter, such as, tristate inverter is gradually increased from the size of 201 to 271,
Thus ensure that the output frequency of digital controlled oscillator selects control word to have linear relationship with frequency.
As it is shown on figure 3, tristate inverter includes PMOS M1, M3, M4, NMOS tube M2,
M5 and M6；
The source electrode of PMOS M3 is connected with the drain electrode of NMOS tube M5 the input as tristate inverter,
Being designated as CLK_IN, PMOS M1, the source electrode of M4 connect power supply, NMOS tube M2, the source electrode of M6
Ground connection, the grid of PMOS M4 and the grid of NMOS tube M5 are connected to external input control signal D,
The grid of PMOS M3 and the grid of NMOS tube M6 are connected to the inverted signal of external input control signal
Db；
The drain electrode of PMOS M3, the drain electrode of PMOS M4, the grid of PMOS M1 are connected to
Together, being designated as node is N1, the source electrode of NMOS tube M5, the drain electrode of NMOS tube M6, NMOS
The grid of pipe M2 links together, and being designated as node is N2, the drain electrode of PMOS M1 and NMOS tube
The connected output as described tristate inverter of drain electrode of M2, is designated as CLK_OUT；
A PMOS M3 phase inverter similar with the function of NMOS tube M2, PMOS M3 and
The function of NMOS tube M5 is similar to a transmission gate, and control signal D and Db control clock signal from defeated
Entering the propagation to output, if D=1, Db=0, input clock signal can pass through tristate inverter；Otherwise,
When D=0, Db=1, PMOS M1 and NMOS tube M2 are all turned off, thus disconnect output
CLK_OUT and the connection of input；
Different from traditional tristate inverter, the introducing of PMOS M4 and NMOS tube M6 ensure that
Under the conditions of D=0, Db=1, the grid of PMOS M1 is connected with Vdd, the grid of NMOS tube M2
It is connected with Gnd, so can ensure that PMOS M1 and NMOS tube M2 can complete switch off, anti-
Only at D=0, during Db=1, node N1 and node N2 floating, it is impossible to complete switch off PMOS M1
With NMOS tube M2 so that outfan CLK_OUT also can be charged or discharged.
As shown in Figure 4, exporting clock frequency for DCO of the present invention when working selects control word to close with frequency
The schematic diagram of system, the output of DCO and frequency select control word to be approximately linear relationship.Select in frequency
At control word D [7:0]=128, the output frequency of DCO is fo。
Claims (2)
1. the linear wide scope digital controlled oscillator circuit being applied to FPGA, it is characterised in that: include
Buffer, MUX, SRAM and at least two tristate inverter chain；
The structure of each tristate inverter chain is the most identical, including the end to end tristate inverter of at least five；
The output of last tristate inverter is the output of tristate inverter chain belonging to it, each tristate inverter
The output of chain is both connected to together, and delivers to the input of MUX；
In q-th tristate inverter chain, the first Enable Pin of each tristate inverter is both connected to together, by
N-th control of the control signal of outside input, the second Enable Pin of each tristate inverter is both connected to one
Rising, by n-th control of the inverted signal of the control signal of described outside input, n more than or equal to 1 is just
Integer, i.e. n=1,2,3,4,5 ...；Q is the number of tristate inverter chain；
The tri-state that each tristate inverter in tristate inverter chain is all corresponding with other tristate inverter chains
Phase inverter is parallel with one another；In tristate inverter chain, the output of m-th tristate inverter is connected to MUX
Input, m=3+i, i are the even number more than or equal to 0, i.e. i=0,2,4,6,8 ...
SRAM is connected to the selection of MUX and controls end, for selecting the length of tristate inverter chain,
The output feedback link of MUX, to the input of tristate inverter chain, makes tristate inverter chain constitute annular
Agitator, meanwhile, the output of MUX exports after buffer buffering shaping, is described number
The output of controlled oscillator circuit；
Described tristate inverter includes PMOS M1, M3, M4, NMOS tube M2, M5 and M6；
The source electrode of PMOS M3 is connected with the drain electrode of NMOS tube M5 the input as tristate inverter,
PMOS M1, the source electrode of M4 connect power supply, NMOS tube M2, the source ground of M6, PMOS
The grid of M4 and the grid of NMOS tube M5 are connected to external input control signal, PMOS M3
The grid of grid and NMOS tube M6 is connected to the inverted signal of external input control signal；
The drain electrode of PMOS M3, the drain electrode of PMOS M4, the grid of PMOS M1 are connected to
Together, the source electrode of NMOS tube M5, the drain electrode of NMOS tube M6, the grid of NMOS tube M2 connect
Together, the drain electrode of PMOS M1 is connected as described tristate inverter with the drain electrode of NMOS tube M2
Output.
A kind of linear wide scope digital controlled oscillator electricity being applied to FPGA the most according to claim 1
Road, it is characterised in that: the quantity of described tristate inverter chain is identical with the figure place of external input control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410100574.6A CN103905039B (en) | 2014-03-18 | 2014-03-18 | A kind of linear wide scope digital controlled oscillator being applied to FPGA |
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| CN201410100574.6A CN103905039B (en) | 2014-03-18 | 2014-03-18 | A kind of linear wide scope digital controlled oscillator being applied to FPGA |
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| CN103905039B true CN103905039B (en) | 2017-01-04 |
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| CN111953343B (en) * | 2020-09-07 | 2023-05-30 | 北京中科芯蕊科技有限公司 | Digital control subthreshold ring oscillator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3115640A1 (en) * | 1981-04-18 | 1982-11-11 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Integrated dynamic shift memory comprising insulated-gate field-effect transistors |
| CN1405650A (en) * | 2001-09-19 | 2003-03-26 | 尔必达存储器株式会社 | Interpolating circuit and DLL circuit and semi-conductor integrated cirucit |
| CN101183852A (en) * | 2006-11-13 | 2008-05-21 | 财团法人工业技术研究院 | High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same |
| CN203104407U (en) * | 2011-09-28 | 2013-07-31 | 英特尔公司 | Device and system for controlling temperature drift and supply voltage drift in digital phase-locked loop (DPLL) |
-
2014
- 2014-03-18 CN CN201410100574.6A patent/CN103905039B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3115640A1 (en) * | 1981-04-18 | 1982-11-11 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Integrated dynamic shift memory comprising insulated-gate field-effect transistors |
| CN1405650A (en) * | 2001-09-19 | 2003-03-26 | 尔必达存储器株式会社 | Interpolating circuit and DLL circuit and semi-conductor integrated cirucit |
| CN101183852A (en) * | 2006-11-13 | 2008-05-21 | 财团法人工业技术研究院 | High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same |
| CN203104407U (en) * | 2011-09-28 | 2013-07-31 | 英特尔公司 | Device and system for controlling temperature drift and supply voltage drift in digital phase-locked loop (DPLL) |
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