CN103854989A - 具有相同鳍型场效晶体管栅极高度的结构及其形成方法 - Google Patents

具有相同鳍型场效晶体管栅极高度的结构及其形成方法 Download PDF

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CN103854989A
CN103854989A CN201310624809.7A CN201310624809A CN103854989A CN 103854989 A CN103854989 A CN 103854989A CN 201310624809 A CN201310624809 A CN 201310624809A CN 103854989 A CN103854989 A CN 103854989A
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CN103854989B (zh
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B.S.哈兰
S.梅塔
S.波诺思
R.拉马钱德兰
S.施米茨
T.E.斯坦达尔特
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明提供了一种用于制造多个鳍型FET半导体器件的方法，该方法包括：提供由半导体基板蚀刻成并由氧化物层和氮化物层覆盖的多个鳍，氧化物层设置在多个鳍和氮化物层之间；去除多个鳍的一部分以形成开口；以及在开口的侧壁上形成电介质间隔壁。该方法还可包括用填充材料填充开口，其中填充材料的顶表面与氮化物层的顶表面实质上齐平；去除氮化物层以在多个鳍和填充材料之间形成间隙，其中填充材料具有在间隙之上延伸的凹形几何形状；以及去除凹形几何形状且使多个鳍和填充材料之间的间隙加大。

Description

具有相同鳍型场效晶体管栅极高度的结构及其形成方法
技术领域
本发明总体上涉及集成电路，特别是栅极高度相同的多个鳍型FET半导体器件。
背景技术
对于优化性能来讲，希望半导体器件结构的尺寸一致性希望用于优化的功能性。尺寸的变化可能影响半导体器件的制造且最终影响到半导体器件的可靠性，例如，鳍型FET器件（finFET devices）。通常用于制造鳍型FET器件的工艺流程可能产生栅极高度上的很大变化。由于芯片上的图案密度的变化，栅极高度可在单一芯片内变化很大。高图案密度的区域可包括多个鳍，而低图案密度的区域可包括一个或两个鳍。通常，低图案密度的区域中测得的栅极高度可能低于高图案密度的区域中测得的栅极高度。
通常，先栅极工艺流程可包括在基板中形成鳍，沉积包括高k电介质和一个或多个栅极金属的栅极堆叠，并且最终蚀刻最后的栅极结构。作为选择，置换栅极（RG）工艺流程可包括利用虚设栅极堆叠。虚设栅极堆叠的栅极堆叠的厚度可在高图案密度区和低图案密度区之间变化。本领域的技术人员应理解，有源区域可包括可形成一个或多个半导体器件的芯片的区域，而无源区域可包括没有半导体器件的芯片的区域。此外，有源区域比没有鳍的非有源区域具有更高的图案密度（例如，更多的鳍）。
发明内容
根据本发明的一个实施例，提供一种方法。该方法可包括：提供由半导体基板的蚀刻成以及由氧化物层和氮化物层覆盖的多个鳍，氧化物层设置在多个鳍和氮化物层之间，去除多个鳍的一部分以形成开口，在开口的侧壁上形成电介质间隔壁。该方法还把包括用填充材料填充开口。该方法还可包括用填充材料填充开口，其中填充材料的顶表面与氮化物层的顶表面实质上齐平，去除氮化物层以在多个鳍和填充材料之间形成间隙，其中填充材料具有在间隙之上延伸的凹形几何形状，并且去除凹形几何形状且使多个鳍和填充材料之间的间隙加大。
根据另一个示范性实施例，提供一种结构。该结构可包括自半导体基板蚀刻出的第一多个鳍和第二多个鳍、以及设置在半导体基板的上面以及第一多个鳍和第二多个鳍之间的填充材料，其中填充材料不接触第一多个鳍或第二多个鳍。
附图说明
结合附图将更好理解下文以示例的方式给出的但并不用来限制本发明仅仅如此的详细描述，附图中：
图1示出了根据示范性实施例的鳍型FET器件在其制造的中间步骤上的截面图。
图2示出了根据示范性实施例去除鳍以形成芯片的无源区域。
图3示出了根据示范性实施例形成一对电介质间隔壁。
图4示出了根据示范性实施例沉积填充材料。
图5示出了根据示范性实施例去除氮化物层。
图6示出了根据示范性实施例的第一蚀刻技术，用于去除填充材料中形成的凹形特征，与从鳍的顶部去除氮化物层和去除氧化物层一致。
图7示出了根据示范性实施例的第二蚀刻技术，用于去除任何的残留氧化物层。
图8示出了根据示范性实施例形成栅极。
图9示出了根据示范性实施例变化图案密度对覆盖栅极材料的平面性的影响。
附图不必按比例。附图仅为示意性表示，不意味着描绘本发明的具体参数。附图旨在仅描绘本发明的典型实施例。在附图中，相同的附图标记表示相同的元件。
具体实施方式
本文公开了所要求保护的结构和方法的具体实施例；然而，可以理解的是，所公开的实施例仅为所要求结构和方法的示例，其可以以不同的形式实施。然而，本发明可以以很多不同的形式实施，而不应解释为限于这里阐述的示范性实施例。相反，提供这些示范性实施例使本公开透彻和完整，并且向本领域的技术人员全面传达本发明的范围。在描述中，已知特征和技术的细节可以省略以避免对所提出的实施例的不必要的掩盖。
本发明涉及鳍型FET器件的制造，特别是，在具有变化器件密度的多组鳍FET上实现相同的栅极高度。栅极高度由于变化图案密度而发生变化，例如，晶片中图案化的鳍的密度。可能有利的是在鳍FET器件的形成过程中使栅极高度的变化最小化，以减少后续工艺的复杂性且改善产率和可靠性。
鳍型FET器件可包括形成在晶片中的多个鳍；覆盖所述多个鳍的一部分的栅极，其中鳍由栅极覆盖的部分用作器件的沟道区域，并且鳍从栅极下向外延伸的部分用作器件的源极和漏极区域；以及在栅极的相对侧上的电介质间隔壁。本实施例可实施在先栅极或后栅极鳍型FET制造工艺流程中，然而，后栅极，或者置换栅极（RG）工艺流程依赖于下面的详细描述。
在RG工艺流程中，半导体基板可图案化且蚀刻以形成鳍。接下来，虚设栅极可形成在垂直于鳍的长度的方向上。例如，虚设栅极可从多晶硅的覆盖层图案化且蚀刻。一对间隔壁可沉积在虚设栅极的相对侧壁上。稍后，虚设栅极例如可通过诸如反应离子蚀刻（RIE）的各向异性垂直蚀刻工艺从间隔壁对之间去除。这在间隔壁之间开口，然后在该开口可形成金属栅极。典型的集成电路可分成有源区域和无源区域。有源区域可包括鳍型FET器件。每个有源区域可具有不同的图案密度或者不同数量的鳍型FET器件。
现在参见图1-8，示出了根据本发明一个实施例形成结构100的示范性工艺步骤，并且现在将在下文更加详细地描述。应注意，图1-8全部表示为晶片的截面图，其具有形成在半导体基板中的多个鳍106。截面图定向为使垂直于多个鳍106的长度的视图被示出。此外，应注意，尽管该说明书可能以单数形式引用结构100的某些部件，但是在全部附图中可表示多个部件，并且相同的部件用相同的附图标记表示。图中所示的特定数量的鳍仅为了示例的目的。
现在参见图1，示出了工艺流程过程中的中间步骤的结构100的截面图。在该制造步骤上，结构100通常可包括多个鳍106，由基板蚀刻成，该多个鳍具有沉积在其上的氧化物层108以及氮化物层110。
半导体基板可包括体半导体或层叠的半导体，例如，Si/SiGe、绝缘体上硅（SOI）或绝缘体上SiGe（SGOI）。体半导体基板材料可包括非掺杂Si、n-掺杂Si、p-掺杂Si、单晶Si、多晶Si、非晶Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP和所有其它的III族/V族或II族/VI族化合物半导体。在图1所示的实施例中，可采用SOI基板。SOI基板可包括衬底基板102、形成在衬底基板102顶部的埋设的电介质层104以及形成在埋设的电介质层104顶部的SOI层（未示出）。埋设的电介质层104可隔离SOI层与基底基板102。应注意，多个鳍106可从SOI基板的最上层、SOI层蚀刻。
衬底基板102可由几种已知半导体材料的任何一种制造，例如，硅、锗、硅-锗合金、碳化硅、硅-锗碳化物合金和化合物（例如，III族-V族化合物和II族-VI族化合物）半导体材料。化合物半导体材料的非限定性示例包括砷化镓、砷化铟和磷化铟。通常，衬底基板102可为但不限于约几百微米厚。例如，衬底基板102的厚度可在0.5mm至约1.5mm的范围内。
埋设的电介质层104可包括几种电介质材料的任何一种，例如，硅的氧化物、氮化物和氮氧化物。埋设的电介质层104也可包括硅之外元素的氧化物、氮化物和氮氧化物。另外，埋设的电介质层104可包括晶体或非晶体电介质材料。而且，埋设的电介质层104可采用几种已知方法的任何一种形成，例如，热或等离子体氧化或氮化法、化学气相沉积法和物理气相沉积法。埋设的电介质层104的厚度可在约5nm至约200nm的范围内。在一个实施例中，埋设的电介质层104的厚度可在约150nm至约180nm的范围内。
SOI层，例如多个鳍106，可包括衬底基板102中包括的几种半导体材料的任何一种。通常，衬底基板102和SOI层根据化学成分、掺杂剂浓度和结晶取向可包括相同或不同的半导体材料。在本发明的一个特定实施例中，衬底基板102和SOI层包括的半导体材料至少包括不同的结晶取向。通常，衬底基板102或SOI层包括{110}结晶取向，并且衬底基板102或SOI层中的另一个包括{100}结晶取向。通常，SOI层的厚度可在约5nm至约100nm的范围内。在一个实施例中，SOI层的厚度可在约25nm至约30nm的范围内。用于形成SOI层的方法是本领域已知的。非限定性示例包括通过注氧隔离（Separation by Implantation of Oxygen,SIMOX）、晶片键合和外延层转移（Epitaxial Layer TRANsfer,ELTRAN
Figure BDA0000424085900000041
）。本领域的普通技术人员应理解，多个鳍106可从SOI层蚀刻。因为多个鳍106可由SOI层蚀刻成，所以它们也可包括上文列出的SOI层所有的任何特性。
氧化物层108可包括氧化硅或氮氧化硅。在一个实施例中，氧化物层108可这样形成，例如，将SOI层的顶表面热转化或等离子体转化成电介质材料，例如，氧化硅或氮氧化硅。在一个实施例中，氧化物层108可通过化学气相沉积（CVD）或原子层沉积（ALD）沉积氧化硅或氮氧化硅而形成。氧化物层108的厚度可在约1nm至约10nm的范围内，尽管小于1nm且大于10nm的厚度是可接受的。在一个实施例中，氧化物层108的厚度可为约5nm。
氮化物层110可包括任何适当的绝缘材料，例如，氮化硅。氮化物层110可采用已知的传统沉积技术形成例如，低压化学气相沉积（LPCVD）。在一个实施例中，氮化物层110的厚度可在约5nm至约100nm的范围内。在一个实施例中，氮化物层110的厚度可为约50nm。
现在参见图2，掩模层112可施加在结构100之上，并且用于形成一个或多个有源区域和一个或多个非有源区域，例如，第一有源区域114、第二有源区域116和非有源区域118。掩模层112可为诸如光致抗蚀剂的软掩模或诸如氧化物的硬掩模。掩模层112可覆盖且保护第一有源区域114和第二有源区域116，同时可去除设置在非有源区域118上的多个鳍106、氧化物层108和氮化物层110。非有源区域118上的多个鳍106、氧化物层108和氮化物层110可采用任何适当的非选择性蚀刻技术去除，例如，干蚀刻、湿蚀刻或者二者的结合。例如，采用CxFy基蚀刻剂的干蚀刻技术可用于从非有源区域118去除某些鳍106、氧化物层108和氮化物层110。优选的蚀刻技术将采用单一去除技术从非有源区域118去除某些鳍106、氧化物层108和氮化物层110，并且可产生开口120。在一个实施例中，某些鳍106、氧化物层108和氮化物层110可在交替的（alternate）蚀刻步骤中分别去除。优选地，掩模层112可排列为使适当量的氮化物层110保留在位于第一和第二有源区域114、116中的多个鳍106的侧壁上。然而，掩模层112的排列可导致某些蚀刻错误，进而沿着有源区域114的边缘留下不足量的氮化物层110，例如，如图所示的边缘122。相反，蚀刻错误，例如边缘设置上的错误，可沿着第二有源区域116的第二边缘124留下超过适当量的氮化物层110。
现在参见图3，可沿着非有源区域的侧壁形成一个或多个电介质间隔壁，例如，可沿着开口120的侧壁形成成对的电介质间隔壁126。成对的电介质间隔壁126通常可用于保证适当量的电介质材料来保护第一和第二有源区域114、116的多个鳍106。更具体而言，成对的电介质间隔壁126可形成为向第一或第二有源区域114、116的留存不足量的电介质材料的任何区域增加适当量的电介质材料，例如沿着第一边缘122，如图2所示。
成对的电介质间隔壁126可这样形成，共形沉积或生长电介质，之后进行定向蚀刻，从结构100的水平表面去除电介质，而在开口120的侧壁上将其留下。在一个实施例中，成对的电介质间隔壁126可包括任何适当的氮化物。在一个实施例中，成对的电介质间隔壁126可具有约3nm至约30nm范围内的水平宽度或厚度，最通常的是10nm。在一个实施例中，成对的电介质间隔壁126可包括与氮化物层110类似的材料。通常，成对的电介质间隔壁126可包括单层；然而，成对的电介质间隔壁126可包括多层电介质材料。
现在参见图4，填充材料128可采用本领域已知的任何适当沉积技术沉积在结构100的顶部上。填充材料128用来填充非有源区域，例如，非有源区域118。在一个实施例中，填充材料128可包括本领域已知的任何适当的氧化物材料。在一个实施例中，填充材料128可包括采用CVD沉积技术沉积的高纵横比氧化物。填充材料128可具有约50nm至约1000nm范围内的厚度。在一个实施例中，填充材料128可具有约200nm至约600nm范围内的厚度。优选地，填充材料128可具有大于氮化物层110高度的厚度。
在沉积在结构100的顶部后，填充材料128可采用CMP技术平坦化。CMP技术可对氮化物层110选择性地去除某些填充材料128。在一个实施例中，CMP技术可采用二氧化铈基浆凹陷填充材料128。在抛光前，填充材料128由于图案密度上的变化而可为非平面的，例如，如图9所示。用于抛光填充材料128的CMP技术可设计为改善平面度，并且可有利于消除填充材料128由于图案密度上的变化而导致的非平面表面。
现在参见图5，氮化物层110可以选择性地去除为使氧化物层108和填充材料128保留。选择性去除可采用适合于对氧化物选择性地去除氮化物的任何已知蚀刻技术实现。在一个实施例中，氢氟酸去垢（deglaze），之后采用热磷蚀刻剂的湿蚀刻技术，可用于去除氮化物层110。氮化物层110的去除可导致填充材料128具有凹形（re-entrant）几何形状130。凹形几何形状130可防止形成均匀的栅极进而导致器件可靠性问题。凹形几何形状130可防止随后形成可靠栅极结构，因为凹形几何形状可防止栅极材料的共形沉积。此外，凹形几何形状130还可防止虚设栅极材料的去除。残留的虚设栅极材料或者不足的栅极材料覆盖可影响器件的性能和可靠性。
现在参见图6，第一蚀刻技术可用于解决填充材料128的不希望的凹形几何形状130，并且去除某些或全部氧化物层108。优选地，清洗技术可去除凹形几何形状130。在一个实施例中，已知的化学氧化物去除（COR）蚀刻技术可用于去除凹形几何形状130。
所用的COR技术可包括将结构100暴露到HF和氨的气体混合物，优选比率为2﹕1，在1mTorr和10mTorr之间的压力下和约25℃的温度下。在该暴露期间，HF和氨气与填充材料128反应以形成固态反应产物。固态反应产物可随后通过将结构加热到约100℃的温度而去除，因此使反应产物蒸发。作为选择，反应产物可通过在水中清洗结构100而去除，或者用水溶液将其去除。
除了去除凹形几何形状130外，COR技术也可蚀刻填充材料128的侧壁。这可有效地减小填充材料128的宽度，并且增加多个鳍106和填充材料128之间的空间。例如，该空间可由图5中的尺寸（x）和图6中的（y）限定，其中（y）大于（x）。
现在参见图7，在去除不希望的凹形几何形状130后，第二蚀刻技术可用于从多个鳍106之上去除氧化物层108的任何残留材料。氧化物层108的剩余部分可采用适合于去除氧化物的任何已知的蚀刻技术去除。在一个实施例中，采用氢氟酸蚀刻剂的湿蚀刻技术可用于去除氧化物层108。去除氧化物层108可导致填充材料128进一步凹陷，使得填充材料128的顶表面可与多个鳍106的顶表面实质上齐平。
现在参见图8，接下来，在RG工艺流程中，栅极可形成在结构100上，并且通常的制造技术可用于完成半导体器件的形成。RG工艺流程可包括形成栅极氧化物148以及虚设栅极材料150。在大部分情况下，虚设栅极材料150可为牺牲的，并且在随后的操作中被取代。在某些情况下，栅极氧化物148可为牺牲的，并且在随后的操作中取代。
现在参见图9，示出了具有变化图案密度的结构200的截面图。结构200可包括基板202、鳍204和覆盖栅极材料层206。栅极材料层可包括RG工艺流程中所用的覆盖虚设栅极材料，或者先栅极工艺流程中所用的栅极材料的覆盖层。此外，结构200可包括高图案密度区域，例如，区域208，和低图案密度区域，例如，区域210。如前所述，高图案密度区域与低图案密度区域相比可包括较大数量的鳍。
示出了图案密度对覆盖栅极材料层206的平面性的影响。覆盖栅极材料层206的厚度或高度在高图案密度区域中可较厚或较高。应注意，氧化物层，如图1-8所示的氧化物层108，仅为了示出的目的从图9省略。
为了说明的目的已经对本发明的各种实施例进行了描述，但是不意味着详尽了所有的实施例或者将本发明限于所公开的实施例。在不脱离所描述实施例的范围和精神的情况下，很多修改和变化对本领域的普通技术人员来说是显见的。本文所用术语选择为更好地说明实施例的原理、市场中发现的技术上的实际应用或技术改进，或者能使本领域的普通技术人员理解本文所公开的实施例。

Claims (11)

1.一种方法，包括：
提供由半导体基板蚀刻成并由氧化物层和氮化物层覆盖的多个鳍，该氧化物层设置在所述多个鳍和所述氮化物层之间；
去除所述多个鳍的一部分以形成开口；
在所述开口的侧壁上形成电介质间隔壁；
用填充材料填充所述开口，其中所述填充材料的顶表面与所述氮化物层的顶表面实质上齐平；
去除所述氮化物层以在所述多个鳍和所述填充材料之间形成间隙，其中所述填充材料具有在所述间隙之上延伸的凹形几何形状；以及
去除所述凹形几何形状且使所述多个鳍和所述填充材料之间的所述间隙加大。
2.如权利要求1所述的方法，还包括：
去除所述氧化物层；以及
凹陷所述填充材料使所述填充材料的所述顶表面与所述多个鳍的顶表面实质上齐平。
3.如权利要求2所述的方法，还包括：
在所述多个鳍和所述填充材料之上和之间形成栅极。
4.如权利要求3所述的方法，其中形成所述栅极包括采用先栅极工艺流程或置换栅极工艺流程。
5.如权利要求1所述的方法，其中用填充材料填充所述开口包括沉积氧化物。
6.如权利要求1所述的方法，其中从半导体基板蚀刻而提供多个鳍包括提供体基板或绝缘体上半导体基板。
7.一种结构，包括
第一多个鳍和第二多个鳍，由半导体基板蚀刻成；以及
填充材料，设置在所述半导体基板之上以及所述第一多个鳍和所述第二多个鳍之间，其中所述填充材料不接触所述第一多个鳍或所述第二多个鳍。
8.如权利要求7所述的结构，还包括：
栅极，设置在所述第一多个鳍、所述第二多个鳍和所述填充材料之上和之间，其中所述栅极包括至少一种与所述填充材料不同的材料。
9.如权利要求7所述的结构，其中所述填充材料具有与所述第一多个鳍和所述第二多个鳍实质上相同的高度。
10.如权利要求7所述的结构，其中所述填充材料包括氧化物。
11.如权利要求7所述的结构，其中所述半导体基板包括体基板或绝缘体上半导体基板。
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