CN103828026A - 具有选择性形成的金属罩的集成电路结构 - Google Patents

具有选择性形成的金属罩的集成电路结构 Download PDF

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CN103828026A
CN103828026A CN201280044778.1A CN201280044778A CN103828026A CN 103828026 A CN103828026 A CN 103828026A CN 201280044778 A CN201280044778 A CN 201280044778A CN 103828026 A CN103828026 A CN 103828026A
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metal gates
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杨智超
D·V·霍拉克
查尔斯·W·库布尔格三世
P·邵姆
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GlobalFoundries Inc
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Abstract

本发明公开了形成使用在栅极之上的选择性形成的且至少部分氧化的金属罩的集成电路结构的方法，以及相关的结构。在一种实施例中，方法包括：提供包括晶体管的前体结构，晶体管具有金属栅极；在金属栅极的暴露部分之上形成止蚀层；至少部分氧化止蚀层；并且在至少部分氧化止蚀层之上形成介电层。

Description

具有选择性形成的金属罩的集成电路结构
相关申请的交叉引用
本申请要求在2011年9月15日提交的、题目为“IntegratedCircuit Structure Having Selectively Formed Metal Cap”的美国专利申请S/N:13/233,064的优先权，该专利申请的内容通过引用全文并入本文。
技术领域
本文所公开的主题涉及形成集成电路的方法以及由其形成的结构。更特别地，本发明的各方面涉及形成与晶体管的无边界接触件。
背景技术
照常规，在具有全金属栅极（FMG）的晶体管中形成自对准接触件包括使用介电罩以及在该罩之上的高k值材料层，该高k值材料层在自对准过程中充当止蚀层。介电罩和高k值材料的组合对于形成替代金属栅极（RMG）同样有用。但是，高k值材料在RMG方案中必须在介电罩之后形成。在该方案中，高k值材料保留于最终的集成电路器件（包括该结构）内。该高k值层存在于最终的集成电路器件内会增加在集成电路内的电容效应。所增加的电容能够不利地影响器件的性能。
发明内容
本发明公开了形成集成电路结构的方法，该集成电路结构使用在栅极之上的选择性形成的且至少部分氧化的金属罩。在一种实施例中，方法包括：提供包括晶体管的前体结构，该晶体管具有金属栅极；在金属栅极的暴露部分之上形成止蚀层；至少部分氧化止蚀层；并且在至少部分氧化的止蚀层之上形成介电层。
本发明的第一方面包括一种方法，该方法包括：提供包括具有金属栅极的晶体管的前体结构；在金属栅极的暴露部分之上形成止蚀层；至少部分氧化止蚀层；并且在至少部分氧化的止蚀层之上形成介电层。
本发明的第二方面包括一种形成集成电路结构的方法，该方法包括：形成具有暴露的金属栅极以及与暴露的金属栅极相邻的间隔物的晶体管结构；在暴露的金属栅极之上沉积止蚀层，除了间隔物之外；基本上氧化整个止蚀层；并且在止蚀层之上形成介电层。
本发明的第三方面包括一种集成电路结构，该集成电路结构具有：基板；位于基板之上的金属栅极；在基板之上的且基本上包围金属栅极的至少一个内衬层；以及直接位于金属栅极之上的至少部分氧化的止蚀层，该止蚀层包括钴（Co）、锰（Mn）、钨（W）、铱（Ir）、铑（Rh）或钌（Ru）中的至少一项。
附图说明
本发明的这些及其他特征根据下面结合用于示出本发明的各种实施例的附图进行的关于本发明的各方面的详细描述更容易理解，在附图中：
图1示出了常规集成电路结构的截面图。
图2示出了图1的集成电路结构在根据实施例执行的处理步骤之后的截面图。
图3示出了图2的集成电路结构在根据实施例执行的处理步骤之后的截面图。
图4示出了图3的集成电路结构在根据实施例执行的处理步骤之后的截面图。
图5示出了图4的集成电路结构在根据实施例执行的处理步骤之后的截面图。
图6示出了根据实施例的集成电路结构的截面图。
图7示出了根据可替换的实施例的集成电路结构的截面图。
应当注意，本发明的附图并不一定是按比例的。附图意在仅示出本发明的典型方面，并因此不应被认为是对本发明的范围的限定。在附图中，相似的编号在不同的附图中代表相似的元件。
具体实施方式
本文所公开的主题涉及形成具有在栅极之上的至少部分氧化的金属罩的集成电路结构的方法，以及这样形成的结构。更具体地，本发明的各方面提供具有选择性形成的且至少部分氧化的金属罩的集成电路结构，以及用于形成这样的结构的解决方案。
在一种实施例中，本发明的各方面包括一种形成集成电路结构的方法。该方法可以包括在金属栅极的暴露部分之上选择性地形成（例如，沉积）金属，其中金属栅极基本上分别包含于相邻的金属内衬和高k值的内衬层之内。金属能够按照包括化学气相沉积（CVD）、原子层沉积（ALD）或无电沉积（electroless deposition）在内的若干方式之一来沉积达大约0.5-10纳米的厚度。金属然后被氧化以形成选择性地位于金属栅极之上的止蚀层。在某些情况下，金属只是被部分氧化，使得外部区域被氧化而核心区域未氧化，其中核心区域直接接触金属栅极。
另一种实施例包括一种形成集成电路结构的方法，该方法包括：形成具有暴露的金属栅极的晶体管结构；选择性地将止蚀层（etch stoplayer）沉积于暴露的金属栅极之上；基本上氧化整个止蚀层；并且在止蚀层之上形成介电层。
另一种实施例包括一种具有金属栅极以及直接形成于金属栅极之上的选择性沉积的止蚀层的集成电路结构。止蚀层至少被部分氧化，并且可以包括钴（Co）、锰（Mn）、钨（W）、铱（Ir）、铑（Rh）或钌（Ru）中的一项或多项。在一种实施例中，止蚀层的内部（或核心）区域没有被氧化，而止蚀层的外面部分被氧化。在另一种实施例中，基本上整个止蚀层都被氧化。
转至图1，图中示出了现有技术的前体集成电路（IC）结构2的截面图。如同本文将进一步描述的，该前体IC结构2可以根据实施例被依次处理，以便形成非常规的集成电路结构。如图所示，前体IC结构2包括常规基板4。基板4可以包括硅、锗、硅锗、碳化硅以及基本由具有由化学式AlX1GaX2InX3AsY1PY2NY3SbY4定义的组成的一种或多种III-V族化合物半导体构成的那些半导体中的至少一项，其中X1、X2、X3、Y1、Y2、Y3及Y4代表相对比例，每个都大于或等于0，且X1+X2+X3+Y1+Y2+Y3+Y4=1（1是总的相对摩尔量）。其他合适的基板包括具有组成ZnA1CdA2SeB1TeB2的II-VI族化合物半导体，其中A1、A2、B1及B2是相对比例，每个都大于或等于0，且A1+A2+B1+B2=1（1是总的摩尔量）。而且，部分或整个半导体基板4会反生应变。
前体IC结构2还包括形成于基板4之上的两个常规的晶体管结构6（例如，场效应晶体管或FET）。由于这些常规的晶体管结构6的形成在本技术领域中是已知的，因而关于用来形成这些晶体管结构6的方法的描述在本文中被省略。另外，本文所描述的过程还可以应用于这些常规的晶体管结构6中的一个或多个，尽管这些过程在本文中可能仅参照单个晶体管结构6来描述。
在某些实施例中，一个或多个晶体管结构6可以包括金属栅极8，该金属栅极8可以由铝（Al）、铜（Cu）、铑（Rh）、铱（Ir）、钌（Rh）或钨（W）中的一项或多项形成。晶体管结构6还可以包括为金属栅极8加衬里的金属内衬10，其中金属内衬10包括钽（例如，氮化钽，TaN）、钨（例如，氮化钨，WN）或钛（例如，氮化钛，TiN）中的一项或多项。金属内衬10接触金属栅极8并且可以基本上包围或环绕着金属栅极8。包围金属内衬10的是高k值（或者，高介电常数）的内衬12，该内衬12可以由任何高介电常数的材料形成，例如，金属氧化物，如氧化钽（Ta2O5）、钛酸钡（BaTiO3）、氧化铪（HfO2）、氧化锆（ZrO2）、氧化铝（Al2O3），或者金属硅酸盐，如硅酸铪（HfA1SiA2OA3）或硅酸铪氧氮化物（HfA1SiA2OA3NA4），其中A1、A2、A3及A4代表相对比例，每个均大于或等于0，且A1+A2+A3+A4=1（1是总的相对摩尔量）。
高k值的内衬12与间隔物14相毗邻，该间隔物可以由常规的间隔材料（例如，氮化硅，Si3N4）形成。这些间隔物14近似位于与金属栅极8相邻或邻接之处，并且可以基本上包围金属栅极8。还示出的是包含于晶体管结构6内的导电层16，该导电层16可以由用于执行与晶体管结构6相关的功能的任何合适的接触金属形成。
图2示出了对图1的前体集成电路结构2执行的过程，其中该过程是根据实施例执行的方法的一部分。如图所示，图2示出了为金属栅极8选择性地形成止蚀层（例如，金属止蚀层）18。在一种实施例中，止蚀层18可以通过包括化学气相沉积（CVD）、原子层沉积（ALD）或无电沉积在内的一种或多种可选择的沉积技术来形成于金属栅极8之上。止蚀层18在某些实施例中可以沉积达大约0.5-10纳米（nm）的厚度。止蚀层18可以包括钴（Co）、锰（Mn）或钌（Ru）中的一项或多项。在某些实施例中，止蚀层18仅选择性地形成于金属栅极8之上。在其他实施例中，为金属栅极8以及金属内衬10和高k值的内衬12选择性地形成止蚀层18。沉积技术可以对半导体结构6的顶部或平面部分具有选择性，但除了间隔物14之外。如同本文所使用的，术语“选择性的（selective）”可以是包容性术语（inclusive term），使得形成对第二层有“选择性”的第一层意指第一层仅形成于第二层之上。正因如此，层在某些实施例中被形成，不包括其他未提及的层（例如，相邻层）。
如同本文将进一步描述的，与使用覆盖于栅极和间隔物两者之上的整体高k值的层的常规集成电路结构相比较，为金属栅极8选择性地形成止蚀层18允许具有降低的电容效应的金属栅极的电绝缘。在金属栅极8的材料与周围绝缘体的材料（例如，间隔物14）之间的对照（contrast）允许沉积对金属栅极8有选择性的止蚀层18。
图3示出了为形成氧化金属止蚀层（或氧化止蚀层）20而至少部分氧化图2的止蚀层18的过程。氧化止蚀层20可以通过含有等离子体的过程或者在含有氧气的或含有臭氧的气氛中的热过程来部分氧化或完全氧化。氧化过程允许氧化止蚀层20充当在金属栅极8与随后形成的接触层（如同参照图6和7所示出及描述的）之间的有效绝缘体。如图所示，图3示出了根据实施例的完全氧化止蚀层20。
图4示出了在图3的结构之上形成介电层22和介电层24的过程。介电层22、24可以包括一种或多种常规的介电材料，例如，二氧化硅（SiO2）、氮化硅（Si3N4）、碳化硅（SiC）、氧氢掺杂型碳化硅（SiCOH）等。这些介电层22、24可以使用例如化学气相沉积、旋涂法等常规技术来形成。应当理解，这些介电层22、24能够被形成为单个介电层或多个介电层，这是本技术领域所已知的。
图5示出了分别在介电层22和介电层24中形成开口26的过程。开口26被形成以使导电层16沿着间隔物14的边露出，用于接触的后续形成（图6和7）。开口26可以使用任何常规的蚀刻技术来形成，并且优选地被选择性形成（各向异性地）。在某些情况下，开口26可以是自对准的，也就是，开口26的形成由下垫层（例如，氧化止蚀层20和间隔物14）的抗蚀性决定。在任何情况下，氧化止蚀层20能够充当在金属栅极8之上的止蚀层，以保护栅极8在蚀刻过程中免受物理损坏。另外，氧化止蚀层20能够使栅极与形成于开口26内的以后形成的触头（例如，在图6和7中的触头28）物理及电隔离。
图6示出了在开口26内形成至导电层16的触头28的过程。触头28可以使用任何常规的方法（例如，沉积和/或外延生长）来形成，并且可以由包括Cu、W等中的一项或多项在内的常规接触材料形成。触头28可以通过例如填充开口来形成，并且多余的接触材料可以使用常规方法（例如，CMP或其他抛光/平坦化方法）回蚀或（否则的话）去除。氧化止蚀层20能够使金属栅极8与触头28在触头28的形成期间及之后物理及电隔离（或分离）。如图所示，该最终的集成电路结构102包括：基板4；位于基板4之上的金属栅极8；在基板4之上且基本上包围金属栅极8的至少一个内衬层（金属内衬10或高k值的内衬12）；以及直接位于金属栅极8之上的氧化止蚀层20。如本文所描述的，氧化止蚀层20可以包括钴（Co）、锰（Mn）或钌（Ru）中的至少一项，并且近似被完全氧化。
图7示出了集成电路结构202的一种可替换实施例，其中止蚀层20只是被部分氧化。在这种情况下，止蚀层20包括与金属栅极8直接接触的未氧化的核心区域30，以及基本上包围核心区域30（除核心区域30的与金属栅极8接触的部分外）的外部（或周围）区域32。外部区域32可以使用本文所描述的常规技术来氧化，并且在某些情况下通过在氧化过程中部分氧化止蚀层20来形成，使得内核30保留为未氧化的。
本文所使用的术语仅用于描述特定实施例，而并非旨在对本公开内容的限定。如同本文所使用的，单数形式“一”、“一个”及“该”意指同样包括复数形式，除非上下文另有清楚说明。还应当理解，术语“包括”和/或“包含”在用于本说明书时指示存在着所阐明的特征、整数、步骤、操作、元件和/或构件，但是并不排除存在或另加一个或多个其他特征、整数、步骤、操作、元件、构件和/或它们的分组。
在下面的权利要求书中的相应的结构、材料、动作以及所有方法或步骤加功能元件的等同物意指包括用于结合所特别声明的其他要求权利的要件来执行功能的任何结构、材料或动作。本公开内容的描述已经为了说明和描述而给出，但是并非意指为穷尽性的或者将本公开内容限定于所公开的形式。本领域技术人员应当清楚不脱离本公开内容的范围和精神的许多修改和变化。实施例被选择并被描述，以便最佳地解释本公开内容的原理及实际应用，并且使本领域技术人员能够理解用于具有适合于可想到的特定用途的各种修改的各种实施例的公开内容。

Claims (20)

1.一种形成集成电路结构的方法，所述方法包括：
提供包括晶体管（6）的前体结构，所述晶体管具有金属栅极（8）以及与所述金属栅极相邻的间隔物（14）；
在所述金属栅极的暴露部分之上形成止蚀层（18）；
至少部分氧化（20）所述止蚀层；以及
在所述至少部分氧化的止蚀层之上形成介电层（22）。
2.根据权利要求1所述的方法，还包括：
在所述介电层内形成延伸至所述止蚀层（20）的开口（26）；以及
在所述开口内形成触头（28）。
3.根据权利要求2所述的方法，其中在所述介电层内形成所述开口包括蚀刻所述介电层，其中所述止蚀层在蚀刻期间防止对所述金属栅极的蚀刻，并且其中所述止蚀层在形成所述触头之后使所述金属栅极与所述触头物理及电隔离。
4.根据权利要求1所述的方法，其中所述止蚀层作为金属层仅选择性地形成于所述金属栅极的所述暴露部分之上。
5.根据权利要求4所述的方法，其中对所述止蚀层的至少部分氧化包括氧化基本上整个所述止蚀层。
6.根据权利要求4所述的方法，其中对所述止蚀层的至少部分氧化包括仅氧化所述止蚀层的外面部分（32）。
7.根据权利要求4所述的方法，其中所述金属层包括钴（Co）、锰（Mn）、钨（W）、铱（Ir）、铑（Rh）或钌（Ru）中的至少一项。
8.根据权利要求1所述的方法，其中所述止蚀层的形成包括仅将所述止蚀层沉积于所述金属栅极的所述暴露部分之上。
9.根据权利要求8所述的方法，其中沉积使用化学气相沉积（CVD）、原子层沉积（ALD）或无电沉积来执行。
10.根据权利要求1所述的方法，其中所述止蚀层具有在大约0.5纳米与10纳米之间的厚度。
11.根据权利要求1所述的方法，还包括：在与所述金属栅极邻接的金属内衬（10）之上以及与所述金属内衬邻接的高k值的内衬（12）之上选择性地形成所述止蚀层。
12.一种形成集成电路结构的方法，所述方法包括：
形成晶体管结构（6），所述晶体管结构具有暴露的金属栅极（8）以及与所述暴露的金属栅极相邻的间隔物（14）；
在所述暴露的金属栅极之上沉积止蚀层（18），除所述间隔物外；
基本上氧化（20）整个所述止蚀层；以及
在所述止蚀层之上形成介电层（22）。
13.根据权利要求12所述的方法，还包括：
在所述介电层内形成延伸至所述止蚀层的开口（26）；并且
在所述开口内形成触头（28）。
14.根据权利要求13所述的方法，其中在所述介电层内形成所述开口包括蚀刻所述介电层，并且其中所述止蚀层在蚀刻期间防止对所述金属栅极的蚀刻，并且其中所述止蚀层在形成所述触头之后使所述金属栅极与所述触头物理及电隔离。
15.根据权利要求12所述的方法，其中所述止蚀层是包括钴（Co）、锰（Mn）或钌（Ru）中的至少一项的金属层。
16.根据权利要求12所述的方法，其中所述止蚀层的沉积包括仅在所述暴露的金属栅极之上沉积所述止蚀层，并且使用化学气相沉积（CVD）、原子层沉积（ALD）或无电沉积来执行。
17.一种集成电路结构，包括：
基板（4）；
位于所述基板之上的金属栅极（6）；
在所述基板之上且基本上包围所述金属栅极的至少一个内衬层（12）；以及
直接位于所述金属栅极之上的至少部分氧化的止蚀层（30，32），所述止蚀层包括钴（Co）、锰（Mn）、钨（W）、铱（Ir）、铑（Rh）或钌（Ru）中的至少一项。
18.根据权利要求17所述的集成电路结构，还包括与所述至少一个内衬层相邻的间隔物部件（14），其中所述止蚀层仅形成于所述金属栅极及所述至少一个内衬层之上。
19.根据权利要求17所述的集成电路结构，其中所述止蚀层只是被部分氧化。
20.根据权利要求17所述的集成电路结构，其中所述止蚀层被完全氧化。
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