CN103826072A

CN103826072A - Miniature infrared imaging system

Info

Publication number: CN103826072A
Application number: CN201410049548.5A
Authority: CN
Inventors: 蓝金辉; 李红福; 曾溢良; 邹金霖
Original assignee: University of Science and Technology Beijing USTB
Current assignee: University of Science and Technology Beijing USTB
Priority date: 2014-02-13
Filing date: 2014-02-13
Publication date: 2014-05-28
Anticipated expiration: 2034-02-13
Also published as: CN103826072B

Abstract

The invention discloses a miniature infrared imaging system. According to the miniature infrared imaging system, an infrared camera lens which works in a specific band is utilized to converge infrared radiation emitted by a target object to an infrared focal plane array, and the infrared focal plane array generates response signals for the infrared radiation, and a readout circuit outputs the response signals to a signal processing board, and the signal processing board performs a series of signal processing on the response signals, and finally, the response signals are synthetised into standard video signals which are transmitted to a display screen that displays the standard video signals. The system can perceive, acquire, process and display the infrared radiation emitted by the target in real time and can realize a storage function. In signal processing, the invention provides a novel space and time domain-combined infrared image filtering and denoising method. The miniature infrared imaging system has the advantages of low power consumption, small size, light weight, low cost and high reliability. Based on the above advantages, the application of the miniature infrared imaging system of the invention has broad prospects in the military, commercial and industrial fields.

Description

A kind of Minitype infrared imaging system

Technical field

The invention belongs to infrared image field, be specifically related to FPGA(Field Programmble Gate Array, field programmable gate array) technology, hardware description language (Verilog language), SOPC technology, Digital Image Processing and VGA Display Technique.A kind of system and method that moving target real-time Infrared video is taken that is suitable for is particularly provided.

Background technology

Along with the progress of science and the development of technology, infrared imagery technique is widely used in the every field such as military affairs, industry, business, medical treatment, forest fire protection, environmental protection.No matter be in national defence, or industrial, and in scientific research, infrared imagery technique has application extremely widely in these are related to the field of national economy, plays a part can not be ignored.Can say that infrared imagery technique is one of key technology of weighing a national military strength.

Infrared imagery technique is emerging after World War II infrared signal conversion the technology processed, mainly studies transmitting, the transmission of infrared energy, rule and the implementation procedure thereof of reception.All temperature of nature are higher than the object thermal radiation towards periphery of absolute zero (273.15 ℃), this is because the object in the Nature is all by molecular composition, and the charged particle of interior of articles is all in ceaselessly motion, interparticle relative motion will produce heat energy, infrared radiation belongs to a thermal-radiating part, and the thermal radiation Main Ingredients and Appearance that the object in normal temperature sends is exactly infrared radiation.Infrared radiation is a kind of invisible light, and it is adjacent with visible wavelength.Wherein, visible light wavelength is between 0.38～0.76um, and ultrared wavelength is between 0.76～1000um.Intensity and spectral component that the radiation temperature of object is sent to infrared radiation are directly proportional, and obviously, the temperature of the target object more intensity of high infrared radiation is just larger, and the intensity of the low radiation of temperature is just low.Non refrigerating infrared imaging instrument is generally operational in 8～14um wave band.

Most of high accuracy infrared imaging devices are all to adopt FPGA+DSP framework in the market, and wherein DSP relies on its powerful operational capability mainly to realize data operation, data communication and data management function; And FPGA has online programming ability flexibly, mainly realize the fixing signals such as the compensation of nonuniformity correction, blind element, video be synthetic and process and sequencing control function, the two real-time processing to infrared image that cooperatively interacted.But, in these systems, need frequently to switch the control to memory based on the time-multiplexed DSP of bus and FPGA, this will inevitably reduce the data transmission efficiency of whole system, the complexity that increases analyzing logic control, nonsystematic design and application bring inconvenience.The more important thing is, adopt the circuit volume of DSP+FPGA framework larger, be difficult to the requirement of adaptive system miniaturization.

The present invention proposes a kind of SOPC technology based on FPGA, utilizes programmable system on sheet, realizes the requirement of miniaturization low-power consumption.Nowadays, embedded system is towards high-performance more, more small size, more low-power consumption, more cheap future development, and the design and development of embedded system is towards based on chip, the particularly future development of system-level programmable chip (SOPC).Simultaneously in order to reduce development difficulty, normal employing merged microprocessor technology, Digital Signal Processing, the design of system-level programmable chip and Hardware/Software Collaborative Design in the method for designing based on embedded intelligent platform of one, to improve the development efficiency of system, shorten the cycle in product introduction market.Along with the progress of large scale integrated circuit design technology and the raising of manufacturing technology level, and the increase of logic gate number on chip, Embedded System Design is increasingly sophisticated, on one single chip, logic gate number is increased in when making design objective become complicated, also for designer's development and Design has been opened up new world, whole system can be integrated on a chip, i.e. so-called system-on-chip technology (SOC), SOC is the inexorable trend of integrated circuit development.

Summary of the invention

The object of the invention is to provide a kind of small low-consumption low cost infrared imaging system, than traditional infrared imaging system, there is the characteristics such as low cost, low-power consumption, miniaturization, reliability height, this system is suitable for modularized design simultaneously, upgradability is good, be convenient to safeguard, reliability is high, and it is convenient to transplant.

For achieving the above object, the present invention adopts following technical proposals:

Small low-consumption low cost infrared imaging system of the present invention comprises power circuit module, analog voltage acquisition module, the processing of FPGA image and modular converter, vision signal synthesis module, infrared lens, Uncooled focal plane array row, LCD MODULE and SDRAM, serial FLASH module.This FPGA adopts the EP2C5Q208C8 model chip of the Cyclone II series that the cost performance of altera corp is high, use the SDRAM of 1M × 4Banks × 16Bits to carry out the buffer memory of video data, serial FLASH is realized solidifying of FPGA program, utilize jtag interface to realize plate level on-line debugging, Video Decoder converts the analog video signal of infrared focal plane array output to the digital video signal of ITU-BT.656 form, deliver to and in FPGA, carry out deinterleaving, go here and there and change, color notation conversion space, the operations such as image processing, by fifo buffer, vision signal is deposited in SDRAM, deposited a two field picture reads vision signal again and delivers to and in video encoder, carry out the synthetic of video standard signal from SDRAM by FIFO, video encoder is under the control of FPGA output display clock, and show line by line effective infrared video under the video display module control of constructing in FPGA.

Above-mentioned memory module adopts the SDRAM chip of 1M × 4Banks × 16Bits size, the space of total 64M size is divided into 4 Bank, and each Bank is the space of 1M size, needs 12 address wires, communicating by letter with FPGA is 16 digital video data, and fetch data is R[7:3], G[7:2], B[7:3].

Above-mentioned video decode module is used for receiving the analog signal of infrared focal plane array output, the infrared radiation of target object receives and is converged to Uncooled focal plane array through infrared optical lens and lists, the heat distribution field of the thermo-sensitive material induction targets of focal plane array, and become the voltage signal Video Decoder of exporting to line by line to decode temperature transition, Video Decoder converts analog video signal to the digital video signal of ITU-BT.656 form, deliver in FPGA and process, FPGA is configured video decoding chip by I2C interface.

Above-mentioned series arrangement module is used for program Solidification in fpga chip, the present invention FPGA used is based on SRAM technique, after power down, FPGA reverts to white, internal logic relation is lost, must configure the special storage chip EPCS16 of a slice to FPGA, storage program curing after FPGA powers on, is transferred to program in the RAM of FPGA inside and is moved from configuring chip EPCS16.

Above-mentioned FPGA inter-process module is used for digital video signal to process, and is cached in SDRAM so that the demonstration of follow-up real-time video by fifo buffer.Concrete steps in FPGA inter-process are as follows:

Step 1: the digital video frequency flow that Video Decoder is sent here carries out deinterleaving, by continuous judgement FF, 00,00 and XY carry out F, V, the judgement of the extraction of H and effective video signal, thereby produce YCbCr effective video signal, identification trip, field sync signal and parity field signal;

Step 2: 4:2:2 serial data is transformed into the parallel data of 4:4:4, the Cb of intercalary delection, Cr value produces by the mode of interpolation.Design a counter and select, counting is 0 and within 2 o'clock, is Cb, Cr signal, and counting is 1 and is Y-signal in 3 o'clock, thereby completes the process that serial signal transfers parallel signal to;

Step 3: the data value that effective YCbCr data value of separating is converted to rgb format.Carry out according to following formula to the conversion of RGB for YCbCr:

R=1.164（Y-16）+1.596（Cr-128）

G=1.164（Y-16）-0.813（Cr-128）-0.392（Cb-128）

B=1.164（Y-16）+（Cb-128）

In FPGA, realize with Verilog language, the vision signal after conversion is deposited in and in SDRAM, is carried out buffer memory by fifo buffer;

Step 4: by the Infrared Video Signal after conversion, first carry out background estimating, then it is carried out to time-domain difference computing, to reduce video noise, realize the large-scale background of eliminating by time domain variance filter method again, finally utilize spatial domain edge strength filtering to carry out edge to infrared image and give prominence to.

Small low-consumption low cost infrared imaging system of the present invention, feature is to adopt FPGA to make the features such as designed system has low-power consumption, flexible design, portability is high, upgradability is strong as main process chip, and utilize the intrinsic concurrency of FPGA hardware and unique system of tabling look-up to carry out the algorithm of infrared image processing, realize software algorithm Hardware, guaranteed the requirement of system real time.Be widely used in the every field such as military affairs, industry, business, medical treatment, forest fire protection, environmental protection.

Accompanying drawing explanation

Fig. 1 is the hardware frame figure of infrared video real-time acquisition and display hardware system of the present invention;

Fig. 2 is system power supply module frame chart of the present invention;

Fig. 3 is system video decoder module hardware frame figure of the present invention;

Fig. 4 is FPGA minimum systematic module hardware frame figure of the present invention;

Fig. 5 is system sdram memory module hardware frame figure of the present invention;

Fig. 6 is system serial download configuration module hardware frame figure of the present invention;

Fig. 7 is system video coding module hardware frame figure of the present invention;

Fig. 8 is system video flow chart of data processing figure of the present invention;

Fig. 9 is system colour space transformation flow chart of the present invention;

Figure 10 is Infrared video image filtering noise reduction flow chart of the present invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below with reference to accompanying drawing, a kind of small low-consumption low cost infrared imaging system of the present invention is described in further detail.

Fig. 1 has described the hardware frame figure of small low-consumption low cost infrared imaging system of the present invention.Hardware components is made up of power supply, video decode, the main processing of FPGA, Video coding, SDRAM, series arrangement chip, JTAG, AS, reset circuit, clock circuit.Video decoding chip converts digital video signal to the analog voltage signal of output and sends into and in FPGA, carry out a series of processing, and the vision signal of last synthetic standards outputs in display screen by VGA interface.Serial FLASH, for solidifying the program code of FPGA, is not loss storage of power down, and SDRAM is temporary for infrared image, waits and is filled with a frame output display.Coding and decoding video circuit carries out communicating by letter of digital video signal by well behaved connector with FPGA, and jtag interface is for the on-line debugging of program code.Reset circuit, clock circuit, power supply are the part of FPGA minimum system.

Fig. 2 has described system power supply module frame chart of the present invention.The present invention considers the power supply requirement of whole logical circuit, the core voltage of FPGA needs 1.2V, TVP5150 needs the voltage of 1.8V, 3.3V provides the IO voltage of most of circuit on plate and FPGA, TVP5150, ADV7123, wherein, bank1, the bank2 of FPGA and TVP5150 share a 3.3V, and bank3, the bank4 of FPGA and ADV7123 share a 3.3V.The reason of doing is like this heating causing because electric current is excessive in order to reduce LDO-3.3V.

From the 12V voltage of power supply output, through capacitor filtering, be input in MP1591 power conversion chip, the voltage of output obtains 5V burning voltage through inductance, the present invention adopts four AMS1117 chips, is respectively AMS1117-3.3V, AMS1117-1.8V, AMS1117-1.2V, AMS1117-3.3V, and utilizing these four chips is 3.3V, 1.2V and 1.8V by 5V voltage transitions, AMS1117 is a forward low dropout voltage regulator, presses down and reduces to 1.2V at 1A electric current.AMS1117 has two versions: fixing output version and tunable versions, and fixing output voltage is 1.5V, 1.8V, 2.5V, 2.85V, 3.0V, 3.3V, 5.0V, has 1% precision; Fixing output voltage is that the precision of 1.2V is 2%.The inner integrated overtemperature protection of AMS1117 and current-limiting circuit are the optimal selections of powered battery and portable computer.

Fig. 3 has described system video decoder module hardware frame figure of the present invention.TVP5150 is a super low-power consumption Video Decoder, sends into FPGA and processes convert digital video signal to from the analog voltage signal of Uncooled focal plane array row output.It is its analog-and digital-power supply supply that this decoder uses 1.8V, and provides voltage with 3.3V for I/O mouth.FPGA is by mode of operation and the parameter setting of I2C bus configuration TVP5150, and the design only uses AIP1A passage, and by AIP1B passage ground connection, crystal oscillator adopts the passive crystal oscillator of 14.31818MHZ.

The configuration of TVP5150 is to complete by I2C bus standard.I2C bus is carried out transfer of data by serial data input/output line (SDA) and clock input/output line (SCL), and standard speed is 100 kbit/s, and flank speed is 400 kbit/s.Native system builds I2C bus control unit at the inner Verilog of use of FPGA language, and the speed of use standard 100 kbit/s completes the configuration to TVP5150.According to I2C agreement, produce the sequence of operations such as initial conditions, addressing, write operation, complete respectively the assignment to each register, thereby realize the configuration to TVP5150.

Fig. 4 has described FPGA minimum systematic module hardware frame figure of the present invention.FPGA signal processing module, take the fpga chip EP2C5Q208C8 of Cyclone II series as core, is respectively configuring chip EPCS16 and SDRAM chip HY57V641620 around.Significant data and configuration information in the main memory image processing procedure of storage chip, because considering and FPGA frequent exchange data, therefore in the time of component placement, as long as the in the situation that of permission in space, as far as possible near master chip, and holding wire guarantees coupling and isometric as far as possible, avoid causing in transmitting procedure signal delay.Coding and decoding video module is from row's pin introducing on limit above, and codec chip is placed on respectively the right and left, avoids crosstalking between them.Power module provides stable voltage by contact pin for coding and decoding video module and FPGA signal processing module.The stand of 2 double ten pins on the left side is the peripheral interface of JTAG and AS, and jtag interface is mainly used to realize the debugging of whole system, and AS interface is mainly under AS pattern, to select pof file to download to Cyclone II chip, by program Solidification in fpga chip.

Fig. 5 has described system sdram memory module hardware frame figure of the present invention.The design selects the HY57V641620 model chip of Hynix company, and HY57V641620 is the high-performance dynamic random access memory that a kind of CMOS of employing technique is manufactured, and is divided into 4 BANKS, and each BANK is 1M × 16bits.All input and output are synchronizeed with the rising edge of clock input.The inner streamline of data path reaches very high bandwidth, the compatibility of all input and output voltage levels and LVTTL.

VGA display pixel clock involved in the present invention is 800*600@60Hz's, and transmission speed will reach 40M*16bit.Therefore, realize infrared video and show in real time, must be with SDRAM first by the data buffer storage of handling, after the data of a frame are all written in SDRAM, read again in video d/a chip and shown, just can be seen that VGA shows full picture and keeps stable always.

Fig. 6 has described system serial download configuration module hardware frame figure of the present invention.Most of FPGA is based on SRAM technique, and the chip of SRAM technique information after power down will be lost, so in order to complete the configuration to FPGA in the time that every subsystem powers on, need to separately add the special configuring chip of a slice FPGA.While powering on, FPGA is loaded into the program in configuring chip and data in ram in slice, completes after configuration, and FPGA enters normal operating conditions.And after power down, the circuit logic relation of FPGA inside disappears automatically, now FPGA reverts to again empty chip, and FPGA has two kinds of downloading modes, and one is JTAG pattern, facilitate on-line debugging program to use, another kind is that series arrangement pattern is AS pattern, and fpga chip power down is save routine not, when needs by program Solidification in FPGA time, just need to use AS pattern, by program Solidification in the configuring chip of the EPCS16 of FPGA.

Fig. 7 has described system video coding module hardware frame figure of the present invention.Native system need to build the required line synchronizing signal H of VGA interface, field sync signal V and the simulated video d/a transducer control signal used of digital image information of standard in FPGA.Native system output be that clock is that 40 MHz, field frequency are the video data that 60 Hz, vaild act 600, every row effective pixel points are 800, there are 1056 clocks so construct as calculated every row, have the picture frame period of 628 row, within this frame period, utilize counter to construct to meet line synchronizing signal (H_SYNCH), row crop signal (H_FRONT_PORCH), row back porch signal (H_BACK_PORCH), field sync signal (V_SYNCH), a crop signal (V_FRONT_PORCH), a back porch signal (V_BACK_PORCH) of VGA standard.Clock is input to mould and equals, in 1056 pixel pulse counter, to count in 40～168 interpulse output low levels when pixel pulse, other export high level, using this as line synchronizing signal H_SYNCH; Then count take the capable beat of H_SYNCH as unit, when meter output low level to 1 and 5 time, other exports high level, and in the time counting to 628 line synchronizing signals, counter is clear 0, using this as field sync signal V_SYNCH.In like manner build trip crop signal (H_FRONT_PORCH), row back porch signal (H_BACK_PORCH), a crop signal (V_FRONT_PORCH), a back porch signal (V_BACK_PORCH) with counter, the sequential of having constructed is delivered in D/A conversion chip ADV7123 together with the RGB data flow converting to control signal.

Fig. 8 has described system video flow chart of data processing figure of the present invention.Hardware circuit has been mainly used to collection and the transmission work of data, and the processing of video data conversion, total line traffic controls etc. realize by the logical circuit of FPGA inside.The logical circuit of the main process chip FPGA the inside of native system mainly comprises PLL phase-locked loop generation module, I2C bus configuration module, data acquisition and processing module and video display module.Wherein PLL phase-locked loop module provides operating frequency for SDRAM module for reading and writing, VGA display module, FPGA processing module; I2C bus configuration module provides the configuration of the registers such as channel selecting, address choice, contrast, colourity for Video Decoder; Data acquisition and processing modules implement receiving video signals, utilize FIFO to realize and the cross clock domain transfer of data of SDRAM, and color notation conversion space etc.; Video display module, by the data synthetic standards video receiving from FIFO, is delivered to ADV7123 chip and is processed.The modules desired function of completing circuit that mutually cooperates with, native system adopts hardware description language Verilog to realize the function of the inner modules of FPGA.

Fig. 9 has described system colour space transformation flow chart of the present invention.The data of the BT.656 form that this module is sent here video decoding chip in FPGA by three steps convert.The first step is de-interleaving block, produces YCbCr effective video signal, identification trip, field sync signal.The ITU-R BT.656 data that one frame is complete are divided into two of odd evens, 288 byte that every row ITU-R BT.656 data start are row control signal, 4 byte that start are that EAV(effective video finishes) signal, and then 280 fixing padding datas, last 4 byte are that SAV(effective video is initial) signal.SAV signal and EAV signal have that 3 byte's is leading: FF, 00,00; Last 1 byte XY is by fixed data 1, F(parity flag position), V(vertical blanking flag bit), H(horizontal blanking mark) and by F, V, H calculates low 4 compositions that generate.By continuous judgement FF, 00,00 and XY carry out F, V, the judgement of the extraction of H and effective video signal, for follow-up video control, frame buffer and DAC module sequential structure provide control signal; Second step is for to go here and there and to change, and this module is transformed into 4:2:2 serial data the parallel data of 4:4:4, the Cb of intercalary delection, and Cr value produces by the mode of interpolation.Design a counter and select, counting is 0 and within 2 o'clock, is Cb, Cr signal, and counting is 1 and is Y-signal in 3 o'clock, thereby completes the process that serial signal transfers parallel signal to, realizes the separation of YCbCr serial data; The 3rd step is color space conversion, and this module converts the data value of rgb format to effective YCbCr data value of separating according to certain formula, to deliver to the output display that carries out video data in DAC.

Figure 10 has described the filtering noise reduction flow chart of Infrared video image of the present invention.This module realizes the background filtering noise reduction process of Infrared video image by three steps.The first step is that infrared image sequence is carried out to time domain low-pass filtering, and carries out difference with original infrared image sequence, the infrared image of the noise that is reduced; Second step is that the differential signal obtaining is carried out to the processing of time domain variance filter, and this step can be eliminated background on a large scale; The 3rd step is that the filtered video of variance is carried out to the intensity filtering processing of edge, spatial domain, takes full advantage of the gradient correlation method characteristic of infrared image, and the edge that can realize infrared image strengthens, projecting edge information.

Claims

1. a Minitype infrared imaging system, is characterized in that: described imaging system comprises power circuit module, analog voltage acquisition module, the processing of FPGA image and modular converter, Video signal encoding module, vision signal decoder module, infrared lens, Uncooled focal plane array row, LCD MODULE and SDRAM, serial FLASH module, the infrared radiation that target object sends is received by infrared lens through propagation in atmosphere, and converge on described un-cooled infrared focal plane array, un-cooled infrared focal plane array is by the infrared radiation input that is transformed into analog voltage signal and outputs to vision signal decoder module line by line, converting thereof into digital video signal by the Video Decoder in decoder module is input in FPGA image and processes with modular converter and carry out deinterleaving, go here and there and change, color notation conversion space, the processing such as image filtering noise reduction, then video data is cached in outside SDRAM, deposit a frame and just outputed to the real-time demonstration that completes video in Video signal encoding module.

2. imaging system according to claim 1, is characterized in that, described imaging system adopts SOPC technology, and three board layer stack structure designs have realized the miniaturization of system; And the FPGA core voltage of employing 1.2V.

3. infrared imaging system according to claim 1, it is characterized in that: described analog voltage acquisition module, supplied by independent 14.318MHz crystal oscillator, FPGA is configured the internal register of Video Decoder by I2C bus, when Video Decoder has been configured, the analog voltage signal of Uncooled focal plane array row output is sent in Video Decoder and decoded, and the video data that converts thereof into ITU-R BT.656 form is delivered in FPGA and is processed.

4. infrared imaging system according to claim 2, is characterized in that: described configuration comprises the information such as colourity, contrast, saturation.

5. infrared imaging system according to claim 1, it is characterized in that: described FPGA image is processed and modular converter, in to the real-time processing of infrared image, utilize the intrinsic concurrency of FPGA hardware and unique system of tabling look-up to carry out the algorithm of infrared image processing, realize software algorithm Hardware, guaranteed the requirement of system real time.

6. infrared imaging system according to claim 1, is characterized in that: described color-space conversion module, realize the conversion from the video data of ITU-R BT.656 form to rgb signal, and concrete steps are as follows:

Step 1: the digital video frequency flow that Video Decoder is sent here carries out deinterleaving, produces YCbCr effective video signal, identification trip, field sync signal;

Step 2: the serial data of YCbCr4:2:2 form is converted to the parallel data of YCbCr4:4:4 by the mode of resampling, is convenient to next step conversion;

Step 3: the data value that effective YCbCr4:4:4 data value of separating is converted to rgb format.

7. infrared imaging system according to claim 1, it is characterized in that: the video of described vision signal synthesis module output is the vision signal of 24 RGB color spaces, output display valid pixel is 800 row, 600 row, field frequency is 60Hz, with FPGA interface be the rgb signal of 24, clock frequency is 40MHz, is provided by the clock of the inner synthetic output of Video Decoder, completes digital video and flow to the conversion of analog video data.

8. infrared imaging system according to claim 1, is characterized in that: described system is according to the performance of moving target, and the image filtering method that adopts a kind of new spatial domain to combine with time domain is realized the filtering noise reduction process to infrared image.