CN106506961A - A kind of image processing system and image processing method - Google Patents
A kind of image processing system and image processing method Download PDFInfo
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Abstract
The invention discloses a kind of image processing system, double byte view data is gathered using image capture device, double byte view data is split as high-order single byte view data and low level single byte view data by the field programmable gate array being connected with image capture device, high-order single byte view data and low level single byte view data are received using the processor being connected with field programmable gate array, high-order single byte view data and low level single byte view data are reconfigured as double byte view data, and carries out image procossing.Double byte view data is converted to high-low-position view data using field programmable gate array, processor is reconstructed to the view data for receiving.It can be seen that, double byte view data is split and is reconstructed, made the scope of collectable view data larger, and then improve the precision of image processing system result.Additionally, invention additionally discloses a kind of image processing method, have the advantages that above-mentioned image processing system.
Description
Technical field
The present invention relates to image processing field, more particularly to a kind of image processing system and image processing method.
Background technology
With the continuous progress of image processing techniquess, new demand is proposed to the precision of image processing system.And image
Scope of data handled by the precision of processing system result and image processing system has close relationship.
In recent years, the system that image processing system is generally based on arm processor, because the processor of ARM systems is compared
In other processors, which is that other types of process is incomparable in the performance such as power consumption and volume.By image procossing system
System combines with embedded, to make the performance of image processing system be highly improved.
The camera interface of the image processing system of arm processor typically using arm processor is now based on gathering figure
As data, the view data of the view data generally 8 of collection, i.e. view data represent that with 8 bits which gathers
The coded format of view data is generally BT.601 or BT.656.Picture number due to the collection of existing image processing system
According to for single byte view data, the scope of the view data for collecting can be made to have certain restriction, therefore to view data
When being processed, the precision of image processing system result can be limited by data bits.How image procossing system is improved
System result precision be this area problem demanding prompt solution, based on this, the present invention propose a kind of image processing system with
And image processing method.
Content of the invention
It is an object of the invention to provide a kind of image processing system, it is therefore intended that solve image processing system in prior art
The relatively low problem of the precision of result；It is another object of the present invention to provide a kind of image processing method, its image for gathering
The scope of data is big, and then makes the precision of the result of image processing system higher.
For solving above-mentioned technical problem, the present invention provides a kind of image processing system, and the system includes：
Image capture device, for gathering double byte view data；
The field programmable gate array being connected with described image collecting device, for splitting the double byte view data
For high-order single byte view data and low level single byte view data；
The processor being connected with the field programmable gate array, for receive the high-order single byte view data and
The low level single byte view data, by the high-order single byte view data and the low level single byte view data again
The double byte view data is combined as, and image procossing is carried out to the double byte view data.
Alternatively, Double Data Rate synchronous DRAM, random access memory, embedded multi-media card are also included
And touch screen.
Alternatively, described image collecting device is infrared focal plane detector, and wherein, the infrared focal plane detector is adopted
The double byte view data of collection is 14 bit image data；The infrared focal plane detector is included for output data clock
The first output port, for exporting the second output port of synchronizing signal, for exporting the low 7 of the 14 bit image data
3rd output port of view data, for export the 14 bit image data high 7 bit image data the 4th output port.
Alternatively, the field programmable gate array includes：
For receiving the first receiving port of the data clock, first receiving port passes through Data_Clk holding wires
It is connected with first output port；
For receiving the second receiving port of the synchronizing signal, second receiving port passes through Data_Sync signals
Line is connected with second output port；
For receiving the 3rd receiving port of the low 7 bit image data, the 3rd receiving port passes through Data1_Out
Holding wire is connected with the 3rd output port；
For receiving the 4th receiving port of the high 7 bit image data, the 4th receiving port passes through Data2_Out
Holding wire is connected with the 4th output port；
For exporting the 5th output port of frame synchronizing signal；For exporting the 6th output port of line synchronising signal；With
The 7th output port in output pixel clock signal；For exporting the high-order single byte view data and the low level list
8th output port of byte image data.
Alternatively, the processor is arm processor, and the arm processor includes：
For receiving the 5th receiving port of the frame synchronizing signal, the 5th receiving port passes through VSYNC holding wires
It is connected with the 5th output port；
For receiving the 6th receiving port of the line synchronising signal, the 6th receiving port by HREF signal line with
6th output port is connected；
For receiving the 7th receiving port of the pixel clock signal, the 7th receiving port passes through PCLK signal line
It is connected with the 7th output port；
For receiving the 8th receiving terminal of the high-order single byte view data and the low level single byte view data
Mouthful, the 8th receiving port passes through DATA [7:0] holding wire is connected with the 8th output port.
Alternatively, described image collecting device is visible light wave range camera or ultraviolet band camera or infrared band camera.
Additionally, present invention also offers a kind of image processing method, the method includes：
Image capture device obtains double byte view data, and the double byte view data is transmitted to field programmable gate
Array；
The field programmable gate array by the double byte view data split into high-order single byte view data and
Low level single byte view data, the high-order single byte view data and the low level single byte view data are transmitted to place
Reason device；
The high-order single byte view data and the low level single byte view data are reconfigured by the processor,
Obtain the double byte view data.
Alternatively, the double byte view data is split into high-order single byte picture number by the field programmable gate array
According to this and low level single byte view data includes：
When the double byte view data is 14 bit image data, by high 7 bit image of the double byte view data
The Y location of data storage to BT.601；
Cb or Cr positions by the low 7 bit image data storage to the BT.601 of the double byte view data.
Alternatively, the processor is by the high-order single byte view data and the low level single byte view data weight
Combination nova, obtaining the double byte view data includes：
Adjacent described high 7 bit image data and the low 7 bit image data are reconfigured using character string function
For the double byte view data；
Wherein, the character string function is Val=Y<<7+Cb or Val=Y<<7+Cr.
A kind of image processing system provided by the present invention, the system gather double byte image using image capture device
The double byte view data is split as high-order single by data, the field programmable gate array being connected with described image collecting device
Byte image data and low level single byte view data, utilize the processor being connected with the field programmable gate array then
The high-order single byte view data and the low level single byte view data is received, by the high-order single byte view data
And the low level single byte view data is reconfigured for the double byte view data, and to the double byte view data
Carry out image procossing.Double byte view data image capture device gathered using field programmable gate array is converted to height
Position single byte view data, processor are reconstructed to the view data for receiving, and are reassembled into double byte view data, from
And image processing system is processed to double byte view data.It can be seen that, double byte view data is split and is reconstructed, made
The scope of the view data of collection is larger, and then improves the precision of image processing system result.Additionally, the present invention is also carried
A kind of image processing method is supplied, has been corresponded with the advantage of above-mentioned image processing system.
Description of the drawings
For the clearer explanation embodiment of the present invention or the technical scheme of prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
A kind of system block diagram of the specific embodiment of the image processing system that Fig. 1 is provided by the embodiment of the present invention；
The system block diagram of another kind of specific embodiment of the image processing system that Fig. 2 is provided by the embodiment of the present invention；
Fig. 3 is the signal timing diagram that infrared focal plane detector exports 14 bit image data；
Fig. 4 is the sequential chart that arm processor receives view data；
Fig. 5 is the schematic flow sheet of image-pickup method provided in an embodiment of the present invention.
Specific embodiment
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.Obviously, described embodiment be only a part of embodiment of the invention, rather than
Whole embodiments.Embodiment in based on the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
Refer to Fig. 1, a kind of specific embodiment of the image processing system that Fig. 1 is provided by the embodiment of the present invention is
System block diagram.
Image processing system not only has the processing function to the view data for gathering, and can also have adopting for view data
Data converting function in collection function and view data transmitting procedure.The image processing system provided by the embodiment of the present invention can
To include：
Image capture device 101, for gathering double byte view data；
It is understood that double byte view data refers to acquired image data with two byte representations.General feelings
Under condition, a byte is 8 bits, and the decimal numeral scope that can be represented is 0～255, and double byte is entered for 16 two
Number processed, the decimal numeral scope that can be represented are 0～65536.For double byte view data is compared to single byte view data,
The scope of its view data is bigger.Double byte view data can be 14 bit image data, or 16 bit image data, also
Or be other more than the view data of 8.And above-mentioned image capture device can be infrared focal plane detector, visible ray
Wave band camera, infrared band camera and ultraviolet band camera.When image capture device is infrared focal plane detector, which is red
Outer focus planardetector has thermometric and thermal imaging function simultaneously, by carrying out infrared acquisition to gathering target, so as to be adopted
The greyscale image data and temperature data of collection target.
It should be evident that the view data gathered using image capture device is double byte view data, collection can be made
The image information of target is included as much as possible, and then the image for making to collect accurately represents target image as far as possible.
The field programmable gate array 102 being connected with described image collecting device, for by the double byte view data
It is split as high-order single byte view data and low level single byte view data；
Using the field programmable gate array (Field- being connected with image capture device by data wire
Programmable Gate Array, FPGA) process come the double byte view data to receiving so that after process
View data can be processed and be received.The double byte view data for collecting is passed through data wire by image capture device first
Transmit to FPGA, FPGA receives double byte view data, and carries out fractured operation to double byte view data, obtains high-order individual character
Section view data and low level single byte view data.High-order single byte view data is referred to and will be more than in double byte view data
The data of 8 are splitted out, individually with a byte representation.Position single byte view data is referred in double byte view data
Low data is splitted out, and is individually used for a byte representation.High-order single byte view data and low level single byte view data
Digit artificially can be divided according to the digit of double byte view data.
Be converted in the receivable image data format of processor in double byte view data, the method for conversion has a lot,
For example the high-order view data of double byte view data and low level view data can be stored to BT.601 or BT.605
Relevant position, complete then view data form conversion.When data form is BT.601, on BT.601, there are Y location, Cr
High position data can be stored to the Y location of BT.601 by position, Cb positions, low data store to BT.601 Cr positions or
Person is the Cb positions of BT.601.Certainly, the conversion regime of its data form is not limited to mode mentioned above, and BT.601 and
BT.605 is a kind of more ripe image data format, will not be described here.
It is understood that double byte view data is converted to high-order single byte view data and low level individual character by FPGA
After section view data, high-order single byte view data and unit single byte view data can be made to be received by processor.
The processor 103 being connected with the field programmable gate array, for receiving the high-order single byte view data
And the low level single byte view data, by the high-order single byte view data and the low level single byte view data
Reconfigure as the double byte view data, and image procossing is carried out to the double byte view data.
The processor being connected with each other with FPGA by data signal line, receives the high-order single byte view data that FPGA is transmitted
And low level single byte diagram data, then the view data to receiving be reconstructed, obtain double byte view data, and can
Result to carry out process operation to the double byte view data for obtaining, needed for drawing.
It should be evident that the view data for receiving is view data after fractionation, it is not complete picture number
According to, comprising image information nor complete, need to reconfigure the view data for receiving for double byte view data,
Its double byte view data is consistent with the double byte view data that image capture device is collected.It is understood that
As the digit of the view data of image capture device is higher, and the data bits that processor can be received is that have certain restriction
, therefore need to be split during data transfer, view data is successfully received by processor.And process
After device receives the view data after splitting, in order to preferably include image information, need the view data of fractionation is recombinated
Reduction.The image information that the more view data of digit includes is more, and then the precision of processing result image can be made higher.
Image processing system be unable to do without memorizer to the storage and process of view data, and image real time transfer is obtained
Image shown.Therefore further, the image processing system provided by the embodiment of the present invention can also include：Double Data Rate
Synchronous DRAM, random access memory, embedded multi-media card and touch screen.
Image capture device is adopted by the image processing system provided by the embodiment of the present invention using field programmable gate array
The double byte view data of collection is converted to high-low-position single byte view data, and processor carries out weight to the view data for receiving
Structure, is reassembled into double byte view data, so as to image processing system is processed to double byte view data.It can be seen that, right
Double byte view data is split and is reconstructed, and is made the scope of the view data of collection larger, and then is improve image procossing system
The precision of system result.
As image capture device can be the one kind in multiple image capture devices, different image capture devices are corresponding
Collection picture data type and the transmission of view data, processing procedure have certain difference, therefore below will be to infrared measurement of temperature
Image processing system is introduced.
Fig. 2 is referred to, another kind of specific embodiment of the image processing system that Fig. 2 is provided by the embodiment of the present invention
System block diagram, the system include：
Infrared focal plane detector 201, for gathering 14 bit image data of infrared chart；
Infrared focal plane detector gathers the infrared image signal of target, and the digit of its infrared image signal is 14.Red
Include the first output port for output data clock including infrared focal plane detector on outer focus planardetector, for defeated
Go out synchronizing signal the second output port, for export the 14 bit image data low 7 bit image data the 3rd outfan
Mouthful, for export the 14 bit image data high 7 bit image data the 4th output port.
As the data bits that the digital camera interface of processor can be received is up to 8, therefore need 14 bit images
Data are split so that the view data after fractionation can be received by processor.14 bit image data can be split into 6
The view data and the view data of 8 of position, it is also possible to the view data that 14 bit image data are split into two 7, also may be used
So that 14 bit image data are split into other types of data combination.Now, the 3rd output port and the output of the 4th output port
View data digit also can be correspondingly different, will not be described here.
FPGA202, for 14 bit image data are entered row format conversion, obtains high-order single byte view data and low level
Single byte view data；
Infrared focal plane detector is transmitted the infrared image signal for being gathered to FPGA by low-voltage differential signal,
The 14 bit image data for receiving are encoded by FPGA, are completed form conversion, are obtained high-order single byte view data and low
Position single byte view data.FPGA is included for receiving the first receiving port of the data clock, first receiving port
It is connected with first output port by Data_Clk holding wires；For receiving the second receiving terminal of the synchronizing signal
Mouthful, second receiving port is connected with second output port by Data_Sync holding wires；Described low for receiving
3rd receiving port of 7 bit image data, the 3rd receiving port is by Data1_Out holding wires and the 3rd outfan
Mouth is connected；For receiving the 4th receiving port of the high 7 bit image data, the 4th receiving port passes through Data2_Out
Holding wire is connected with the 4th output port；For exporting the 5th output port of frame synchronizing signal；Synchronous for exporting row
6th output port of signal；The 7th output port for output pixel clock signal；For exporting the high-order single byte
View data and the 8th output port of the low level single byte view data.
It is understood that when the data bits for splitting is not two 7, its 3rd receiving port and the 4th receiving terminal
Mouth received data digit also can be correspondingly different, will not be described here.
14 bit image data can be converted to the data of BT.601 or BT.605 forms, for BT.601 forms
Data, have Y location, Cr positions, Cb positions on BT.601, can be by the high 7 bit image data storage of 14 bit image data to Y positions
The DATA [6 for putting:0] corresponding position, by the low 7 bit image data storage of 14 bit image data to Cb or Cr positions
DATA[6:0] corresponding position, the realization of its storing process can be realized by timing control program, and then complete low-voltage
Conversion of the differential signal to BT.601 data forms, realizes the fractionation to 14 bit image data.And BT.605 data forms turn
Change process similar with said process, here is no longer introduced in detail.It is, of course, also possible to 14 bit image data are converted to which
The data of its form, so that realize the fractionation to 14 bit image data.
It is understood that the difference of the data bits after splitting, the conversion of its BT.601 form or BT.605 forms
Transformation process also have fine distinction, will not be described here.
ARM hardware platform, including arm processor 203, Double Data Rate synchronous DRAM DDR204, is deposited at random
Access to memory RAM205, embedded multi-media card eMMC206 and touch screen LCD207, for high-order single byte view data
And low level single byte view data is recombinated, and to restructuring after view data show.
Arm processor includes that, for receiving the 5th receiving port of the frame synchronizing signal, the 5th receiving port leads to
Cross VSYNC holding wires to be connected with the 5th output port；For receiving the 6th receiving port of the line synchronising signal, described
6th receiving port is connected with the 6th output port by HREF signal line；For receiving the of the pixel clock signal
Seven receiving ports, the 7th receiving port are connected with the 7th output port by PCLK signal line；Described for receiving
High-order single byte view data and the 8th receiving port of the low level single byte view data, the 8th receiving port lead to
Cross DATA [7:0] holding wire is connected with the 8th output port.
Arm processor receives the data after FPGA conversions, then according to data set in advance by digital camera interface
Transformat is input into the source register of arm processor.When the data form for using is BT.601, can be passed with preliminary setting data
Defeated order is YCbYCr, then, when arm processor is received, the input sequence of YCbYCr is Y0Cb0Y1Cr0, now, ARM process
The view data for receiving is reconstructed by device, reconfigures the data of two neighboring byte, i.e., using word during reconstruct
The character of reception is converted to numerical value, such as Val=Y by symbol function<<7+Cb or Val=Y<<7+Cr, such as by Y0 and Cb0
Corresponding numerical value is combined, and can obtain 14 gathered bit image data.Certainly, the difference of data conversion format, which is heavy
The detailed process of structure is also not quite similar, and will not be described here.
After reconstruct draws 14 bit image data, 14 bit image data can be shown, it is possible to use 14 bit image numbers
According to the stably measured for carrying out target.And the view data of 8 is only able to display due to existing image display, therefore need 14
After bit image data are converted to 8 bit image data, then carry out gray scale and show, its 14 methods for turning 8 can be platform Nogata
Figure, or other display packings.
Refer to the signal timing diagram that Fig. 3 and Fig. 4, Fig. 3 export 14 bit image data for infrared focal plane detector, Fig. 4
For the sequential chart that arm processor receives view data.
The high 7 bit image data of 14 bit image data are individually exported, by the low 7 bit image data sheet of 14 bit image data
Solely export, it is possible to achieve the fractionation to 14 data.Data_Clk in Fig. 3 is data clock, and each data clock has 1 digit
According to being transmitted, Data_Sync is data synchronizing signal, and what wherein F was represented is frame synchronizing signal, and what L was represented is the synchronous letter of row
Number, Data1_Out outputs are low 7 data, and Data2_Out outputs are high 7 data.And by high 7 bit image number
According to being represented with corresponding character with low 7 bit image data respectively, more convenient when being recombinated so as to the later stage.In Fig. 4
What VSYNC was represented is frame synchronizing signal, and what HREF was represented is line synchronising signal, and what PCLK was represented is pixel clock signal, DATA
[7:0] represented is data signal, and wherein, each data signal is 8.
The infrared measurement of temperature image processing system provided by the embodiment of the present invention, the 14 bit image data that will be gathered using FPGA
Be converted to arm processor camera interface can receiving data form data, and then arm processor the data for receiving are carried out weight
Structure, obtains 14 bit image data, carries out temperature survey to 14 bit image data and image shows, improve infrared temperature measurement system
Temperature measurement accuracy, meanwhile, improve the temperature-measuring range of infrared measurement of temperature image processing system, improve infrared measurement of temperature image procossing system
The precision of the result of system.
Below image processing method provided in an embodiment of the present invention is introduced, image processing method described below with
Above-described image processing system can be mutually to should refer to.Fig. 5 is the stream of image-pickup method provided in an embodiment of the present invention
Journey schematic diagram, the method include：
Step 501：Image capture device obtains double byte view data, and the double byte view data is transmitted to scene
Programmable gate array；
It is pointed out that image capture device can be infrared band camera, or ultraviolet band camera, also may be used
Think visible light wave range camera.And the double byte view data for gathering, view data can be represented for 9～16 bits,
For example, double byte view data is 14 bit image data.
Step 502：The double byte view data is split into high-order single byte image by the field programmable gate array
Data and low level single byte view data, by the high-order single byte view data and the low level single byte view data
Transmit to processor；
It should be noted that when double byte view data be 14 when, can by 14 split into high 7 bit image data and
Low 7 bit image data, or split into high 6 bit image data and least-significant byte view data, also or other data bits
Combination.
In some embodiments of the invention, the split process of its data can be specially：When the double byte picture number
According to for 14 bit image data when, by the Y location of the high 7 bit image data storage to BT.601 of the double byte view data；Will
Cb the or Cr positions of the low 7 bit image data storage to the BT.601 of the double byte view data.By will be high-order and low
Position data are represented with the kinds of characters of BT.601 forms respectively, to realize the fractionation to double byte view data.Certainly, also may be used
To be converted to the view data of BT.605 forms, its process is similar to, and will not be described here.
Step 503：The processor is by the high-order single byte view data and the low level single byte view data
Reconfigure, obtain the double byte view data.
The view data of high-low-position is combined using processor, the double byte figure before being split after combination
As data.When double byte view data is 14, its process for reconstructing can be specially：Will be adjacent using character string function
The high 7 bit image data and the low 7 bit image data are reconfigured as the double byte view data；Wherein, described
Character string function is Val=Y<<7+Cb or Val=Y<<7+Cr.
Image capture device is adopted by the image processing method provided by the embodiment of the present invention using field programmable gate array
The double byte view data of collection is converted to high-low-position single byte view data, and processor carries out weight to the view data for receiving
Structure, is reassembled into double byte view data, so as to image processing system is processed to double byte view data.It can be seen that, right
Double byte view data is split and is reconstructed, and is made the scope of the view data of collection larger, and then is improve image procossing system
The precision of system result.
In this specification, each embodiment is described by the way of going forward one by one, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment same or similar part mutually referring to.For dress disclosed in embodiment
For putting, as which corresponds to the method disclosed in Example, so description is fairly simple, related part is referring to method part
Illustrate.
Professional further appreciates that, in conjunction with the unit of each example of the embodiments described herein description
And algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, in order to clearly demonstrate hardware and
The interchangeability of software, generally describes composition and the step of each example in the above description according to function.These
Function is executed with hardware or software mode actually, the application-specific and design constraint depending on technical scheme.Specialty
Technical staff can use different methods to realize described function to each specific application, but this realization should
Think beyond the scope of this invention.
The step of method described in conjunction with the embodiments described herein or algorithm, directly can be held with hardware, processor
Capable software module, or the combination of the two is implementing.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, depositor, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Above image processing system provided by the present invention and image processing method are described in detail.Herein
Apply specific case to be set forth principle of the invention and embodiment, the explanation of above example is only intended to help
Understand the method for the present invention and its core concept.It should be pointed out that for those skilled in the art, do not taking off
On the premise of the principle of the invention, some improvement and modification can also be carried out to the present invention, these improvement and modification also fall into this
In invention scope of the claims.
Claims (9)
1. a kind of image processing system, it is characterised in that include:
Image capture device, for gathering double byte view data；
The field programmable gate array being connected with described image collecting device, for being split as height by the double byte view data
Position single byte view data and low level single byte view data；
The processor being connected with the field programmable gate array, for receiving the high-order single byte view data and described
Low level single byte view data, the high-order single byte view data and the low level single byte view data are reconfigured
For the double byte view data, and image procossing is carried out to the double byte view data.
2. the system as claimed in claim 1, it is characterised in that also include Double Data Rate synchronous DRAM, random
Access memorizer, embedded multi-media card and touch screen.
3. system as claimed in claim 2, it is characterised in that described image collecting device is infrared focal plane detector, its
In, the double byte view data of the infrared focal plane detector collection is 14 bit image data；The infrared focus plane
Detector includes the first output port for output data clock, for exporting the second output port of synchronizing signal, be used for
Export the 3rd output port of the low 7 bit image data of the 14 bit image data, be used for exporting the 14 bit image data
4th output port of high 7 bit image data.
4. system as claimed in claim 3, it is characterised in that the field programmable gate array includes：
For receiving the first receiving port of the data clock, first receiving port is by Data_Clk holding wires and institute
State the first output port to be connected；
For receiving the second receiving port of the synchronizing signal, second receiving port by Data_Sync holding wires with
Second output port is connected；
For receiving the 3rd receiving port of the low 7 bit image data, the 3rd receiving port passes through Data1_Out signals
Line is connected with the 3rd output port；
For receiving the 4th receiving port of the high 7 bit image data, the 4th receiving port passes through Data2_Out signals
Line is connected with the 4th output port；
For exporting the 5th output port of frame synchronizing signal；For exporting the 6th output port of line synchronising signal；For defeated
Go out the 7th output port of pixel clock signal；For exporting the high-order single byte view data and the low level single byte
8th output port of view data.
5. system as claimed in claim 4, it is characterised in that the processor is arm processor, the arm processor bag
Include：
For receiving the 5th receiving port of the frame synchronizing signal, the 5th receiving port is by VSYNC holding wires and institute
State the 5th output port to be connected；
For receiving the 6th receiving port of the line synchronising signal, the 6th receiving port by HREF signal line with described
6th output port is connected；
For receiving the 7th receiving port of the pixel clock signal, the 7th receiving port is by PCLK signal line and institute
State the 7th output port to be connected；
For receiving the 8th receiving port of the high-order single byte view data and the low level single byte view data, institute
The 8th receiving port is stated by DATA [7:0] holding wire is connected with the 8th output port.
6. system as claimed in claim 1 or 2, it is characterised in that described image collecting device be visible light wave range camera or
Ultraviolet band camera or infrared band camera.
7. a kind of image processing method, it is characterised in that include：
Image capture device obtains double byte view data, and the double byte view data is transmitted to field-programmable gate array
Row；
The double byte view data is split into high-order single byte view data and low level by the field programmable gate array
Single byte view data, the high-order single byte view data and the low level single byte view data are transmitted to process
Device；
The high-order single byte view data and the low level single byte view data are reconfigured by the processor, are obtained
The double byte view data.
8. method as claimed in claim 7, it is characterised in that the field programmable gate array is by the double byte picture number
Include according to high-order single byte view data and low level single byte view data is split into：
When the double byte view data is 14 bit image data, by the high 7 bit image data of the double byte view data
Store to the Y location of BT.601；
Cb or Cr positions by the low 7 bit image data storage to the BT.601 of the double byte view data.
9. method as claimed in claim 8, it is characterised in that the processor by the high-order single byte view data and
The low level single byte view data is reconfigured, and obtaining the double byte view data includes：
Adjacent described high 7 bit image data and the low 7 bit image data are reconfigured as institute using character string function
State double byte view data；
Wherein, the character string function is Val=Y<<7+Cb or Val=Y<<7+Cr,<<Accord with for shift operation.
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