CN101742264A - NIOS II-based video monitoring method - Google Patents

Abstract

The invention provides an NIOS II-based video monitoring method, which belongs to the technical field of embedded video monitoring. The method comprises the following steps: a, converting an analogue video signal into a digital video signal and a synchronizing signal I; b, processing a video to output an RGB digital video signal and a synchronizing signal II; c, real time displaying, or storing or uploading the RGB digital video signal and the synchronizing signal II to an upper computer; and d, outputting an analogue RGB digital video signal to a VGA for displaying and outputting. The method solves the problems that the video monitoring method in the prior art cannot realize real-time monitoring, acquisition, storage and transmission at the same time. Therefore, the method has the advantages of high integration level and fast image data transmission speed.

Description

A kind of video monitoring method based on NIOS II

Technical field

The invention belongs to the embedded video monitoring technical field, be specifically related to a kind of video monitoring method,, gather, storage and transmission in order to realize the real time monitoring of video monitor based on NIOS II.

Background technology

Video monitor has obtained development rapidly in recent years, and range of application is constantly expanded.The video monitoring system of domestic use in the past mainly is an analogue system, to late 1990s, rapid raising along with network broadband, computer process ability and memory capacity, and the appearance of the various usable video information processing technologies, video monitor has entered digitized cybertimes from the analog video supervision, i.e. the digital video surveillance system.The digital video surveillance system becomes digital signal with the analog-signal transitions that video camera obtains, and is convenient to Computer Processing.When showing on the computer display or on monitor, showing the real-time activity image, vision signal can also be stored in the hard disk of computer, perhaps on network, transmit.

The embedded design framework of traditional video monitor is to use MCU+ASIC to realize the system hardware basis, is realized the operation of system by the different task of operating system scheduling.But the cutting of system hardware is relatively poor, and system optimization, upgrading are not very convenient.

MCU in traditional video monitoring method is system's master control maincenter, and general available high-grade single-chip microcomputer or other functional module of ARM. can realize with the chip of special use.The CVBS analog video signal is through the modulus conversion chip output digital video signal of video, the operation of MCU control whole system, digital video signal is exported the vision signal that needs through the Digital Video Processing chip, through overcompression storage (optional), be transferred to display terminal at last.Therefore, the hardware of traditional video monitor need realize that integrated level is not high with a plurality of elements, and system cost is higher, and in a single day system single board is made, and system's change, upgrading be difficulty relatively.

Existing video monitoring method based on the soft nuclear of NIOS II has been realized the combination of Video processing and NIOS II system.The CVBS analog video signal is through modulus conversion chip output digital video signal, and digital video signal is through video acquisition processing module and the control collaborative work of NIOS II system, and final output video signal is transferred to display terminal.But the video monitoring method of the soft nuclear of existing NIOS II only is confined to the simple process of video, and monitoring can not be satisfied the requirement of real time monitoring, collection, storage and the transmission of video monitor simultaneously in real time, does not also give full play of the characteristic based on the soft nuclear of NIOS II.

Summary of the invention

The object of the invention is to provide a kind of video monitoring method based on NIOS II, and the method that has solved the video monitor of prior art can't realize the problem of real time monitoring, collection, storage and transmission simultaneously.

The technical solution that the present invention is directed to above-mentioned technical problem is as follows:

A kind of method of the video monitor based on NIOS II, special character is that this method may further comprise the steps:

A. analog video signal is transported to the vision signal conversion, after the NIOS II control system control in video computing/system's control, this analog video signal is converted to digital video signal and synchronizing signal I;

B. the processing of Video processing in video computing/system's control with digital video signal and synchronizing signal I, output RGB digital video signal and synchronizing signal II;

C. RGB digital video signal and the synchronizing signal II with Video processing output directly transports to the video display signal conversion, is converted to the RGB digital video signal of simulation; Or with the RGB digital video signal of Video processing output and synchronizing signal II after the NIOSII control system is transported to SDRAM storage in storage/communication, transport to the RGB digital video signal that video display signal conversion is converted into simulation; Perhaps the RGB digital video signal of Video processing output and synchronizing signal II are transported to serial line interface in storage/communication earlier through NIOS II control system, after serial line interface is uploaded to host computer;

D. the RGB digital video signal of simulation being transported to VGA shows for output;

The implementation method of described step b may further comprise the steps:

[1.1] decoding: the BT656 vision signal is decoded as the YCbCr digital video signal of interlacing and the synchronizing signal I of interlacing by BT656;

[1.2] go interlacing: with the synchronizing signal I of the YCbCr digital video signal of interlacing and interlacing by go interlacing be converted to line by line the YCbCr digital video signal and synchronizing signal I line by line;

[1.3] video scaling: YCbCr digital video signal that will be line by line and synchronizing signal I line by line change RGB by video scaling to YCbCr, are converted to the RGB digital video signal;

[1.4] sequential allotment: RGB digital video signal and NIOS II configurable clock generator signal are allocated as the clock signal that RGB digital video signal, synchronizing signal II and confession VGA show by VGA sequential generation blanking;

[1.5] video scaling: according to the VGA sequential synchronizing signal II of output, the configuration zooming parameter that NIOS II control system provides, the synchronizing signal I that goes interlacing to export take place, will go the YCbCr digital video signal line by line of interlacing output to be scaled the YCbCr digital video signal by video scaling;

[1.6] format digital video signal conversion: the YCbCr digital video signal of convergent-divergent is converted to the RGB digital video signal by YCbCr commentaries on classics RGB;

[1.7] sequential allotment: the clock signal that RGB digital video signal and NIOS II configurable clock generator signal are allocated as RGB digital video signal, synchronizing signal II and show for VGA by VGA sequential generation blanking; The clock signal one tunnel that RGB digital video signal, synchronizing signal II and confession VGA show is transported to the MUX selection, and another road is transported to MUX through NIOS II control system and is selected;

[1.8] signal is selected: the RGB digital video signal that the generation of VGA sequential is exported, synchronizing signal II and the clock signal that supplies VGA to show are directly selected to export through MUX and are supplied the VGA demonstration, or RGB digital video signal, the synchronizing signal II of output takes place the VGA sequential and supply the clock signal of VGA demonstration to select output to supply the VGA demonstration through MUX again after NIOS II control system is controlled;

The implementation method of described step c may further comprise the steps:

[2.1] NIOS II CPU control acquisition controlling nuclear is transferred to SDRAM control nuclear and serial line interface control nuclear with the data of Video processing output through DMA control nuclear;

[2.2] data in the NIOS II CPU control SDRAM control nuclear are deposited to SDRAM through DMA control nuclear;

[2.3] data after NIOS II CPU control VGA control nuclear will be changed export Video processing to;

[2.4] NIOS II CPU control SDRAM control nuclear is delivered to VGA control nuclear with data through DMA control nuclear;

[2.5] transfer of data during NIOS II CPU control serial line interface control nuclear is examined acquisition controlling is to host computer.

Acquisition controlling nuclear in the above-described step [2.1] comprises acquisition module and FIFO transport module, acquisition module in the NIOS II CPU control acquisition controlling nuclear is gathered the data of Video processing output, and data are write FIFO transport module in the acquisition controlling nuclear.

VGA control nuclear in the above-described step [2.5] comprises VGA timing sequencer, FIFO memory module.

The specific implementation method of above-described step [2.2] is:

(1) initialization DMA control nuclear

Internal register according to designing requirement configuration DMA control nuclear;

(2) enable DMA control nuclear

DMA control nuclear is enabled to judge that DMA control nuclear energy does not transmit data;

(3) storage

(3.1) judge whether the FIFO transport module is empty

If the FIFO transport module is empty, then carries out DMA control nuclear and wait for;

If the FIFO transport module is non-NULL, then DMA control nuclear control FIFO transport module with image data storage to SDRAM;

(3.2) judge whether the view data that is stored to SDRAM is a frame, has not deposited when frame data, then is back to step (3.1);

(3.3) deposited when frame data, judged whether that next frame data etc. are to be stored; When not having next frame data etc. to be stored, then finish storage;

(3.4) when next frame data etc. are to be stored, judge whether SDRAM is filled with, if SDRAM is not filled with and then is back to step; If SDRAM has stored full, then end data storage.

The specific implementation method of above-described step [2.3] is:

1) initialization DMA control nuclear

Internal register according to designing requirement configuration DMA control nuclear;

2) enable DMA control nuclear

DMA control nuclear is enabled to judge DMA control nuclear energy transmission data;

3) using DMA control nuclear interrupts view data is write the FIFO memory module

3.1) judge whether the FIFO memory module is full:

If the FIFO memory module, is then carried out DMA control nuclear for full and is waited for;

If the FIFO memory module is non-full, then DMA control nuclear control FIFO memory module reads the data among the SDRAM and it is write the FIFO memory module;

3.2) judge whether refresh the FIFO memory module, do not write when frame data, then be back to step 3.1);

3.3) write when frame data, refresh the FIFO memory module, judged whether that next frame data etc. are to be written; When next frame data etc. are to be written, then be back to step 1);

3.4) when not having next frame data etc. to be written, judge whether stop in the FIFO memory module, to write data; When not stopping in the FIFO memory module, writing data, be back to step 1), when stopping in the FIFO memory module, writing data, then finish to write data to the FIFO memory module.

The implementation method of above-described step [2.5] is: A) initialization string line interface (UART) control nuclear; B) data and the signal that parallel data and conversion of signals are serial is uploaded to host computer.

Advantage of the present invention is as follows:

1. integrated level height.

The present invention is integrated in one Video processing and NIOS II control system and forms programmable system (SOPC) on the sheet, need not to introduce independent chip.

2. be easy to upgrade.

The present invention adopts programmable system on the sheet (SOPC), is easy to safeguard and upgrade.

3. applicability is strong.

The present invention puies forward exportable different VGA standard can pass through parameter configuration

4. image data transmission rate is fast.

NIOS II cpu clock of the present invention is up to 50MHZ, and transmitting video data speed is fast.

5. feature richness.

The present invention realized vedio data in real time, gather, storage and transmission, and control each functional module collaborative work by NIOS II control system.

Description of drawings

Fig. 1 is existing video monitoring method block diagram;

Fig. 2 is a Video processing schematic block diagram of the present invention;

Fig. 3 is the capable signal timing diagram of BT656 of vision signal conversion output of the present invention;

Fig. 4 is a BT656 decoding interface schematic diagram of the present invention;

Fig. 5 is a BT656 decoding interface sequential chart of the present invention;

Fig. 6 is the present invention's idol field sync signal 1 sequential chart;

Fig. 7 is strange field sync signal 1 sequential chart of the present invention;

Fig. 8 is dual port RAM work monitoring oscillogram of the present invention;

Fig. 9 removes interlacing interface schematic diagram for the present invention;

Figure 10 is a YCbCr output timing diagram of the present invention;

Figure 11 is a video scaling interface schematic diagram of the present invention;

Figure 12 is the schematic flow sheet of video scaling of the present invention;

Figure 13 calculates the position view of interpolation point X for one embodiment of the invention;

Figure 14 is one embodiment of the invention schematic diagram;

Figure 15 is the amplitude-frequency response schematic diagram of the value of a in the non-linear interpolation function Lanczos formula of one embodiment of the invention;

Figure 16 changes the interface schematic diagram of RGB for YCrCb of the present invention;

Figure 17 is a VGA sequential generation interface schematic diagram of the present invention;

Figure 18 is a line synchronizing signal IIVGA sequential chart of the present invention;

Figure 19 is a field sync signal IIVGA sequential chart of the present invention;

Figure 20 is a NIOS II control system structural representation of the present invention;

Figure 21 is a NIOS II hardware connection layout of the present invention;

Figure 22 is SDRAM control nuclear structure schematic diagram of the present invention;

Figure 23 is DMA control nuclear structure schematic diagram of the present invention;

Figure 24 is serial line interface control nuclear structure schematic diagram of the present invention;

Figure 25 is an acquisition controlling nuclear structure schematic diagram of the present invention;

Figure 26 for Avalon bus of the present invention from port reads transmission time sequence figure;

Figure 27 is FIFO transport module simulation waveform figure of the present invention;

Figure 28 is VGA control nuclear structure schematic diagram of the present invention;

Figure 29 is that stream mode of the present invention is from the port write transmission time sequence;

Figure 30 is a VGA timing sequencer analogous diagram of the present invention;

Figure 31 is the schematic flow sheet of SDRAM storage data of the present invention;

Figure 32 is an image flow for displaying schematic diagram of the present invention.

Figure 33 is a UART transfer process schematic diagram of the present invention.

Embodiment

The method of the video monitor based on NIOS II provided by the invention, referring to Fig. 1, the specific implementation method is as follows:

A. analog video signal is transported to vision signal conversion 1 (ADV7181B), after NIOS II control system 22 controls in video computing/system's control 2, this analog video signal is converted to digital video signal and synchronizing signal I;

B. the processing of Video processing 21 in video computing/system's control 2 with digital video signal and synchronizing signal I, output RGB digital video signal and synchronizing signal II;

C. RGB digital video signal and the synchronizing signal II with Video processing 21 outputs in video computing/system's control 2 directly transports to video display signal conversion 4 (DAV7213), is converted to the RGB digital video signal of simulation; Perhaps with the RGB digital video signal of Video processing 21 output and synchronizing signal II after NIOS II control system 22 is transported to SDRAM32 storage in storage/communication 3, transport to video display signal and change the RGB digital video signal that 4 (DAV7213) are converted to simulation; Perhaps just the RGB digital video signal of Video processing 21 output and synchronizing signal II transport to serial line interface 31 in storage/communication 3 earlier through NIOS II control system 22, after serial line interface 31 is uploaded to host computer;

D. the RGB digital video signal of simulation is transported to VGA and shown 5 for output.

Be elaborated as follows below in conjunction with the specific implementation method of accompanying drawing step b and step c:

[1.1] decoding: BT656 vision signal and synchronizing signal I are the NIOS II control system 21 control of video conversion of signals 1 (ADV7181B) in video computing/system's control 2, the NTSC/PAL/S-Video analog video signal is converted to digital video signal, carry out video decode, 8 the BT656 vision signals of standard and the synchronizing signal I of output handle for the BT656 decoding 211 of rear end.

BT656 decoding 211 will be observed the YCbCr digital video signal that BT.656 sequential and data format obtain interlacing, the output signal of synchronizing signal I, and wherein the YCbCr digital video signal is concrete can be 4: 4: 4,4: 4: 2 etc. YCbCr digital video signal.

Referring to Fig. 3, vision signal conversion 2 (ADV7181B) export the capable signal sequence of BT656, " 80 10 ... " expression current video signal is in the horizontal blanking stage." FF 0000 XY " is the time reference code.As the bit6=' 1 ' of XY, be EAV (effective video end), bit6=' 0 ', be SAV (effective video begins) Cb Y Cr Y ... be effective video signal (taking 1440 CCL).XY time reference code is referring to table 1.

Table 1

Data bit number	First byte	Second byte	The 3rd byte	Nybble
					??7(MSB)	??1	??1	??1	??1

Data bit number	First byte	Second byte	The 3rd byte	Nybble
					??6	??1	??1	??1	??F
??5	??1	??1	??1	??V
					??4	??1	??1	??1	??H
??3	??1	??1	??1	??P3
					??2	??1	??1	??1	??P2
??1	??1	??1	??1	??P2
					??0	??1	??1	??1	??P0

Everybody is defined as nybble: F=" 0 " for Field 0, F=" 1 " for Field 1; V=" 1 " during vertical blanking; H=" 0 " at SAV H=" 1 " at EAV; $\mathrm{<figure-callout\; id="3"\; label="P"\; filenames="H2009102544038E00011.png"\; state="\{\{state\}\}">P</figure-callout>}3=V\&CircleTimes;H;$ $\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="H2009102544038E00031.png,H2009102544038E00034.png"\; state="\{\{state\}\}">P</figure-callout>}2=F\&CirclePlus;H;$ $\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="H2009102544038E00034.png"\; state="\{\{state\}\}">P</figure-callout>}1=F\&CirclePlus;V;$ $\mathrm{<figure-callout\; id="0"\; label="P"\; filenames="H2009102544038E00014.png,H2009102544038E00021.png"\; state="\{\{state\}\}">P</figure-callout>}0=F\&CirclePlus;V\&CirclePlus;H.$

The input signal of BT656 decoding 211 is BT656 vision signal, synchronizing signal I of vision signal conversion 1 (ADV7181B) output, output be YCbCr digital video signal and synchronizing signal I.The BT656 main interface of decoding is a FPGA 27MHZ clock referring to Fig. 4: Clk_bt656; BT656_in[7:0]: the BT656 vision signal of vision signal conversion (ADV7181B) output; The line synchronizing signal I that Hsync1:BT656 solves; The field sync signal I that Vsync1:BT656 solves; The valid data signal of Data_valid1:BT656 decoding output; The field mark signal of Field1:BT656 decoding output, 0 represents the idol field, strange of 1 representative; Y_data1, Cb_data1, the YCbCr signal of Cr_data1:BT656 decoding output.BT656 decoding interface sequential is referring to Fig. 5.

[1.2] go interlacing: the input signal that goes interlacing 212 is the YCbCr digital video signal and the synchronizing signal I of BT656 decoding 211 interlacing that obtain.Be to save resource, go interlacing to adopt capable commentaries on classics of duplicating method line by line, promptly strange, the every row of even number line duplicates a line output more.Like this, strange, even field each can be combined into frame output.

Idol field sync signal I sequential and strange field sync signal I sequential are respectively referring to Fig. 6, Fig. 7.

Because want complete each line data that duplicates, and the data that will preserve next line, can adopt dual port RAM to come deposit data.Because of the BT656 digital video signals of vision signal conversion 2 samplings and the transmission rate of synchronizing signal I are 13.5MHz, and go the YCrCb digital video signal of interlacing 212 outputs and the transmission rate of synchronizing signal I is 27MHz, go interlacing 211 to adopt dual port RAM, go interlacing 212 each line data to read twice, reply frequency finishes being interlaced to the conversion of lining by line scan simultaneously.

Go interlacing 212 to adopt dual port RAM, but buffer memory one field data.The read-write of going interlacing 212 is to carry out simultaneously.Dual port RAM work monitoring waveform is referring to Fig. 8, and address_a is the write address counting, and the address counting clock is that 13.5M. enables the address counting and is TD_HS, and low level is effective; Address_b is for reading address counting, and the address counting clock is that 27M. enables the address counting and is BLANK, and high level is effective.From signal waveform, address_a and address_b counting equate to be 720, meet design requirement.Simultaneously whenever write one and can accurately read two field data, do not have deviation, adhere to specification fully.

Go interlacing 212 interfaces referring to Fig. 9, Hsync2 removes the line synchronizing signal I line by line of interlacing 212 outputs; Vsync2 removes the field sync signal I line by line of interlacing 212 outputs; Data_valid2 removes the valid data signal of interlacing 212 outputs; Y_data2, Cb_data2, Cr_data2 remove the YCbCr digital video signal of interlacing 212 outputs.

Complete YCbCr output timing is referring to Figure 10, and when data_valid2 was high level, YCrCb output effective video data during for low level, were exported the blanking data, Y output " 0x00 ", Cr, Cb output " and 0x80 ".

[1.3] video scaling: line by line YCbCr digital video signal and synchronizing signal I are line by line changeed RGB214 by video scaling 213 to YCbCr, be converted to the RGB digital video signal;

[1.4] sequential allotment: RGB digital video signal and NIOS II configurable clock generator signal by the VGA sequential clock signal that 215 blankings are allocated as RGB digital video signal, synchronizing signal II and show for VGA are taken place;

[1.5] video scaling: video scaling 213 according to NIOSII configuration zooming parameter, by the synchronizing signal I line by line that goes interlacing 212 outputs and again the VGA sequential synchronizing signal II of 215 outputs take place, to carrying out convergent-divergent by the YCbCr digital video signal that goes interlacing 212 outputs.

The function of video scaling 213 is that the video level of input and/or vertically scale are become to show the form that needs.For example YCbCr digital video signal and the synchronizing signal I (720X480 or 720X576) with input is reduced into YCbCr digital video signal and synchronizing signal II (640X480).The interface of video scaling 213 is referring to Figure 11, and wherein Clk_27 is the 27MHZ of a system clock; Clk_vga is the VGA of a system read clock; The synchronizing signal II for the VGA demonstration of 215 outputs takes place in Hsync_vga, vsync_vga for the VGA sequential; Y_data, Cb_data, Cr_data are the video data signal through video scaling 213 outputs.

The following method of video scaling 213 concrete application realizes that its schematic flow sheet is referring to Figure 12.

1) video scaling 213 calculates the interpolation step-length according to the synchronizing signal I and the synchronizing signal II of input, and calculate: interpolation step-length=synchronizing signal I/ synchronizing signal II gets the interpolation step-length.

1.1) determine new pixel X location of interpolation according to the interpolation step-length.

For example the I of synchronizing signal line by line of input video convergent-divergent 213 is 720X480, and the synchronizing signal II of input video convergent-divergent is 640X480, then can get pantograph ratio (640*480)/(720*480)=0.889.Determine with one or more valid pixels to be a pixel unit according to the convergent-divergent precision.For example each valid pixel is a pixel unit, obtains needing the step-length of interpolation to be so (720x480)/(640*480)=1.125.

Referring to Figure 13, be 1 with the step-length of original each effective pixel points, the interpolation point step-length 1.125,2.25,3.375 that is then produced ... be the position that interpolation point X is promptly wanted in the position of new pixel, see illustrated imaginary point.Imaginary point indicates to produce the one-row pixels point of 640X480, and real point is represented the one-row pixels point of original 720X480.

2) be square formation formula zone with 16 original image vegetarian refreshments, form X1 ~ X16 pixel, the pixel value that obtains the X position is non-linear interpolation x_lans as a result.

The non-linear interpolation that 16 pixels around the current pixel point obtain current pixel point is x_lans as a result.Be square formation for example, form X1 ~ X16 pixel, obtain the pixel value of X position, referring to Figure 14 with 16 original image vegetarian refreshments.

The specific implementation method is as follows:

2.1) the row zoom factor para_v of calculating square formation, the capable zoom factor para_h of square formation,

Because the non-linear interpolation function frequency spectrum has very wide pass-band performance, can obtain the less interpolation result of high frequency loss.Therefore use the Lanczos non-linear interpolation function here, the form by leggy interpolation and look-up table realizes that the value of table can dispose by software.

In look-up table, adopt 128X4 interpolation, promptly 128 positions according to the function symmetry, can obtain 256 sampling locations.So precision can reach 1/256 location of pixels.

Following formula is the Lanczos non-linear interpolation function.

The amplitude-frequency response of the value of a is referring to Figure 15 in the Lanczos formula, here adopt leggy interpolating function mode, get the interpolation point interpolation coefficient para_v1 of four some correspondences on every side, para_v2, para_v3, para_v4 is a unit 1 at interval between each point of these four points, scope is-2＜x＜2 therefore to get a=2.

Example is some values (0/256,1/256,2/256 wherein if get the x location of interpolation ... 255/256,256/256),, obtains the corresponding coefficient of four interpolating pixel points and be para_v1, para_v2, para_v3, para_v4 respectively according to following formula.

para_v1＝sinc(-1-x)*sinc((-1-x)/2)；

para_v2＝sinc(-x)*sinc(-x/2)；para_v3＝sinc(1-x)*sinc((1-x)/2)；

para_v4＝sinc(2-x)*sinc((2-x)/2)；

2.2) determine look-up table

With step 2.1) row zoom factor para_v, the capable zoom factor para_h of square formation of the square formation of gained write look-up table.

Obtain look-up table referring to table 2:

Location of interpolation x	??para_v1	??para_v2	??para_v3	??para_v4
					??0/256	??0.000	??1.000	??0.000	??0.000
??1/256	??0.002	??1.000	??0.003	??0.000
					??2/256	??-0.005	??1.000	??0.005	??-0.000
??3/256	??-0.007	??1.000	??0.008	??-0.000
					??...	??...	??...	??...	??...
??129/256	??0.063	??0.568	??0.579	??0.064
					??130/256	??0.062	??0.562	??0.584	??0.065
??...	??...	??...	??...	??...
					??256/256	??-0.000	??0.000	??1.000	??0.000

Because interpolating function has even symmetry, can find out from table 2 that therefore the interpolation coefficient of skew x from 129/256 to 256/256 and skew x from 127/256 to 0/256 has symmetric relation, so look-up table coefficient that only need from 0/256 to 128/256 gets final product.

When tabling look-up, such as, when the vertical location of interpolation of X was 0, promptly deviation post was 0/256, by look-up table, can obtain 4 interpolation coefficients and be [0,1,0,0].When the vertical location of interpolation of X was 7/256, promptly deviation post was 7/256, by look-up table, can obtain 4 interpolation coefficients and be [0.016,0.998,0.018,0].

In like manner, can pass through horizontal-shift, tabling look-up obtains the interpolation coefficient of horizontal direction.

2.3) finding step 2.2) and in the row zoom factor para_v of square formation of gained look-up table, calculate normalized coefficient with sum1 and every row vertical to coefficient with definite every row vertically to coefficient.

Normalized coefficient with sum1 be the row zoom factor para_v sum of square formation;

Calculate:

Vertically to coefficient X_m1=(X1*para_v1+X5*para_v2+X9*para_v3+X13*para_v4)/sum1

Vertically to coefficient X_m2=(X2*para_v1+X6*para_v2+X10*para_v3+X14*para_v4)/sum1

Vertically to coefficient X_m3=(X3*para_v1+X7*para_v2+X11*para_v3+X15*para_v4)/sum1

Vertically to coefficient X_m4=(X4*para_v1+X8*para_v2+X12*para_v3+X16*para_v4)/sum1

Then every row vertically to coefficient.

2.4) finding step 2.2) and in the gained look-up table square formation capable zoom factor para_h calculated level to normalized coefficient with sum2 with the non-linear interpolation of definite final X position X_lans as a result.

Level to normalized coefficient with sum2 be the capable zoom factor para_h sum of square formation.

Calculate: X_lans=(X_m1*para_h1+X_m2*para_h2+X_m3*para_h3+X_m4*para_h4)/sum2 gets non-linear interpolation X_lans as a result.

2.5) for the smoothness of control of video interpolation point, need carry out overshoot and dash control down interpolation result X.The specific implementation method is:

2.5.1) choose the minimum value XL_min of the original image vegetarian refreshments position of the maximum XL_max of original image vegetarian refreshments position of square formation adjacent column and square formation adjacent column.

That is: the maximum XL_max=MAX of original image vegetarian refreshments position (X6, X7, X10, X11)

The minimum value XL_min=MIN of original image vegetarian refreshments position (X6, X7, X10, X11)

2.5.2) select n position overshoot control thresholding 0T_ctrl and n position to dash control thresholding UT_ctrl down according to designing requirement, its scope is 0 ~ 63.

2.5.3) judge overshoot and dash control down to determine non-linear interpolation X_lans1 as a result.

2.5.3.1) will be through step 2.4) non-linear interpolation of gained is after the maximum XL_max of X_lans and original image vegetarian refreshments position compares as a result, non-linear interpolation X_lans1 is as a result determined in the control overshoot.

2.5.3.2) will be through step 2.4) non-linear interpolation of gained is after the minimum value X_min of X_lans and original image vegetarian refreshments position compares as a result, descends to dash control, determines non-linear interpolation X_lans1 as a result.

If X_lans＞X_max, then X_lans1=X_lans-(X_lans-X_max) * 0T_ctrl/64;

If (X_lans＜X_min), then X_lans1=X_lans+ (X_min-X_lans) * UT_ctrl/64

Final interpolation result X_lans1 will be limited in 0 ~ 255, if X_lans1＞255 definite non-linear interpolation as a result the value of X_lans1 be 255; If X_lans1＜0 definite non-linear interpolation value of X_lans1 as a result is 0.

3) by linear interpolation method, the linear interpolation that 16 pixels around the current pixel point obtain current pixel point is x_bi as a result.

The specific implementation method is as follows:

3.1) calculate:

The level left side point LL1=[X1*N_ctrl1+X2* (64-N_ctrl1) of interpolation]/64

The right point of the level of interpolation LR1=[X4*N_ctrl1+X3* (64-N_ctrl1)]/64

The level left side point LL2=[X5*N_ctrl1+X6* (64-N_ctrl1) of interpolation]/64

The right point of the level of interpolation LR2=[X8*N_ctrl1+X7* (64-N_ctrl1)]/64

The level left side point LL3=[X9*N_ctrl1+X10* (64-N_ctrl1) of interpolation]/64

The right point of the level of interpolation LR3=[X12*N_ctrl1+X11* (64-N_ctrl1)]/64

The level left side point LL4=[X13*N_ctrl1+X14* (64-N_ctrl1) of interpolation]/64

The right point of the level of interpolation LR4=[X16*N_ctrl1+X15* (64-N_ctrl1)]/64

Wherein to choose scope be 0 ~ 63 to n position thresholding N_ctrl1, the horizontal left-right dots of interpolation.

3.2) calculate:

Linear interpolation point X_l1=LL1* (1-x_offset)+LR1*x_offset,

Linear interpolation point X_l2=LL2* (1-x_offset)+LR2*x_offset,

Linear interpolation point X_l3=LL3* (1-x_offset)+LR3*x_offset,

Linear interpolation point X_l4=LL4* (1-x_offset)+LR4*x_offset,

Wherein x_offset be level to side-play amount, the linear interpolation point.

3.3) calculate:

The upward some X_UP=[X_l1*N_ctrl1+X_l2* (64-N_ctrl1) of vertical direction]/64,

The following some X_DN=[X_l3*N_ctrl1+X_l4* (64-N_ctrl1) of vertical direction]/64,

Some X_UP on the vertical direction and following some X_DN of vertical direction.

3.4) calculate:

Linear interpolation is X_bi=X_UP* (1-y_offset)+X_DN*y_offset as a result, and wherein y_offset is for vertically to side-play amount.

Get linear interpolation X_bi as a result.

Under noise situations, linear interpolation can obtain interpolation effect preferably, because its low-frequency filter characteristics makes it that function of good noise reduction be arranged.

4) determine final interpolation result by adaptive judgement:

With linear interpolation as a result X_bi and non-linear interpolation as a result X_lans1 compare to determine final interpolation result.

4.1) choose the maximum Ymax of the position of former 16 pixels, choose the minimum value Ymin of the position of former 16 pixels.

4.2) difference and the n position thresholding N_ctrl2 of the minimum value Ymin of the position of the maximum Ymax of the position of former 16 pixels and former 16 pixels compared, determine interpolation result.

If the minimum value Ymin＞n position thresholding N_ctrl2 of the position of former 16 pixels of maximum Ymax-of the position of former 16 pixels, then interpolation result is linear interpolation X_bi; If the minimum value Ymin＜n position thresholding N_ctrl2 of the position of former 16 pixels of maximum Ymax-of the position of former 16 pixels, then interpolation result is non-linear interpolation X_lans as a result, and wherein the span of n position thresholding N_ctrl2 is 0 ~ 63.

[1.6] format digital video signal conversion: transporting to YCbCr by the YCbCr digital video signal of the convergent-divergent of video scaling 213 outputs changes RGB214, changes the RGB digital video signal that obtains after RGB 214 conversions through YCbCr and transports to the VGA sequential and take place 215.

YCrCb changes the RGB214 interface referring to Figure 16.Y_data2 wherein, Cb_data2, Cr_data2 are the data from video scaling output; Y_data2 refers to brightness, and Cb_data2 refers to blue component, and Cr_data2 refers to red component.Output is the RGB data of having changed, and R_data refers to redness, and G_data refers to green, and B_data refers to blueness.

Used conversion square formation is shown below:

$\left[\begin{array}{c}R\\ G\\ B\end{array}\right]=\left[\begin{array}{ccc}1& 1.403& 0\\ 1& -0.714& -0.344\\ 1& 0& 1.770\end{array}\right]\&times;\left[\begin{array}{c}Y\\ \mathrm{Cr}\\ \mathrm{Cb}\end{array}\right]$

R＝Y+1.403Cr＝Y+Cr+0.403Cr＝Y+Cr+0x19CCr

For convenience of calculation is expressed as decimal 0.403 R that 10 hexadecimal calculates that moves to right to 0x19C, G, B at last also will be by correcting, because of some bad value makes rgb value greater than 1023 or less than 0.When greater than 1023 the time, correcting rgb value is 1023, less than 0 o'clock, and RGB assignment 0.RGB can represent with 10 binary systems like this.

[1.7] sequential is allocated: RGB digital video signal and NIOS II configurable clock generator signal are imported VGA sequential generation 215 and are allocated, and synchronizing signal II, RGB digital video signal of exporting after VGA sequential generation 215 allotments and the clock signal one tunnel that supplies the VGA demonstration are transported to the MUX selection; Another road is transported to MUX through NIOS II control system 22 and is selected 216; The synchronizing signal II of output feeds back to video scaling 213 after 215 blankings allotment takes place the VGA sequential simultaneously.

VGA sequential generation 215 produces the sequential that VGA show to be needed, and is synchronous with the output valid data, the capable field sync signal II of the VGA video data of the 640*480 of generation standard.

General computer VGA (640 * 480, the 60Hz) signal sequence of picture format, its Dot Clock DCLK is 25.175MHz, field frequency is 59.94Hz.Field duration is 16.683ms, and every has 525 row, the effective display line of 480 behaviors wherein, 45 behavior field blanking intervals.Every of field sync signal Vs has a pulse, and the low level width of this pulse is 63 μ s (2 row).Vertical blanking period comprises field synchronization time, field blanking crop (13 row), field blanking back porch (30 row), totally 45 row.Line period is 31.78 μ s, and every display line comprises 800 points, and wherein 640 is to show that effectively be row latent period (non-display area) at 160.The every row of line synchronizing signal Hs has a pulse, and the low level width of this pulse is 3.81 μ s (i.e. 96 DCLK); Row latent period comprises capable lock in time, horizontal blanking crop (19 DCLK) and horizontal blanking back porch (45 DCLK), totally 160 Dot Clocks.Composite blanking signal is the logical AND of horizontal blanking signal and field blanking signal, is high level in effective demonstration phase composite blanking signal, and it is a low level at non-display area.

215 interfaces take place referring to Figure 17 in the VGA sequential.Wherein Clk_vga is the read clock of VGA, also is the clock of module.R_data1, g_data1, b_data1 is for exporting to the final data of video display signal conversion 4 (DAV7213).Hsync, vsync is the synchronizing signal II that exports to video display signal conversion 4 (DAV7213), also is the signal to video scaling 213 inputs.

The sequential that line synchronizing signal II (hsync) produces is referring to Figure 18, and wherein first trailing edge to the second trailing edge is a complete cycle, totally 800 pixels, and wherein effective pixel points is 640.

The sequential that field sync signal II (vsync) produces is a complete cycle referring to first trailing edge to the second of Figure 19 trailing edge, and totally 525 row wherein effectively look like 480 of behaviors.

[1.8] signal is selected: the RGB digital video signals, synchronizing signal II of 215 outputs take place and directly select 216 outputs to show for VGA through MUX for the clock signal that VGA shows in the VGA sequential, or the RGB digital video signals, synchronizing signal II of 215 outputs take place the VGA sequential and select 216 outputs to show for VGA through MUX for the clock signal that VGA shows again after 22 controls of NIOS II control system.

Referring to Figure 20, NIOS II control system 22 mainly is made of NIOS II CPU224, acquisition controlling nuclear 225, SDRAM control nuclear 221, DMA control nuclear 223, serial line interface control nuclear 222 and VGA control nuclear 226.

In SOPC, add the User Defined peripheral hardware, simplified the design of hardware.The hardware of the NIOS II control system 22 that generates in SOPCBuilder connects referring to Figure 21.Wherein Cpu_0 is NIOSII CPU; Tri_state_bridge is the Avalon bus; Timer0, timer1 are timer; Sdram is a SDRAM control nuclear; Button_pio, switch_pio are input/output end port; Dma is a DMA control nuclear; UART_0 is serial line interface (UART) control nuclear; Vga is a VGA control nuclear, and to_sdram is an acquisition controlling nuclear.

The control method of step c mainly may further comprise the steps:

[2.1] NIOSIICPU224 control acquisition controlling nuclear 225 is transferred to SDRAM control nuclear 221 and serial line interface control nuclear 222 with the data of Video processing 21 outputs through DMA control nuclear 223;

[2.2] data in the NIOSIICPU224 control SDRAM control nuclear 221 are deposited to SDRAM32 through DMA control nuclear 223;

[2.3] data after NIOSIICPU224 control VGA control nuclear 226 will be changed export Video processing 21 to;

[2.4] NIOSIICPU224 control SDRAM control nuclear 221 is delivered to VGA control nuclear 226 with data through DMA control nuclear 223;

[2.5] NIOSIICPU224 control serial line interface control nuclear 222 with the transfer of data in the acquisition controlling nuclear 225 to host computer.

Be explained in detail for the relevant control nuclear in the NIOS II control system 22 below in conjunction with accompanying drawing.

The clock of SDRAM chip clock and AVALON bus interface drives and must as other Synchronization Design, must guarantee the address synchronously, and data, control signal must keep stable when arriving at the clock edge.So must control stabilizing clock between nuclear 221 and the SDRAM chip at SDRAM with phase-locked loop pll.In low-speed clock, the clock relative time delay is less, and phase-locked loop pll can.SDRAM control nuclear 221 interface schematic diagrames are referring to Figure 22.

AVALON is the user interface part of SDRAM control nuclear 221 from interface.When visiting from interface, SDRAM control nuclear 221 whole host-host protocols are transparent to the user.Can control the address (Adress) of AVALON by control logic from interface, data (Data), wait for request (Waitrequest), reading of data effectively (Readdatavalid) signal realized SDRAM chip read-write operation afterwards via the sdram interface adaptation processing.

Clock source (Clock source) is NIOS II control system 22 clock 50Mhz, adjusts by the phase-locked loop pll phase place, produces the SDRAM control nuclear clock (controllerclock) of 50MHZSDRAMclock (SDRAM chip clock) and 50MHz out of phase.

In 22 designs of NIOS II control system, adopt the data manipulation of DMA control nuclear transmission SDRAM, video data is transferred to SDRAM control nuclear 221 by the AVALON bus by dma mode.By SDRAM control nuclear 221 video data is write SDRAM32 in batches.

DMA control nuclear 223 is realized the transmission of batch data from interface control by AVALON.Main read port (READ MASTER PORT) connects the read data source module, and main write port (WRITE MASTER PORT) connects write data purpose module.DMA control is endorsed with very effective transmission data, as long as configure DMA control nuclear internal register, connects module for reading and writing, the transmission data that DMA control nuclear just can batch.When the DMA control nuclear end of transmission, DMA control nuclear 223 sends interrupt request singal, and NIOSIICPU224 can respond it.DMA control nuclear 223 interface schematic diagrames are referring to Figure 23.

The DMA control nuclear 223 that the video data of gathering is transferred to by the AVALONG bus port is controlled nuclear 223 bulk transfer video datas to SDRAM control nuclear 221 by NIOS II CPU224 control DMA.

Serial line interface (UART) control nuclear 222 provides convenience for communications between embedded system and the external devices.Serial line interface (UART) control nuclear 222 is observed RS-232 agreement sequential provides adjustable baud rate through the baud rate frequency division, parity check bit, position of rest and data bit.Serial line interface control nuclear 222 interface schematic diagrames are referring to Figure 24.

Serial line interface control nuclear 222 connects AVALON from interface, is uploaded to host computer after converting parallel data to serial data via control register; Thereby the serial data of input is converted to via control register and reaches AVALON after the parallel data and realized serial interface communication from interface.

Acquisition controlling nuclear 225 mainly is made of acquisition module and FIFO transport module, and the acquisition module in the NIOS II CPU224 control acquisition controlling nuclear 225 is gathered the data of Video processing 21 outputs, and data are write FIFO transport module in the acquisition controlling nuclear 225.

Acquisition controlling nuclear 225 meets the Avalon bus specification, this acquisition controlling nuclear 225 with Video processing 21 outputs data by the DMA control nuclear 223 complete SDRAM control nuclears of sending into, realize the storage and the processing of data.

The data frequency of Video processing 21 outputs is 27MHz, and every frame image data is 640 * 480 * 16bit pixel.Yet NIOSII CPU224 work clock is 50MHz, therefore needs the FIFO transport module to realize the continuity of front and back transmission.Acquisition controlling is examined 225 structural representations referring to Figure 25.

Acquisition controlling nuclear 225 comprises acquisition module and FIFO transport module.Acquisition module is realized the collection of Video processing 21 dateouts, and its input interface has: write clock (write_clk), write and enable (write_en) and 16 bit data bus (RGB[15:0]).Hanging over interface on the Avalon bus has data-out bus (FIFO Q[15:0]), chip selection signal (chipselect), reading request signal (read_req), Avalon bus address (address), reads spacing wave (read_empty), reads clock (read_clk).

The synchronizing signal II (RGB USEFUL) that uses Video processing 21 outputs is as writing enable signal, and the acquisition module in the NIOS IICPU224 control acquisition controlling nuclear 225 is to FIFO transport module write data.Because FIFO transport module output clock is not expired so the FIFO transport module can not write, and only can be read sky FIFO transport module greater than writing clock.So reading request signal (read_req) is sent by the Avalon bus, through reading spacing wave (read_empty), the time of reading data in the FIFO transport module by NIOS II CPU control DMA control nuclear is that the FIFO transport module begins to read the data in the FIFO transport module during for non-NULL for low level reading spacing wave (read_empty).The data time sequence that reads transmission from port of Avalon bus is referring to Figure 26, wherein effectively RGB data-signal (Data avai lable) connect the output of FIFO transport module read spacing wave (read_empty).FIFO transport module simulation waveform is referring to Figure 27.

Referring to Figure 26, when FIFO transport module non-NULL, promptly Data available is 1 o'clock, the chip selection signal of Avalon bus (chipselect), reads enable signal (read_en) simultaneously for high, reads the data of FIFO transport module output; When the FIFO transport module is sky, be that valid data (Data available) are 0 o'clock, the chip selection signal of Avalon bus (chipselect), read enable signal (read_en) simultaneously for low, data etc. FIFO transport module to be read, when FIFO transport module non-NULL, the chip selection signal of Avalon bus (chipselect), read enable signal (read_en), continue reading of data simultaneously for high.

VGA control nuclear 226 comprises that VGA timing sequencer, its structural representation of FIFO memory module are referring to Figure 28.RGB digital video signal, synchronizing signal II by the Avalon bus interface, transport to VGA control nuclear 226 and output to video display signal conversion 4 then.

Referring to Figure 29, when the FIFO memory module non-when full, be that read data (read for data) is 1 o'clock, the chip selection signal of Avalon bus (chipselect), write signal (write) is high simultaneously, the FIFO memory module reads Avalon bus dateout, when the FIFO memory module is write when full, be that read data (read for data) is 0 o'clock, the chip selection signal of Avalon bus (chipselect), write signal (write) is low simultaneously, the FIFO memory module is waited for Avalon bus dateout, and is non-when full up to the FIFO memory module, the chip selection signal of Avalon bus (chipselect), write signal (write) is high simultaneously, and the FIFO memory module continues to read Avalon bus dateout.

Because NIOS II CPU224 system clock is 50MHz, and VGA display timing generator generation input clock is 25MHz, and this needs the FIFO memory module to play a cushioning effect, is another peripheral hardware and control FIFO memory module reads and writes data---DMA control nuclear 223.In NIOS II control system 22, the data that the Video processing 21 that NIOSIICPU224 control acquisition controlling nuclear 225 is gathered is exported, NIOS II CPU224 control SDRAM control nuclear 221 is controlled nuclear 223 with the data of gathering via DMA and is deposited SDRAM32 in.Use DMA control nuclear 223 that data transmission channel is provided then, and the read-write of control FIFO memory module enables, FIFO memory module data when the clock frequency allotment of 50MHz and 25MHz are not overflowed.The clock signal that the data of reading with the 25MHz clock from the FIFO memory module produce synchronizing signal II that VGA needs, RGB digital video signal, show for VGA through the VGA timing sequencer.

Separately the VGA timing sequencer is carried out emulation, oscillogram is referring to Figure 30 after its emulation.

Specific implementation method in the step [2.2] is as follows, and its schematic flow sheet is referring to Figure 31.

(1) initialization DMA control nuclear: according to the internal register of designing requirement configuration DMA control nuclear.

Initialization DMA control nuclear 223 mainly is the register parameters of configuration DMA control nuclear 223.DMA control nuclear 223 has 5 registers.Be respectively:

Status register: represent DMA control nuclear 223 current transmission states for every of register, can judge the state of DMA control nuclear 223 by reading this register value, the value of this register can not write.Status register comprises that transmission complement mark (done), busy flag (busy), DMA control nuclear 223 end of transmissions are because read port sends end-of-packet incident (reop), DMA control nuclear 223 end of transmissions are because write port sends end-of-packet incident (weop), DMA control nuclear 223 end of transmissions are because the transmission byte number satisfies designated length (len).

Read address register: write DMA control nuclear 223 addresses of reading external port or SDRAM chip to this register.

Writing address register: the address that writes DMA control nuclear 223 output external port or SDRAM chip to this register.

Transmission byte length register: the total byte length of regulation DMA control nuclear 223 transmission, DMA control nuclear 223 every transmission one byte register values subtract 1, are 0 o'clock up to register value, DMA control nuclear 223 ends of transmission.

Control register: the mode of control DMA control nuclear 223 transmission data.Title and functional description thereof that control register is every see Table 3, and the transmission means of DMA control nuclear 223, transmission direction, transport property (stationarity of address) and other enable to control by control register.

Table 3

The position sequence number	The position title	Functional description
			??0	??BYTE	The byte transmission
??1	??HW	The half-word transmission
			??2	??WORD	The word transmission
??3	??GO	DMA enables
			??4	??LEN	Interruption enables

The position sequence number	The position title	Functional description
			??5	??REEN	Read to hold end-of-packet to enable
??6	??WREN	Writing the end end-of-packet enables
			??7	??LEEN	Designated length finishes
??8	??RCON	Fixed address is read
			??9	??WCON	Fixed address is write

Initialization DMA control nuclear 223 is at first with control register and status register zero clearing, write the data length that needs transmission to length register (LENGTH), then dispose the start address of main read port start address, main write port, last configuration control register makes DMA control nuclear 223 be in from the fixed address read data, enable 223 transmission of DMA control nuclear, nibble transmission state.This function is that reading of data is transferred among the SDRAM32 from the FIFO transport module.Therefore, in this module, the work of DMA control nuclear 223 is to be that a frame image data of 640 * 480 * 16 is write from main read port (address is 0x00c010b8) and become owner of write port (the pointer base address of SDRAM) with length.The table of comparisons 3 is configured to 394 with control register, finishes the storage of image data.Design DMA control nuclear 223 initial configuration DMA control nuclear 223 internal register parameter concrete configurations are as follows:

void?init_dma1()

{

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_STATUS(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_0_BASE，LENTH)；

IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_0_BASE，0x00C010B8)；

IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_0_BASE，FRAME_BUFFER[0])；

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，394)；

}

After having disposed the transmission parameter of DMA control nuclear 223, just 223 reading of data are examined in may command DMA control.DMA control nuclear 223 begin from the enable signal of FIFO transport module read data by NIOS II control system 22 write control switch and the valid pixel signal provides.In case enable DMA control nuclear 223,223 transmission voluntarily of DMA control nuclear, NIOS IICPU224 can handle other affairs, when stops transmission as long as handle DMA control nuclear 223.Enable signal by DMA control nuclear 223 in software calls DMA control nuclear 223 transfer functions, whenever enables a DMA transmission, can transmit a frame image data and deposit system's main memory in.

If read the multiple image data of depositing in SDRAM32, can expend too many NIOSII CPU224 resource and should not control with the direct scheduled transmission of NIOS II CPU224, and DMA control nuclear 223 can be realized the transmission of mass data, control simply, the accuracy rate height.

(2) enable DMA control nuclear 223

DMA control nuclear 223 is enabled to judge that can DMA control nuclear 223 transmit data;

(3) storage

(3.1) judge whether the FIFO transport module is empty:

If the FIFO transport module is empty, then carries out DMA control nuclear 223 and wait for.

If the FIFO transport module is non-NULL, then DMA control nuclear 223 control FIFO transport modules with image data storage to SDRAM32.

(3.2) judge whether the view data that is stored to SDRAM32 is a frame, has not deposited when frame data, then is back to step (3.1);

(3.3) deposited when frame data, judged whether that next frame data etc. are to be stored; When not having next frame data etc. to be stored, then finish storage;

(3.4) when next frame data etc. are to be stored, judge whether SDRAM32 is filled with, if SDRAM32 is not filled with and then is back to step (1); If SDRAM32 has stored full, then end data storage.

DMA control nuclear 223 transmission course specific implementation processes are as follows:

A) NIOS II CPU224 prepares to start 223 transmission of DMA control nuclear by its control port (control port) configuration DMA control nuclear 223.

B) NIOS IICPU224 starts DMA control nuclear 223, and DMA control nuclear 223 transmits, i.e. 223 beginnings of DMA control nuclear transmit data under the situation that does not have NIOS II CPU224 to interfere.

C) the main write port of DMA control nuclear 223 writes data to the FIFO transport module then in regular turn from reading address reading data, the main write port of DMA control nuclear 223 reading of data and write data to destination address from the FIFO memory module; In transmission course, can not need NIOSIICPU224 to intervene, but NIOSIICPU224 can stop current DMA control nuclear 223 transmission courses.

D) reach designated length or run into end mark (EOP) when transmitting data, DMA control nuclear 223 ends of transmission, DMA control nuclear 223 will produce DMA control nuclear 223 ends of transmission and interrupt.

The specific implementation method of view data output is as follows: image flow for displaying schematic diagram is referring to Figure 32.

1) according to the internal register of designing requirement configuration DMA control nuclear 223, DMA control nuclear 223 is carried out initialization;

The control register of initial configuration DMA control nuclear 223, status register, interrupt function, and read/write address, concrete configuration is as follows:

void?init_dma()

{alt_irq_register(DMA_0_IRQ，NULL，DMA_0_isr)；

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_STATUS(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_0_BASE，LENTH)；

IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_0_BASE，FRAME_BUFFER[0])；

IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_0_BASE，0x00C010B4)；

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，730)；

}

2) DMA control nuclear 223 is enabled to judge that DMA control nuclear 223 can transmit data;

3) using DMA control nuclear 223 interrupts view data is write the FIFO memory module

3.1) judge that the FIFO memory module is full?

If the FIFO memory module, is then carried out DMA control nuclear 223 for full and is waited for;

If the FIFO memory module is non-full, then DMA control nuclear 223 control FIFO memory modules read the data among the SDRAM32 and it are write the FIFO memory module;

3.2) judge whether refresh the FIFO memory module, do not write when frame data, then be back to step 3.1);

3.3) write when frame data, refresh the FIFO memory module, judged whether that next frame data etc. are to be written; When next frame data etc. are to be written, then be back to step 1);

3.4) when not having next frame data etc. to be written, judge whether stop in the FIFO memory module, to write data; When not stopping in the FIFO memory module, writing data, be back to step 1), when stopping in the FIFO memory module, writing data, then finish to write data to the FIFO memory module.

Different to the SDRAM32 mode with acquisition of image data, DMA control nuclear 223 transmits data to VGA and will keep image freeze to show or the filstrip broadcast, has used DMA control nuclear 223 interrupt functions.The continuity that its effect will keep image data to send exactly.When DMA control nuclear 223 sends a field data, just produce interrupt signal, the value of the status register of DMA control nuclear 223 is changed, enter interrupt function immediately, send another field data.The problem of running into here is that in a single day DMA control nuclear 223 enter interrupt function, for keeping the stable of picture will continual transmission data, take data/address bus, if NIOSIICPU224 handles other data, will exert an influence to DMA control nuclear 223 transmission data/address buss, picture will produce shake.For head it off can only make NIOSIICPU224 when showing tableaux, be in wait state.When showing that Deng end the tableaux signal is effective, NIOSIICPU224 ability operate as normal, its DMA control nuclear 223 interrupt routines are as follows:

static?void?DMA_0_isr(void*context，alt_u32?id)

{if(IORD_ALTERA_AVALON_DMA_STATUS(DMA_0_BASE)&0x01)

{IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_STATUS(DMA_0_BASE，0x00)；

IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_0_BASE，LENTH)；

IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_0_BASE，FRAME_BUFFER[0])；

IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_0_BASE，0x00C010B4)；

IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_0_BASE，730)；

}

}

223 transmission are provided with similar with DMA control nuclear, by serial line interface (UART) control nuclear 222 relevant register are set, carry out different serial line interface (UART) control nuclear 222 operations, but note be 222 transmission of serial line interface (UART) control nuclear be byte, and the data format of storage is a font.

According to the internal register explanation of table 4 serial line interface (UART) control nuclear 222, by the configuration relevant register can enable, the transmission of end, initialization string line interface (UART) control nuclear 222.

Table 4

Status register and control register by configuration serial line interface (UART) control nuclear 222 finish the transmission that serial line interface (UART) is controlled nuclear 222.

The variable initialize, state, the preparation of control register receives and is ready for sending position ' 1 ', waits for that entering serial line interface (UART) control nuclear 222 interrupts.Enter in serial line interface (UART) the control nuclear 222 and have no progeny, carry out transfer of data according to serial line interface 31 (UART) agreement, when frame image data transmission finished, knot serial line interface (UART) was controlled nuclear 222 transmission, jumped out serial line interface (UART) and controlled nuclear 222 interruptions.

Claims (8)

1. the method based on the video monitor of NIOS II is characterized in that, this method may further comprise the steps:

A. analog video signal is transported to vision signal conversion (1), after NIOS II control system (22) control in video computing/system's control (2), this analog video signal is converted to digital video signal and synchronizing signal I;

B. the processing of Video processing (21) in video computing/system's control (2) with digital video signal and synchronizing signal I, output RGB digital video signal and synchronizing signal II;

C. RGB digital video signal and the synchronizing signal II with Video processing (21) output directly transports to video display signal conversion (4), is converted to the RGB digital video signal of simulation; Or with the RGB digital video signal of Video processing (21) output and synchronizing signal II after NIOS II control system (22) is transported to SDRAM (32) storage in storage/communication (3), transport to video display signal and change the RGB digital video signal that (4) are converted to simulation; Perhaps the RGB digital video signal of Video processing (21) output and synchronizing signal II are transported to serial line interface (31) in storage/communication (3) earlier through NIOS II control system (22), after serial line interface (31) is uploaded to host computer;

D. the RGB digital video signal of simulation is transported to VGA and shown that (5) are for output;

The implementation method of described step b may further comprise the steps:

[1.1] decoding: the BT656 vision signal is decoded as the YCbCr digital video signal of interlacing and the synchronizing signal I of interlacing by BT656 decoding (211);

[1.2] go interlacing: with the synchronizing signal I of the YCbCr digital video signal of interlacing and interlacing by go interlacing (212) be converted to line by line the YCbCr digital video signal and synchronizing signal I line by line;

[1.3] video scaling: line by line YCbCr digital video signal and synchronizing signal I are line by line passed through video scaling (213) to YCbCr commentaries on classics RGB (214), be converted to the RGB digital video signal;

[1.4] sequential allotment: RGB digital video signal and NIOS II configurable clock generator signal by the VGA sequential clock signal that (215) blanking is allocated as RGB digital video signal, synchronizing signal II and shows for VGA are taken place;

[1.5] video scaling: according to the VGA sequential synchronizing signal II of (215) output, the configuration zooming parameter that NIOS II control system provides, the synchronizing signal I that goes interlacing (212) to export take place, will go the YCbCr digital video signal line by line of interlacing (212) output to be scaled the YCbCr digital video signal by video scaling (213);

[1.6] format digital video signal conversion: the YCbCr digital video signal of convergent-divergent is changeed RGB (214) by YCbCr be converted to the RGB digital video signal;

[1.7] sequential allotment: the clock signal that (215) blanking is allocated as RGB digital video signal, synchronizing signal II and shows for VGA takes place by the VGA sequential in RGB digital video signal and NIOS II configurable clock generator signal; The clock signal one tunnel that RGB digital video signal, synchronizing signal II and confession VGA show is transported to MUX selection (216), and another road is transported to MUX through NIOS II control system (22) and is selected (216);

[1.8] signal is selected: the RGB digital video signal that VGA sequential generation (215) is exported, synchronizing signal II and the clock signal that supplies VGA to show are directly selected (216) to export through MUX and are supplied the VGA demonstration, or RGB digital video signal, the synchronizing signal II of (215) output takes place the VGA sequential and supply the clock signal of VGA demonstration to select (216) output to supply the VGA demonstration through MUX again after NIOS II control system (22) is controlled;

The implementation method of described step c may further comprise the steps:

[2.1] NIOS II CPU (224) control acquisition controlling nuclear (225) is transferred to SDRAM control nuclear (221) and serial line interface control nuclear (222) with the data of Video processing (21) output through DMA control nuclear (223);

[2.2] data in NIOS II CPU (224) the control SDRAM control nuclear (221) are deposited to SDRAM (32) through DMA control nuclear (223);

[2.3] data after NIOS II CPU (224) control VGA control nuclear (226) will be changed export Video processing (21) to;

[2.4] NIOS II CPU (224) control SDRAM control nuclear (221) is delivered to VGA control nuclear (226) with data through DMA control nuclear (223);

[2.5] NIOS II CPU (224) control serial line interface control nuclear (222) with the transfer of data in the acquisition controlling nuclear (225) to host computer.

2. the method for a kind of video monitor based on NIOS II according to claim 1, it is characterized in that, acquisition controlling nuclear (225) in the described step [2.1] comprises acquisition module and FIFO transport module, acquisition module in NIOS IICPU (224) the control acquisition controlling nuclear (225) is gathered the data of Video processing (21) output, and data are write FIFO transport module in the acquisition controlling nuclear (225).

3. the method for a kind of video monitor based on NIOS II according to claim 1 and 2 is characterized in that, the VGA control nuclear (226) in the described step [2.5] comprises VGA timing sequencer, FIFO memory module.

4. the method for a kind of video monitor based on NIOS II according to claim 3 is characterized in that the specific implementation method of described step [2.2] is:

(1) initialization DMA control nuclear (223)

Internal register according to designing requirement configuration DMA control nuclear (223);

(2) enable DMA control nuclear (223)

DMA control nuclear (223) is enabled to judge that can DMA control nuclear (223) transmit data;

(3) storage

(3.1) judge whether the FIFO transport module is empty

If the FIFO transport module is empty, then carries out DMA control nuclear (223) and wait for;

If the FIFO transport module is non-NULL, then DMA control nuclear (223) control FIFO transport module with image data storage to SDRAM (32);

(3.2) judge whether the view data that is stored to SDRAM (32) is a frame, has not deposited when frame data, then is back to step (3.1);

(3.3) deposited when frame data, judged whether that next frame data etc. are to be stored; When not having next frame data etc. to be stored, then finish storage;

(3.4) when next frame data etc. are to be stored, judge whether SDRAM (32) is filled with, if SDRAM (32) is not filled with and then is back to step (1); If SDRAM (32) has stored full, then end data storage.

5. the method for a kind of video monitor based on NIOS II according to claim 4 is characterized in that the specific implementation method of described step [2.3] is:

1) initialization DMA control nuclear (223)

Internal register according to designing requirement configuration DMA control nuclear (223);

2) enable DMA control nuclear (223)

DMA control nuclear (223) is enabled to judge that DMA control nuclear (223) can transmit data;

3) using DMA control nuclear (223) interrupts view data is write the FIFO memory module

3.1) judge whether the FIFO memory module is full:

If the FIFO memory module for full, then carried out DMA control nuclear (223) and is waited for;

If the FIFO memory module is non-full, then DMA control nuclear (223) control FIFO memory module reads the data among the SDRAM (32) and it is write the FIFO memory module;

3.2) judge whether refresh the FIFO memory module, do not write when frame data, then be back to step 3.1);

3.3) write when frame data, refresh the FIFO memory module, judged whether that next frame data etc. are to be written; When next frame data etc. are to be written, then be back to step 1);

3.4) when not having next frame data etc. to be written, judge whether stop in the FIFO memory module, to write data; When not stopping in the FIFO memory module, writing data, be back to step 1), when stopping in the FIFO memory module, writing data, then finish to write data to the FIFO memory module.

6. the method for a kind of video monitor based on NIOS II according to claim 4 is characterized in that the implementation method of described step [2.5] is:

A) initialization string line interface (UART) control nuclear (222);

B) data and the signal that parallel data and conversion of signals are serial.

7. the method for a kind of video monitor based on NIOS II according to claim 1 is characterized in that, dual port RAM is adopted in the interlacing (212) of going in the described step [1.1].

8. the method for a kind of video monitor based on NIOS II according to claim 1 is characterized in that described step [1.6] application matrix

$\left[\begin{array}{c}R\\ G\\ B\end{array}\right]=\left[\begin{array}{ccc}1& 1.403& 0\\ 1& -0.714& -0.344\\ 1& 0& 1.770\end{array}\right]\&times;\left[\begin{array}{c}Y\\ \mathrm{Cr}\\ \mathrm{Cb}\end{array}\right]$ Realize.

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