CN103715077B - 一种深亚微米u型栅槽的制作方法 - Google Patents
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Abstract
本发明公开了一种深亚微米U型栅槽的制作方法,该方法包括:在半导体外延材料表面生长栅介质;在栅介质上匀胶;对电子束光刻胶进行曝光及显影;对电子束光刻胶进行回流烘胶,固化胶截面形成刻蚀窗口;采用ICP刻蚀工艺对栅介质进行刻蚀;以及去胶形成U型栅槽。利用本发明,能够得到栅角圆滑的U型栅槽,有效降低了器件源漏间,尤其是栅漏间的峰值电场,提高了器件的击穿电压,减少了器件漏电,提高了器件效率。
Description
技术领域
本发明涉及一种深亚微米U型栅槽的制作方法,尤其是针对高频场效应晶体管(FET),能有效降低器件源漏间,尤其是栅漏间的峰值电场,提高器件的击穿电压,减少器件漏电,提高器件效率。
背景技术
毫米波段功率放大器在军用、商用和消费领域具有巨大的应用前景。高频宽带无线通信技术、精确制导武器、远程雷达及空间通讯技术,工作频段从C、X波段逐渐向Ku、Ka等更高频段发展。
随着场效应晶体管(FET)工作频率的增加,对器件截止频率的要求也随之增加。截止频率是衡量晶体管高速性能的重要因子,公式为:
其中vs为载流子的饱和漂移速率,Lg为栅长。可以看出,栅长是决定器件截止频率最关键的因素。通常,工作在X波段以上的场效应晶体管的栅长都在深亚微米量级。
在化合物半导体器件中,为了抑制材料外延表面态导致的电流崩塌效应,通常采用钝化工艺,在钝化工艺后,采用凹栅槽工艺形成栅结构的栅脚部分。
但是,随着器件工作频率的提高,源漏间距以及栅脚线条尺寸都相应变小,器件栅漏之间的场强变高,从而导致器件击穿电压变低,同时,强变高将会导致够沟道电子在强电场下极易进入缓冲(buffer)层,这将导致漏电增加,器件效率降低。
因此,如何在缩短器件特征尺寸的同时调制源漏间电场分布,抑制沟道的强电场,提高器件的击穿电压成为了器件设计和工艺开发的一个重点。
发明内容
(一)要解决的技术问题
有鉴于此,本发明的主要目的在于提供一种深亚微米U型栅槽的制作方法,以有效降低器件源漏间,尤其是栅漏间的峰值电场,提高器件的击穿电压,减少器件漏电,提高器件效率。
(二)技术方案
为达到上述目的,本发明提供了一种深亚微米U型栅槽的制作方法,该方法包括:在半导体外延材料表面生长栅介质;在栅介质上匀胶;对电子束光刻胶进行曝光及显影;对电子束光刻胶进行回流烘胶,固化胶截面形成刻蚀窗口;采用ICP刻蚀工艺对栅介质进行刻蚀;以及去胶形成U型栅槽。
上述方案中,所述在半导体外延材料表面生长栅介质的步骤中,所述半导体外延材料是GaN衬底,所述栅介质是Si3N4,采用PECVD生长。
上述方案中,所述在栅介质上匀胶的步骤中,是在栅介质上涂敷ZEP520电子束光刻胶,厚度为并采用180℃热板真空加热3分钟。
上述方案中,所述对电子束光刻胶进行曝光及显影的步骤中,采用电子束曝光,剂量为300μC/cm2,电流为200pA,能量为100kV;显影液ZED-N50显影90秒,定影液ZMD-D定影15秒,并用氮气吹干。
上述方案中,所述对电子束光刻胶进行回流烘胶的步骤中,是对ZEP520电子束光刻胶进行150℃热板真空回流烘胶10分钟。
上述方案中,所述采用ICP刻蚀工艺对栅介质进行刻蚀的步骤之前,还包括:使用氧等离子体对表面进行处理,去除表面残胶。
上述方案中,所述采用ICP刻蚀工艺对栅介质进行刻蚀的步骤中,刻蚀气体采用SF6和CHF3的混合气体,比例为SF6∶CHF3=3∶40,刻蚀压力为3.5Pa,射频功率(RF)为20W,直流功率(LF)为250W,刻蚀时间为180秒。
上述方案中,所述去胶形成U型栅槽的步骤中,是采用去胶液ZDMAC去胶30分钟,IPA冲洗,去离子水冲洗,氮气吹干,形成U型栅槽。所述去胶形成U型栅槽的步骤中,栅槽尺寸为100nm~200nm。
(三)有益效果
从上述技术方案可以看出,本发明具有以下有益效果:
1、利用本发明,由于优化了ICP等离子刻蚀工艺的气体选择和刻蚀压力,所以能够得到栅角圆滑的U型栅槽,有效降低了器件源漏间,尤其是栅漏间的峰值电场,提高了器件的击穿电压,减少了器件漏电,提高了器件效率。
2、利用本发明,一次电子束曝光采用ZEP520A,通过电子束曝光和ICP刻蚀,能将栅脚控制在深亚微米量级,尺寸在100nm~250nm之间;
3、利用本发明,由于采用高温回流烘胶,条件为150℃热板真空回流烘胶10分钟,固化了胶的形状,提高了ICP刻蚀的一致性和重复性;
4、利用本发明,由于优化了ICP等离子刻蚀工艺的气体选择和刻蚀压力,所以能够有效降低器件源漏间,尤其是栅漏间的峰值电场,提高了器件的击穿电压。
附图说明
图1为本发明提供的制作深亚微米U型栅槽的方法流程图;
图2a至图2f为依照本发明实施例的制作深亚微米U型栅槽的工艺流程图;
图3a为显影后ZEP520电子束光刻胶的截面;
图3b为回流烘胶后ZEP520电子束光刻胶的截面;
图4a为回流烘胶和ICP刻蚀后截面,刻蚀压力为0.5Pa;
图4b为回流烘胶和ICP刻蚀后截面,,刻蚀压力为3.5Pa;
图5a为栅脚尺寸约为100nm的U型栅槽截面;
图5b为栅脚尺寸约为150nm的U型栅槽截面;
图5c为栅脚尺寸约为200nm的U型栅槽截面;
图5d为栅脚尺寸约为250nm的U型栅槽截面;
图6a为器件正向击穿电压测试结果;
图6b为器件肖特基结的反向击穿电压测试结果。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
本发明提供了一种深亚微米U型栅槽的制作方法,该方法将传统栅槽的直角优化成有弧度的U型,避免电场尖峰的出现,平滑场强分布;采用Si3N4做为栅介质,结合电子束曝光工艺、回流工艺以及ICP刻蚀工艺得到深亚微米U型栅槽。
如图1所示,图1为本发明提供的制作深亚微米U型栅槽的方法流程图,该方法包括以下步骤:
步骤1:在半导体外延材料表面生长栅介质;
步骤2:在栅介质上匀胶;
步骤3:对电子束光刻胶进行曝光及显影;
步骤4:对电子束光刻胶进行回流烘胶,固化胶截面形成刻蚀窗口;
步骤5:采用ICP刻蚀工艺对栅介质进行刻蚀;
步骤6:去胶形成U型栅槽。
其中,步骤1中所述半导体外延材料是GaN衬底,所述栅介质是Si3N4,采用PECVD生长。步骤2中在栅介质上匀胶,是在栅介质上涂敷ZEP520电子束光刻胶,厚度为并采用180℃热板真空加热3分钟。步骤3中所述对电子束光刻胶进行曝光及显影,是采用电子束曝光,剂量为300μC/cm2,电流为200pA,能量为100kV;显影液ZED-N50显影90秒,定影液ZMD-D定影15秒,并用氮气吹干。步骤4中所述对电子束光刻胶进行回流烘胶,是对ZEP520电子束光刻胶进行150℃热板真空回流烘胶10分钟。步骤4中所述采用ICP刻蚀工艺对栅介质进行刻蚀之前,还包括:使用氧等离子体对表面进行处理,去除表面残胶。步骤5中所述采用ICP刻蚀工艺对栅介质进行刻蚀,刻蚀气体采用SF6和CHF3的混合气体,比例为SF6∶CHF3=3∶40,刻蚀压力为3.5Pa,射频功率(RF)为20W,直流功率(LF)为250W,刻蚀时间为180秒。步骤6中所述去胶形成U型栅槽,是采用去胶液ZDMAC去胶30分钟,IPA冲洗,去离子水冲洗,氮气吹干,形成U型栅槽中,栅槽尺寸为100nm~200nm。
基于图1所示的制作深亚微米U型栅槽的方法流程图,图2a至图2f示出了依照本发明实施例的制作深亚微米U型栅槽的工艺流程图,具体包括:
如图2a所示,在GaN衬底上生长栅介质,在本实施例中是采用PECVD方法在GaN衬底上生长Si3N4做为栅介质;
如图2b所示,匀胶,即在Si3N4栅介质上涂敷ZEP520电子束光刻胶,厚度约为并采用180℃热板真空加热3分钟;
如图2c所示,对电子束光刻胶进行曝光及显影,采用电子束曝光,剂量为300μC/cm2,电流为200pA,能量为100kV;显影液ZED-N50显影90秒,定影液ZMD-D定影15秒,并用氮气吹干;
如图2d所示,对电子束光刻胶进行回流烘胶,固化胶截面形成刻蚀窗口;即对ZEP520电子束光刻胶进行150℃热板真空回流烘胶10分钟,固化胶截面形成刻蚀窗口;
如图2e所示,采用ICP刻蚀工艺对Si3N4栅介质进行刻蚀,刻蚀气体为SF6和CHF3的混合气体,比例为SF6∶CHF3=3∶40,刻蚀压力为3.5Pa,射频功率(RF)为20W,直流功率(LF)为250W,刻蚀时间为180秒。采用ICP刻蚀工艺对栅介质进行刻蚀之前,还包括:使用氧等离子体对表面进行处理,去除表面残胶。
如图2f所示,去胶形成U型栅槽;去胶液ZDMAC去胶30分钟,IPA冲洗,去离子水冲洗,氮气吹干,得到U型栅槽,栅槽尺寸为100nm~200nm。
图3为图2c和图2d后ZEP520电子束光刻胶的电镜照片,其中:图3a所示为显影后ZEP520电子束光刻胶的截面,图3b所示为回流烘胶后ZEP520电子束光刻胶的截面,可以看出,回流烘胶后,胶的形状从矩形变成了倒梯形。
图4为图2e后的电镜照片,同时对比了不同刻蚀条件的电镜照片,其中:图4a所示为回流烘胶和ICP刻蚀后截面,刻蚀压力为0.5Pa;图4b所示为回流烘胶和ICP刻蚀后截面,刻蚀压力为3.5Pa。可以看出,刻蚀压力从0.5Pa提高到3.5Pa后,栅槽形状从矩形栅槽变成了U型栅槽,符合实验设计要求。
图5为图2f后U型栅槽截面的电镜照片,对比了不同尺寸的电镜照片,其中:图5a所示为栅脚尺寸约为100nm的U型栅槽截面;图5b所示为栅脚尺寸约为150nm的U型栅槽截面;图5c所示为栅脚尺寸约为200nm的U型栅槽截面;图5d所示为栅脚尺寸约为250nm的U型栅槽截面。可以看出,利用本发明可以实现100nm~250nm的U型栅槽,符合实验设计要求。
图6是采用本发明的U型栅槽制作的GaN HEMT器件的击穿电压测试结果。其中,图6a所示为器件正向击穿电压测试结果,图6b所示为器件肖特基结的反向击穿电压测试结果。可以看出,器件正向和反响击穿电压均大于100V,符合器件性能要求。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (6)
1.一种深亚微米U型栅槽的制作方法,该方法包括:
在半导体外延材料表面生长栅介质;
在栅介质上匀胶;
对电子束光刻胶进行曝光及显影;
对电子束光刻胶进行回流烘胶,固化胶截面形成刻蚀窗口;
采用ICP刻蚀工艺对栅介质进行刻蚀;以及
去胶形成U型栅槽;
其中,所述对电子束光刻胶进行回流烘胶的步骤中,是对ZEP520电子束光刻胶进行150℃热板真空回流烘胶10分钟;
所述采用ICP刻蚀工艺对栅介质进行刻蚀的步骤中,刻蚀气体采用SF6和CHF3的混合气体,比例为SF6:CHF3=3:40,刻蚀压力为3.5Pa,射频功率为20W,直流功率为250W,刻蚀时间为180秒。
2.根据权利要求1所述的深亚微米U型栅槽的制作方法,其特征在于,所述在半导体外延材料表面生长栅介质的步骤中,所述半导体外延材料是GaN衬底,所述栅介质是Si3N4,采用PECVD生长。
3.根据权利要求1所述的深亚微米U型栅槽的制作方法,其特征在于,所述在栅介质上匀胶的步骤中,是在栅介质上涂敷ZEP520电子束光刻胶,厚度为并采用180℃热板真空加热3分钟。
4.根据权利要求1所述的深亚微米U型栅槽的制作方法,其特征在于,所述对电子束光刻胶进行曝光及显影的步骤中,采用电子束曝光,剂量为300μC/cm2,电流为200pA,能量为100kV;显影液ZED-N50显影90秒,定影液ZMD-D定影15秒,并用氮气吹干。
5.根据权利要求1所述的深亚微米U型栅槽的制作方法,其特征在于,所述采用ICP刻蚀工艺对栅介质进行刻蚀的步骤之前,还包括:使用氧等离子体对表面进行处理,去除表面残胶。
6.根据权利要求1所述的深亚微米U型栅槽的制作方法,其特征在于,所述去胶形成U型栅槽的步骤中,是采用去胶液ZDMAC去胶30分钟,IPA冲洗,去离子水冲洗,氮气吹干,形成U型栅槽。
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