CN103681302B - 选择性蚀刻方法 - Google Patents
选择性蚀刻方法 Download PDFInfo
- Publication number
- CN103681302B CN103681302B CN201210360730.3A CN201210360730A CN103681302B CN 103681302 B CN103681302 B CN 103681302B CN 201210360730 A CN201210360730 A CN 201210360730A CN 103681302 B CN103681302 B CN 103681302B
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- gas
- selective etching
- slit
- etching according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005530 etching Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 18
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 16
- 150000002367 halogens Chemical class 0.000 claims abstract description 16
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 13
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 22
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 5
- 230000008676 import Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 238000000059 patterning Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
本发明提供一种选择性蚀刻方法,包括下列步骤:提供一硅基板;在该硅基板上形成一图案化硅氧化物罩幕;以及导入一混合气体对该硅基板进行蚀刻,用以在该硅基板中形成一狭缝,并同时完全移除该图案化硅氧化物罩幕,其中该混合气体包括氟碳气体与卤素气体,且该氟碳气体与该卤素气体的比例介于1∶1~5∶1。本发明的方法不仅可以省略单独的移除四乙氧基硅烷罩幕层的步骤,而且有助于改善硅基板(狭缝)侧壁粗糙的问题。
Description
技术领域
本发明涉及一种半导体制备方法,特别涉及一种选择性蚀刻方法。
背景技术
在半导体制备方法中,当完成蚀刻硅基板的步骤后(例如在板中形成狭缝或开口),须续移除其上所覆盖例如四乙氧基硅烷(TEOS)的罩幕层(masklayer),以利后续制备过程的进行。但,一般而言,当完成蚀刻硅基板的步骤时,浅沟槽隔离物(shallowtrenchisolation,STI)结构业已形成且暴露在外,此时,若径向移除罩幕层,则浅沟槽隔离物(STI)结构势必在此移除过程中遭受损害。因此,如何在蚀刻硅基板的同时,也一并移除其上所覆盖的罩幕层而不须额外再增加后续移除罩幕层的步骤是本领域在改善半导体制备方法上持续努力的方向。
发明内容
为解决上述现阶段存在的技术缺陷,本发明提供一种选择性蚀刻方法,包括下列步骤:
提供一硅基板;
在该硅基板上形成一图案化硅氧化物罩幕;以及
导入一混合气体对该硅基板进行蚀刻,用以在该硅基板中形成一狭缝(slit),并同时完全移除该图案化硅氧化物罩幕,其中该混合气体包括氟碳(fluorocarbon)气体与卤素气体,且该氟碳气体与该卤素气体的比例介于1:1~5:1。
根据本发明的构思,该硅基板为多晶硅。
根据本发明的构思,该硅氧化物罩幕为四乙氧基硅烷(tetraethoxysilane,TEOS)。
根据本发明的构思,以一等离子体蚀刻(plasmaetching)方法对该硅基板进行蚀刻。
根据本发明的构思,该氟碳气体包括四氟甲烷(CF4)与三氟甲烷(CHF3)。
根据本发明的构思,该四氟甲烷(CF4)与三氟甲烷(CHF3)的比例介于1:1~1:3。
根据本发明的构思,该卤素气体包括氟气或氯气。
根据本发明的构思,该狭缝的深度大于200nm。
在蚀刻硅基板的方法中,本发明通过调整混合气体中属于氟碳(fluorocarbon)气体类且以造成非等向性蚀刻(anisotropicetching)效应为主的四氟甲烷(CF4)与三氟甲烷(CHF3)气体之间的比例至一特定比例以增加此蚀刻过程对例如四乙氧基硅烷(TEOS)罩幕层的蚀刻选择性(selectivity),以致当完成硅基板蚀刻在板中形成狭缝(slit)时,四乙氧基硅烷(TEOS)罩幕层可同时被完全移除,不须再另进行后续移除四乙氧基硅烷(TEOS)罩幕层的步骤。此外,调整混合气体中属于卤素(halogen)气体类的氟气或氯气的比例至一特定比例可有效降低蚀刻硅基板时对硅基板所造成的等向性蚀刻(isotropicetching)效应,有助改善硅基板中的狭缝的侧壁粗糙的问题。
附图说明
图1A~1D为本发明实施例中的一种选择性蚀刻方法示意图。
【主要部件符号说明】
10~硅基板;
12~氮化硅层;
14~硅氧化物层;
16~图案化光阻层;
18~混合气体;
20~狭缝。
具体实施方式
请参阅图1A~1D,说明本发明的一实施例,一种选择性蚀刻方法,包括下列步骤:
首先,请参阅图1A,提供一硅基板10。在一实施例中,硅基板10可为多晶硅。之后,形成一氮化硅层12于硅基板10上。在一实施例中,通过例如化学气相沉积(chemicalvapordeposition,CVD)方法形成氮化硅层12于硅基板10上。接着,形成一硅氧化物层14于氮化硅层12上。在一实施例中,硅氧化物层14可为四乙氧基硅烷(tetraethoxysilane,TEOS)。在一实施例中,通过例如化学气相沉积(chemicalvapordeposition,CVD)方法形成硅氧化物层14于氮化硅层12上。之后,形成一图案化光阻层16于硅氧化物层14上。
接着,以图案化光阻层16为一罩幕(mask),对硅氧化物层14与氮化硅层12进行蚀刻(图案化),以形成图案化的硅氧化物层14与氮化硅层12。在一实施例中,以图案化光阻层16为一罩幕,通过例如等离子蚀刻(plasmaetching)方法对硅氧化物层14与氮化硅层12进行蚀刻(图案化),以形成图案化的硅氧化物层14与氮化硅层12。之后,移除图案化光阻层16,如图1B所示。
接着,请参阅图1C,以图案化的硅氧化物层14与氮化硅层12为一罩幕(mask),导入一混合气体18对硅基板10进行一蚀刻,用以在硅基板10中形成一狭缝(slit)20,值得注意的是,在形成狭缝20的过程中,图案化的硅氧化物层14将同时被完全移除,如图1D所示。在一实施例中,以图案化的硅氧化物层14与氮化硅层12为一罩幕,导入一混合气体18,通过例如等离子蚀刻(plasmaetching)方法对硅基板10进行蚀刻,用以在硅基板10中形成狭缝20。在一实施例中,在硅基板10中所形成狭缝20的深度大于200nm。
上述导入用于蚀刻的混合气体18包括氟碳(fluorocarbon)气体与卤素(halogen)气体,且氟碳气体与卤素气体的比例介于1:1~5:1。在一实施例中,氟碳(fluorocarbon)气体可包括四氟甲烷(CF4)与三氟甲烷(CHF3)。在一实施例中,四氟甲烷(CF4)与三氟甲烷(CHF3)的比例大体介于1:1~1:3。在一实施例中,卤素气体可包括氟气或氯气。
在蚀刻硅基板的方法中,本发明通过调整混合气体中属于氟碳(fluorocarbon)气体类且以造成非等向性蚀刻(anisotropicetching)效应为主的四氟甲烷(CF4)与三氟甲烷(CHF3)气体之间的比例至一特定比例以增加此蚀刻过程对例如四乙氧基硅烷(TEOS)罩幕层的蚀刻选择性(selectivity),以致当完成硅基板蚀刻在板中形成狭缝(slit)时,四乙氧基硅烷(TEOS)罩幕层可同时完全被移除,不须再另进行后续移除四乙氧基硅烷(TEOS)罩幕层的步骤。此外,调整混合气体中属于卤素(halogen)气体类的氟气或氯气的比例至一特定比例可有效降低蚀刻硅基板时对硅基板所造成的等向性蚀刻(isotropicetching)效应,有助改善硅基板中的狭缝的侧壁粗糙的问题。
Claims (8)
1.一种选择性蚀刻方法,其特征在于,包括下列步骤:
提供一硅基板;
在所述硅基板上形成一图案化硅氧化物罩幕;以及
导入一混合气体对所述硅基板进行蚀刻,用以在所述硅基板中形成一狭缝,并同时完全移除所述图案化硅氧化物罩幕,所述混合气体包括氟碳气体与卤素气体,且所述氟碳气体与所述卤素气体的比例介于1∶1~5∶1。
2.根据权利要求1所述的选择性蚀刻方法,其特征在于,所述硅基板为多晶硅。
3.根据权利要求1所述的选择性蚀刻方法,其特征在于,所述硅氧化物罩幕为四乙氧基硅烷。
4.根据权利要求1所述的选择性蚀刻方法,其特征在于,以等离子蚀刻方法对所述硅基板进行蚀刻。
5.根据权利要求1所述的选择性蚀刻方法,其特征在于,所述氟碳气体包括四氟甲烷与三氟甲烷。
6.根据权利要求5所述的选择性蚀刻方法,其特征在于,所述四氟甲烷与三氟甲烷的比例介于1∶1~1∶3。
7.根据权利要求1所述的选择性蚀刻方法,其特征在于,所述卤素气体包括氟气或氯气。
8.根据权利要求1所述的选择性蚀刻方法,其特征在于,所述狭缝的深度大于200nm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210360730.3A CN103681302B (zh) | 2012-09-25 | 2012-09-25 | 选择性蚀刻方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210360730.3A CN103681302B (zh) | 2012-09-25 | 2012-09-25 | 选择性蚀刻方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103681302A CN103681302A (zh) | 2014-03-26 |
CN103681302B true CN103681302B (zh) | 2016-07-27 |
Family
ID=50318499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210360730.3A Active CN103681302B (zh) | 2012-09-25 | 2012-09-25 | 选择性蚀刻方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103681302B (zh) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6541164B1 (en) * | 1997-10-22 | 2003-04-01 | Applied Materials, Inc. | Method for etching an anti-reflective coating |
US6458671B1 (en) * | 2001-02-16 | 2002-10-01 | Applied Materials Inc. | Method of providing a shallow trench in a deep-trench device |
KR100562674B1 (ko) * | 2003-11-03 | 2006-03-20 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조 방법 |
JP2007110005A (ja) * | 2005-10-17 | 2007-04-26 | Nec Electronics Corp | 半導体装置の製造方法 |
CN100517640C (zh) * | 2006-12-05 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法和半导体器件 |
US20100310828A1 (en) * | 2007-11-16 | 2010-12-09 | Ulvac, Inc. | Substrate processing method and substrate processed by this method |
-
2012
- 2012-09-25 CN CN201210360730.3A patent/CN103681302B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN103681302A (zh) | 2014-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9378975B2 (en) | Etching method to form spacers having multiple film layers | |
US9070635B2 (en) | Removing method | |
US8383485B2 (en) | Epitaxial process for forming semiconductor devices | |
CN103177950B (zh) | 制造鳍器件的结构和方法 | |
US9048192B2 (en) | Method of forming a pattern | |
CN103515321B (zh) | 半导体器件的侧墙形成方法 | |
US8329547B2 (en) | Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide | |
US20160079388A1 (en) | Production of spacers at flanks of a transistor gate | |
US7462562B2 (en) | Fabrication method of semiconductor device | |
CN107731666B (zh) | 双重图形化的方法 | |
JP2013131587A5 (zh) | ||
JP2011114216A (ja) | 半導体装置の製造方法 | |
US9384994B2 (en) | Method of forming multiple patterning spacer structures | |
CN103681302B (zh) | 选择性蚀刻方法 | |
US9805934B2 (en) | Formation of contact/via hole with self-alignment | |
TW202121527A (zh) | 以多色選擇性非等向性蝕刻相鄰線的方法 | |
CN104064449B (zh) | 一种半导体器件的制造方法 | |
US8334205B2 (en) | Method for removing polymer after etching gate stack structure of high-K gate dielectric/metal gate | |
CN108807267B (zh) | 半导体装置及其制造方法 | |
CN102881581B (zh) | 在基底中形成狭缝的方法及刻蚀气体组成 | |
US20110223768A1 (en) | Method for Forming Contact Opening | |
US9646884B2 (en) | Block level patterning process | |
JP2010093158A (ja) | 半導体装置の製造方法 | |
JP2007042885A (ja) | 半導体製造方法 | |
JP2006032801A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |