CN103608917B - 超薄功率晶体管和具有定制占位面积的同步降压变换器 - Google Patents

超薄功率晶体管和具有定制占位面积的同步降压变换器 Download PDF

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CN103608917B
CN103608917B CN201280028281.0A CN201280028281A CN103608917B CN 103608917 B CN103608917 B CN 103608917B CN 201280028281 A CN201280028281 A CN 201280028281A CN 103608917 B CN103608917 B CN 103608917B
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thickness
contact pad
chip
strip
terminal
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CN103608917A (zh
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J·A·赫尔嵩末
O·J·洛佩斯
J·A·浓趣勒
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/442—Shapes or dispositions of multiple leadframes in a single chip
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01321—Manufacture or treatment of die-attach connectors using local deposition
    • H10W72/01323—Manufacture or treatment of die-attach connectors using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/074—Connecting or disconnecting of anisotropic conductive adhesives
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/344—Dispositions of die-attach connectors, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Dc-Dc Converters (AREA)
CN201280028281.0A 2011-04-07 2012-04-09 超薄功率晶体管和具有定制占位面积的同步降压变换器 Active CN103608917B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/082,147 US9165865B2 (en) 2011-04-07 2011-04-07 Ultra-thin power transistor and synchronous buck converter having customized footprint
US13/082,147 2011-04-07
PCT/US2012/032788 WO2013106050A2 (en) 2011-04-07 2012-04-09 Ultra-thin power transistor and synchronous buck converter having customized footprint

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Publication Number Publication Date
CN103608917A CN103608917A (zh) 2014-02-26
CN103608917B true CN103608917B (zh) 2016-11-16

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CN201280028281.0A Active CN103608917B (zh) 2011-04-07 2012-04-09 超薄功率晶体管和具有定制占位面积的同步降压变换器

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US (2) US9165865B2 (https=)
EP (1) EP2724368B1 (https=)
JP (1) JP6053752B2 (https=)
CN (1) CN103608917B (https=)
WO (1) WO2013106050A2 (https=)

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US9184121B2 (en) * 2014-02-05 2015-11-10 Texas Instruments Incorporated Stacked synchronous buck converter having chip embedded in outside recess of leadframe
US9171828B2 (en) 2014-02-05 2015-10-27 Texas Instruments Incorporated DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
US9508625B2 (en) * 2014-04-01 2016-11-29 Infineon Technologies Ag Semiconductor die package with multiple mounting configurations
US20150371930A1 (en) * 2014-06-18 2015-12-24 Texas Instruments Incorporated Integrated Circuit Packaging Method Using Pre-Applied Attachment Medium
US9721860B2 (en) 2014-11-06 2017-08-01 Texas Instruments Incorporated Silicon package for embedded semiconductor chip and power converter
WO2016080521A1 (ja) * 2014-11-20 2016-05-26 日本精工株式会社 電子部品搭載用放熱基板
CN104465423B (zh) * 2014-12-08 2017-08-22 杰群电子科技（东莞）有限公司 一种双引线框架叠合设计半导体器件封装方法
US10032884B2 (en) 2015-10-22 2018-07-24 International Business Machines Corporation Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling
CN106024745A (zh) * 2016-07-01 2016-10-12 长电科技（宿迁）有限公司 一种半导体管脚贴装结构及其焊接方法
CN109473414B (zh) * 2017-09-08 2022-11-11 万国半导体(开曼)股份有限公司 模制智能功率模块及其制造方法
JP7116303B2 (ja) * 2018-06-25 2022-08-10 日亜化学工業株式会社 パッケージ及び発光装置
DE102018214228A1 (de) * 2018-08-23 2020-02-27 Brose Fahrzeugteile Gmbh & Co. Kommanditgesellschaft, Bamberg Elektronik eines Elektromotors eines Kraftfahrzeugs
US11145578B2 (en) 2019-09-24 2021-10-12 Infineon Technologies Ag Semiconductor package with top or bottom side cooling and method for manufacturing the semiconductor package
US11742267B2 (en) 2020-10-12 2023-08-29 Toyota Motor Engineering And Manufacturing North America, Inc. Power electronics assembly having flipped chip transistors
DE112021005639T5 (de) * 2020-12-23 2023-08-03 Rohm Co., Ltd. Verfahren zur herstellung eines halbleiterbauteils und halbleiterbauteils
EP4314397A1 (en) * 2021-03-31 2024-02-07 University of Copenhagen Transferable networks and arrays of nanostructures
US20250112132A1 (en) * 2023-09-29 2025-04-03 Alpha And Omega Semiconductor International Lp Semiconductor package having lead frame with slanted sections

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CN101283449A (zh) * 2005-07-01 2008-10-08 金·沃扬 以单个贴装封装实现的完整功率管理系统
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US20100148346A1 (en) * 2008-12-12 2010-06-17 Quinones Maria Clemens Y Semiconductor die package including low stress configuration

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US6624007B2 (en) 2001-07-26 2003-09-23 Rohm Co., Ltd. Method of making leadframe by mechanical processing
JP2003100988A (ja) 2001-09-25 2003-04-04 Hitachi Ltd 半導体装置およびその製造方法
JP4386239B2 (ja) 2003-03-12 2009-12-16 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US7504733B2 (en) * 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US8354303B2 (en) 2009-09-29 2013-01-15 Texas Instruments Incorporated Thermally enhanced low parasitic power semiconductor package

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US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US20100148346A1 (en) * 2008-12-12 2010-06-17 Quinones Maria Clemens Y Semiconductor die package including low stress configuration

Also Published As

Publication number Publication date
JP2014515189A (ja) 2014-06-26
US20120256239A1 (en) 2012-10-11
EP2724368A4 (en) 2015-08-05
WO2013106050A2 (en) 2013-07-18
US9779967B2 (en) 2017-10-03
EP2724368B1 (en) 2016-11-16
WO2013106050A3 (en) 2013-10-03
EP2724368A2 (en) 2014-04-30
JP6053752B2 (ja) 2016-12-27
CN103608917A (zh) 2014-02-26
US9165865B2 (en) 2015-10-20
US20160005627A1 (en) 2016-01-07

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