CN103580681B - Phase-locked loop phase difference adjusting device - Google Patents
Phase-locked loop phase difference adjusting device Download PDFInfo
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- CN103580681B CN103580681B CN201210269962.8A CN201210269962A CN103580681B CN 103580681 B CN103580681 B CN 103580681B CN 201210269962 A CN201210269962 A CN 201210269962A CN 103580681 B CN103580681 B CN 103580681B
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Abstract
The invention provides a phase-locked loop phase difference adjusting device which comprises a phase difference detection module, a data processing module, and a digital-to-analog conversion module. A phase-locked loop inputting clock and a phase-locked loop output clock are connected to the input end of the phase difference detection module, and are used for detecting the phase difference of the input clock and the output clock; the data processing module is connected to the phase difference detection module, converts the detected phase difference data in proportion into DAC_data and outputs the DAC_data; the digital-to-analog conversion module is connected to the data processing module, takes the DAC_data as input data and converts the DAC_data as output currents, and the output currents are used as the input of a phase-locked loop filter. The phase-locked loop phase difference adjusting device is used in cooperation with an existing phase-locked loop, can adjust the phase between the input clock and the output clock dynamically under the situation that the losing lock phenomenon of the phase-locked loop does not occur, and improves synchronism.
Description
Technical field
The present invention relates to the signal processing technology in communicating, more particularly to the device that phaselocked loop phase contrast is adjusted.
Background technology
The technical field such as phaselocked loop is widely used in broadcast communication, frequency synthesis, automatically control and clock is synchronous.By reflecting
Phase device, loop filter and voltage controlled oscillator composition.Phase discriminator is used for differentiating the phase between input signal Ui and output signal U o
Potential difference, and output error voltage Ud.Noise and interference component in Ud is filtered by the loop filter of low-pass nature, is formed voltage-controlled
Control voltage Uc of agitator (VCO).Uc act on the result of voltage controlled oscillator be make phaselocked loop output clock and input when
Clock constant phase difference, so as to loop is locked, is referred to as into lock.In common phaselocked loop, when entering to lock every time, input clock with it is defeated
The phase contrast for going out clock is uncontrollable, enters phase contrast after lock and keeps constant.
Phase contrast size between phaselocked loop input clock and output clock is an important technology index of phaselocked loop.
At present under technology, the phase contrast between common phaselocked loop input, output is larger, will far from the phase contrast met in practical application
Ask.In addition, phaselocked loop common at present can just start phase adjustment only in the case of losing lock, can not in the case of non-losing lock
Dynamic adjustment, and for many products using phaselocked loop, losing lock can affect the normal work of product, be to receive
's.This directly affects application of the phaselocked loop in the higher field of numerous synchronicity requirements.
The content of the invention
It is an object of the invention to provide a kind of phaselocked loop phase contrast adjusting means, uses cooperatively with existing phaselocked loop, can be
In the case of the non-losing lock of phaselocked loop adjustment input, output clock between phase contrast, can be by adjusting offset to 80ps within,
Improve synchronicity.
In order to solve above-mentioned technical problem, following technological means are present invention employs：A kind of phaselocked loop phase contrast adjusts dress
Put, including phase difference detection module, phaselocked loop input clock and output clock are connected to the input of phase difference detection module, use
In the phase contrast for detecting the input clock and output clock；
Data processing module, connects the phase difference detection module, and the phase data for detecting is changed in proportion
Calculate output data DAC_data；
D/A converter module, connects the data processing module, and the DAC_data is converted to as input data
Output current, as the input of the cycle of phase-locked loop wave filter.
Further, the phase difference detection module constitutes a carry chain by n parallel data output channel, and n is certainly
So count.
Further, each circuit-switched data output channel includes a carry multiplexer MUXCY and a d type flip flop.
Further, the span of the n is：n≥1/f1* Δ t, wherein f1For the frequency of the input clock of phaselocked loop
Rate, Δ t is the time delay between the input and output of MUXCY.
The present invention is because using techniques described above scheme, the phaselocked loop phase contrast adjusting means can be different with form
Phaselocked loop use cooperatively, it is not necessary to change the framework of original phaselocked loop；And the device can be in the feelings of the non-losing lock of phaselocked loop
Under condition, the phase place between dynamic adjustment phaselocked loop input clock and output clock effectively prevents the appearance of phaselocked loop losing lock situation,
And effectively improve phaselocked loop input clock and export the synchronicity between clock.
Description of the drawings
The phaselocked loop phase contrast adjusting means of the present invention is shown in detail in by below example and accompanying drawing.
Fig. 1 is the system construction drawing of embodiment of the present invention phaselocked loop phase contrast adjusting means and phaselocked loop；
Fig. 2 a are phaselocked loop phase contrast adjusting means structural representation in one embodiment of the invention；
Fig. 2 b are phaselocked loop phase contrast adjusting means structural representation in another embodiment of the present invention；
Phase detecting module structural representation in Fig. 3 embodiment of the present invention.
Specific embodiment
The phaselocked loop phase contrast adjusting means of the present invention will be described in further detail below.
As shown in figure 1, including phaselocked loop 10 and phaselocked loop phase contrast adjusting means 20.
Phaselocked loop 10 further comprises phase discriminator 11, loop filter 12, voltage controlled oscillator 13, and frequency divider 14.Phase demodulation
Device 11 is used for differentiating the phase contrast between input signal and output signal, and output error voltage.Noise in error voltage and
Interference component is filtered by loop filter 12, forms the control voltage of voltage controlled oscillator 13.Control voltage acts on VCO
The result of device 13 is that its output clock is pulled to the input clock of loop filter 12 by frequency divider 14, when the two phase contrast is consolidated
Regularly, loop is locked, and is referred to as into lock.
As shown in Figure 2 a, the phase contrast adjusting means 20 also includes phase difference detection module 21, when phaselocked loop 10 is input into
Clock Tin and output clock Tout are connected to the input of phase difference detection module 21, for detecting the input clock Tin and defeated
Go out the phase contrast of clock Tout.
As shown in figure 3, in the phase difference detection module 21, using the frequency of the output clock of the phaselocked loop 10 as
The Tout of the phase difference detection module 21, using the frequency of the input clock of the phaselocked loop 10 as the phase difference detection mould
The Tin of block 21；The phase difference detection module 21 is made up of n data output channel Dn arranged side by side, the data output channel
Dn includes carry multiplexer MUXCY and a d type flip flop composition.The phase difference detection module 21 goes to adopt in the rising edge of Tout
N signal C [1]～Cs [n] of the collection Tin after 1 to n multiplexer time delay, obtains n positions phase data D [1]～D [n].Its
Middle n is natural number, and its span is：n≥1/f1* Δ t, f1For the frequency of the input clock of phaselocked loop, Δ t is MUXCY's
Time delay between input and output.Tout is approximately 0ps, Tin to n-th to the cabling time delay very little of each d type flip flop
The time delay of MUXCY is Δ t*n.As D [m-1]=1 and D [m]=0, it is possible to determine that collected with the rising edge of Tout
The rising edge of Tin, it is possible thereby to the rising edge for calculating Tout lags behind the rising edge m* Δ t of Tin, m* Δ t are exactly phase contrast.
The Δ t of the MUXCY in current main flow FPGA (Field-Programmable Gate Array, i.e. field programmable gate array)
Both less than 40ps, last Tout can be adjusted within 80ps with Tin phase difference detection precision for 2* Δ t, i.e. phase contrast.
Data processing module 22, connects the phase difference detection module 21, by the phase contrast m* Δs t for detecting by
Ratiometric conversion output data DAC_data；The ratio is determined by the parameter of DAC (digital to analog converter) and the voltage controlled oscillator 13
It is fixed.
D/A converter module 23, connects the data processing module 22, and using the DAC_data as input signal, turns
Output current Iout is changed to, as the input of the cycle of phase-locked loop wave filter.
As shown in Figure 2 b, in various embodiments, D/A converter module 23 according to actual needs can be by input signal
Output voltage Uout is converted to, in the D/A converter module 23 voltage/current conversion circuit 24, output current are reconnected
Iout, as the input of the cycle of phase-locked loop wave filter.
In the present invention, phaselocked loop phase contrast adjusting means 20 can be by being connected to the phaselocked loop 10 with upper type
On, therefore, there is no need to change or destroy the framework of original phaselocked loop；On the other hand, by phaselocked loop phase contrast adjusting means 20
Dynamic adjustment phase place is poor, realizes more preferable synchronization.
Due to these are only presently preferred embodiments of the present invention, protection scope of the present invention should not be limited thereto, i.e., it is every according to
The simple equivalence changes that claims of the present invention and present specification are made and modification, all should still belong to the present invention
In the range of patent covers.
Claims (2)
1. a kind of phaselocked loop phase contrast adjusting means, is connected to a phaselocked loop, it is characterised in that include：
Phase difference detection module, the input clock and output clock of the phaselocked loop are connected to the input of phase difference detection module
End, for detecting the phase contrast of the input clock and output clock；
Data processing module, connects the phase difference detection module, the phase data for detecting is converted in proportion defeated
Go out data DAC_data；
D/A converter module, connects the data processing module, and using the DAC_data as input data, is converted to output
Electric current, as the input of the loop filter of the phaselocked loop；
Wherein, the phase difference detection module is made up of n data output channel Dn arranged side by side, and each circuit-switched data output is logical
Road includes a carry multiplexer MUXCY and a d type flip flop, and the phase difference detection module goes collection in the rising edge of Tout
N signal C [1]～Cs [n] of the Tin after 1 to n carry multiplexer MUXCY time delays, obtain n positions phase data D [1]～
D [n], n are natural number, and n >=1/f1* Δ t, wherein f1For the frequency of the input clock of phaselocked loop, Δ t for it is described enter bit multiplex
Time delay between the input and output of device MUXCY, Tout is the output clock, and Tin is the input clock.
2. phaselocked loop phase contrast adjusting means as claimed in claim 1, it is characterised in that the phase difference detection module is by n
Individual parallel data output channel constitutes a carry chain, and n is natural number, and n >=1/f1*Δt。
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| CN201210269962.8A CN103580681B (en) | 2012-07-31 | 2012-07-31 | Phase-locked loop phase difference adjusting device |
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| CN201210269962.8A CN103580681B (en) | 2012-07-31 | 2012-07-31 | Phase-locked loop phase difference adjusting device |
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| CN103580681A CN103580681A (en) | 2014-02-12 |
| CN103580681B true CN103580681B (en) | 2017-04-19 |
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| CN111256836A (en) * | 2020-03-19 | 2020-06-09 | 广州赛恩科学仪器有限公司 | Infrared temperature measurement real-time recording sensing system based on phase-locked capture technology |
| CN111446957B (en) * | 2020-04-21 | 2023-05-09 | 哈尔滨工业大学 | Multi-PLL parallel output clock synchronization system and working method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138841B1 (en) * | 2003-12-23 | 2006-11-21 | Cypress Semiconductor Corp. | Programmable phase shift and duty cycle correction circuit and method |
| CN101176258A (en) * | 2005-06-17 | 2008-05-07 | 三星电子株式会社 | Phase locked loop and receiver using the same, phase detecting method |
| CN102468844A (en) * | 2010-11-11 | 2012-05-23 | 晨星软件研发(深圳)有限公司 | Phase-locked loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100574980B1 (en) * | 2004-04-26 | 2006-05-02 | 삼성전자주식회사 | Phase-Locked Loop for fast frequency locking |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138841B1 (en) * | 2003-12-23 | 2006-11-21 | Cypress Semiconductor Corp. | Programmable phase shift and duty cycle correction circuit and method |
| CN101176258A (en) * | 2005-06-17 | 2008-05-07 | 三星电子株式会社 | Phase locked loop and receiver using the same, phase detecting method |
| CN102468844A (en) * | 2010-11-11 | 2012-05-23 | 晨星软件研发(深圳)有限公司 | Phase-locked loop |
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Address after: 201815 Shanghai city Jiading Industrial Zone No. 1180 Building 8 Xing Xian Lu Patentee after: Shanghai Lianying Medical Technology Co., Ltd Address before: 201815 Shanghai city Jiading Industrial Zone No. 1180 Building 8 Xing Xian Lu Patentee before: SHANGHAI UNITED IMAGING HEALTHCARE Co.,Ltd. |
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Address after: 201807 2258 Chengbei Road, Jiading District, Shanghai Patentee after: Shanghai Lianying Medical Technology Co.,Ltd. Address before: Building 8, 1180 Xingxian Road, Jiading Industrial Zone, Shanghai, 201815 Patentee before: Shanghai Lianying Medical Technology Co.,Ltd. |
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