CN204119210U - A kind of delay locked loop - Google Patents
A kind of delay locked loop Download PDFInfo
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- CN204119210U CN204119210U CN201420433498.6U CN201420433498U CN204119210U CN 204119210 U CN204119210 U CN 204119210U CN 201420433498 U CN201420433498 U CN 201420433498U CN 204119210 U CN204119210 U CN 204119210U
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Abstract
The utility model provides a kind of delay locked loop, under the prerequisite of the least possible increase chip area and power consumption, delay locked loop precision is improved at least one times.This delay locked loop comprises DLL time delay chain, described DLL time delay chain comprises DLL coarse adjustment chain and DLL and finely tunes chain, it is characterized in that: described DLL coarse adjustment chain and DLL finely tune the intermediate phase generator of the intermediate phase clock be provided with between chain for generation of the strange clock of input clock signal and even clock.This raising delay locked loop produces two clock signals by the even clocks of two clock signals of input and strange clock, and be odd clock and sampling clock respectively, the phase difference of odd clock and sampling clock is the half of even clock and odd clock phases difference.
Description
Technical field
The utility model provides a kind of delay locked loop.
Background technology
Delay phase-locked loop (DLL) is widely used in the clock distributing network of interface between microprocessor, memory interface, chip and large scale integrated circuit, be used for the skew problems that clock synchronous solves clock, make the clock delay between chip internal or chip have enough surpluses, thus improve the sequential function of system.
Along with the increase of application system clock frequency, more and more higher to the requirement of DLL degree of regulation, because it directly determines the maximum phase demodulation error of DLL.Traditional DLL is made up of DLL time delay chain (comprising coarse adjustment chain and fine setting chain), delay of feedback, phase discriminator, DLL controller and output driver.Its operation principle is as follows:
The input clock of DLL produces delay clock after time delay chain, and delay clock produces feedback clock after delay of feedback, and feedback clock and input clock all input to phase discriminator.Phase discriminator is sampled to input clock and feedback clock, is compared, and comparative result is exported to DLL controller.DLL controller, according to the time delay of comparative result adjustment Variable delay chain, realizes the phase alignment of feedback clock and input clock, thus realizes the output clock with input clock with specific delay requirement.
In the specific implementation of DLL time delay chain, consider that system requires to have longer delay length and less delay stepsize to time delay chain simultaneously, DLL time delay chain is divided into DLL coarse adjustment chain and DLL to finely tune chain usually.Coarse delay chain circuit is by the control of DLL controller circuitry coarse adjustment control bit signal, the even clock and the strange clock signal that produce two outs of phase export to fine setting chain circuit, the phase difference of these two clock signals i.e. step-length t of coarse tuning circuit for this reason, fine setting chain circuit is simultaneously also by DLL control circuit vernier control position signal controlling, carry out delay with comprehensive to two input clock signals, generation precision is the Single-end output clock of t/n (n is the figure place of fine setting chain circuit).The phase accuracy of this signal is the degree of regulation of DLL circuit.
In existing DLL structure, in order to obtain more high-precision clock, often needing the figure place increasing DLL fine setting chain to realize, needing larger power consumption and chip area.
Summary of the invention
The utility model provides a kind of delay locked loop, under the prerequisite of the least possible increase chip area and power consumption, delay locked loop precision is improved at least one times.
Concrete technical solution of the present invention is as follows:
This delay locked loop comprises DLL time delay chain, described DLL time delay chain comprises DLL coarse adjustment chain and DLL and finely tunes chain, and described DLL coarse adjustment chain and DLL finely tune the intermediate phase generator of the intermediate phase clock be provided with between chain for generation of the strange clock of input clock signal and even clock.
Described intermediate phase generator comprises the first inverter for receiving strange clock signal and the second inverter for receiving even clock signal, the output of the first inverter is connected with the input of strange delay clock processing unit and middle delay process unit respectively, and the output of the second inverter is connected with the input of even delay clock processing unit and middle delay process unit respectively; The output of described strange delay clock processing unit, even delay clock processing unit is connected with the 3rd inverter, and the output of middle delay process unit is connected with the 4th inverter; Described strange delay clock processing unit, even delay clock processing unit to be connected triple gate composition by the inverter of three series connection again; Described middle delay process unit comprises strange inverter group, even inverter group, inverter and triple gate, the input of strange inverter group is connected with the output of the first inverter, output is connected with the input of inverter, the input of even inverter group is connected with the output of the second inverter, output is connected with the input of inverter, and the output of inverter is connected with triple gate; The inverter composition that described strange inverter group and even inverter group are connected by two.
The inverter of described first inverter, the second inverter and strange delay clock processing unit, even delay clock processing unit, middle delay process unit is identical, the triple gate of strange delay clock processing unit, even delay clock processing unit, middle delay process unit is identical, and the 3rd inverter is identical with the 4th inverter.
The utility model has the advantage of:
Delay locked loop precision, under the prerequisite of the least possible increase chip area and power consumption, is improved at least one times by the delay locked loop that the utility model provides.
Accompanying drawing explanation
Fig. 1 is existing delay locked loop principle schematic;
Fig. 2 is the utility model delay locked loop principle schematic;
Fig. 3 is the structure chart of intermediate phase generator;
Fig. 4 is waveform schematic diagram;
Fig. 5 is signal corresponding relation figure;
Description of reference numerals:
0-the second inverter; 1,2,3,11,12,13,14,15,21,22,23-inverter; 4,16,24-triple gate; 5-the three inverter; 17-the four inverter; 20-the first inverter.
Embodiment
Core of the present utility model is that the intermediate phase increased newly produces circuit, it is strange clock according to input and even clock that intermediate phase produces the effect of circuit, produce the clock of the two intermediate phase, the clock being t by original input phase difference becomes the clock of phase difference output t/2.The precision of former like this delay clock just can become t/2n from t/n accordingly, and precision doubles.
The even clock of input signal inputs to inverter 0, and the strange clock of input signal inputs to inverter 20 simultaneously; Even clock is by outputting to inverter 1,2,3 and inverter 11,12,13 simultaneously after inverter 0; Strange clock is by outputting to inverter 21,22,23 and inverter 14,15,13 simultaneously after inverter 20; Inverter 12,15 exports inverter 13 to simultaneously, produce one simultaneously by even clock and strange clock control and phase place in the middle of the two clock signal, delay clock in the middle of called after.
The output even delay clock of called after and the strange delay clock respectively of inverter 3 and 23, they input to triple gate 4 and 24 respectively.Triple gate 4 and 24 suspension control signal odd even is selected to control, and selects to export even delay clock or strange delay clock, increases driving force afterwards finally export odd clock signal by inverter 5.Wherein odd even selects signal to obtain in former DLL controller circuitry easily.Middle delay clock inputs to the triple gate of a conducting always equally, increases driving force afterwards finally export sampling clock signal by inverter 17.
In order to matching transmission time delay and even clock, very clock are to the Balance route of sampling clock, the device of same size all selected by inverter 0 ~ 3,11 ~ 15 and 20 ~ 23, triple gate 4,16 and 24 selects the device of same size, exports the device driving inverter 5 and 7 to select same size.
Be described below in conjunction with waveform schematic diagram:
Signal corresponding relation: clkeven: even clock, clkodd: strange clock, clkeb: even delay clock, clkmb: middle delay clock, clkob: strange delay clock, clkeo: odd clock, clkmid: sampling clock.
Clkeven with clkodd produces clkeb and clkob by identical time delay, and produces phase place between clkmb therebetween simultaneously.Clkeb and clkob is by selecting driver output clkeo, clkmb driver output clkmid.
Can find out, the phase difference of input clkeven and clkodd is originally t, and after intermediate phase generator circuitry, clkeo and the clkmid phase difference of output only becomes original half t/2.
DLL finely tunes chain can adopt traditional multiple circuit structure, its major function be two phase differences be the clock signal delay of t comprehensive after to be converted to a precision step-length be the clock signal of t/n, wherein n is fine setting chain circuit figure place.
The DLL of traditional DLL structure and improvement DLL structure can be adopted thus respectively to finely tune chain output signal eye pattern, and namely the precision of this output signal represents the output clock precision of whole DLL.As shown in Figure 5: the corresponding DLL traditional structure of upper side waveform, clkeven: even clock, clkodd: strange clock, clkfine: delay clock, lower side waveform correspondence inserts the DLL modified node method of intermediate phase generator, clkeo: odd clock, clkmid: sampling clock, clkfine: delay clock.
As can be seen from eye pattern, when adopting DLL traditional structure, the phase difference of clkeven and clkodd is t, and the precision step-length exporting delay clock is t/n; And when adopting the DLL structure improved, the phase difference of clkeo and clkmid is t/2, and exporting the precision step-length of delay clock is t/2n.
Claims (3)
1. a delay locked loop, comprise DLL time delay chain, described DLL time delay chain comprises DLL coarse adjustment chain and DLL and finely tunes chain, it is characterized in that: described DLL coarse adjustment chain and DLL finely tune the intermediate phase generator of the intermediate phase clock be provided with between chain for generation of the strange clock of input clock signal and even clock.
2. delay locked loop according to claim 1, it is characterized in that: described intermediate phase generator comprises the first inverter for receiving strange clock signal and the second inverter for receiving even clock signal, the output of the first inverter is connected with the input of strange delay clock processing unit and middle delay process unit respectively, and the output of the second inverter is connected with the input of even delay clock processing unit and middle delay process unit; The output of described strange delay clock processing unit, even delay clock processing unit is connected with the 3rd inverter, and the output of middle delay process unit is connected with the 4th inverter; Described strange delay clock processing unit, even delay clock processing unit to be connected triple gate composition by the inverter of three series connection again; Described middle delay process unit comprises strange inverter group, even inverter group, inverter and triple gate, the input of strange inverter group is connected with the output of the first inverter, output is connected with the input of inverter, the input of even inverter group is connected with the output of the second inverter, output is connected with the input of inverter, and the output of inverter is connected with triple gate; The inverter composition that described strange inverter group and even inverter group are connected by two.
3. delay locked loop according to claim 2, it is characterized in that: the inverter of described first inverter, the second inverter and strange delay clock processing unit, even delay clock processing unit, middle delay process unit is identical, the triple gate of strange delay clock processing unit, even delay clock processing unit, middle delay process unit is identical, and the 3rd inverter is identical with the 4th inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420433498.6U CN204119210U (en) | 2014-08-01 | 2014-08-01 | A kind of delay locked loop |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420433498.6U CN204119210U (en) | 2014-08-01 | 2014-08-01 | A kind of delay locked loop |
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| CN204119210U true CN204119210U (en) | 2015-01-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124964B (en) * | 2014-08-01 | 2017-08-25 | 西安紫光国芯半导体有限公司 | A kind of delay locked loop and the method for improving delay locked loop precision |
-
2014
- 2014-08-01 CN CN201420433498.6U patent/CN204119210U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124964B (en) * | 2014-08-01 | 2017-08-25 | 西安紫光国芯半导体有限公司 | A kind of delay locked loop and the method for improving delay locked loop precision |
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| C14 | Grant of patent or utility model | ||
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150121 Effective date of abandoning: 20170825 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20150121 Effective date of abandoning: 20170825 |