CN104124964B - A kind of delay locked loop and the method for improving delay locked loop precision - Google Patents
A kind of delay locked loop and the method for improving delay locked loop precision Download PDFInfo
- Publication number
- CN104124964B CN104124964B CN201410376028.5A CN201410376028A CN104124964B CN 104124964 B CN104124964 B CN 104124964B CN 201410376028 A CN201410376028 A CN 201410376028A CN 104124964 B CN104124964 B CN 104124964B
- Authority
- CN
- China
- Prior art keywords
- clock
- delay
- phase inverter
- strange
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Abstract
The present invention provides a kind of delay locked loop and the method for improving delay locked loop precision, on the premise of increase chip area and power consumption as few as possible, and delay locked loop precision is improved at least one times.The delay locked loop includes DLL time delay chains, and the DLL time delay chains include DLL coarse adjustment chain and DLL fine setting chains, it is characterised in that：The intermediate phase generator of the intermediate phase clock for producing the strange clock of input clock signal and even clock is provided between DLL coarse adjustment chain and DLL the fine setting chain.The method of the raising delay locked loop precision is the even clock of two clock signals and strange clock by input to produce two clock signals, it is odd clock and sampling clock respectively, the phase difference of odd clock and sampling clock is the half of even clock and odd clock phases difference.
Description
Technical field
The present invention provides a kind of delay locked loop and the method for improving delay locked loop precision.
Background technology
Delay phase-locked loop (DLL) is widely used in interface and large-scale integrated between microprocessor, memory interface, chip
The clock distributing network of circuit, is used for clock synchronously to solve the skew problems of clock so that between chip internal or chip
Clock delay have enough surpluses, so as to improve the sequential function of system.
With the increase of application system clock frequency, the requirement more and more higher to DLL degrees of regulation, because it is directly determined
DLL maximum phase demodulation error.Traditional DLL by DLL time delay chains (including coarse adjustment chain and fine setting chain), delay of feedback, phase discriminator,
DLL controllers and output driver composition.Its operation principle is as follows：
DLL input clock produces delay clock after time delay chain, and delay clock produces feedback after delay of feedback
Clock, feedback clock is inputted to phase discriminator with input clock.Phase discriminator is sampled to input clock and feedback clock, compared
Compared with, and comparative result is exported give DLL controllers.DLL controllers adjust the delay of Variable delay chain according to comparative result, realize
The phase alignment of feedback clock and input clock, so as to realize the output clock that there is specific delay requirement with input clock.
In DLL time delay chains in the specific implementation, requiring that there is longer delay length simultaneously to time delay chain in view of system
With less delay stepsize, DLL time delay chains are generally divided into DLL coarse adjustment chain and DLL fine setting chains.Coarse delay chain circuit is controlled by DLL
The control of device circuit coarse adjustment control bit signal processed, the even clock and strange clock signal of two outs of phase of generation, which are exported, gives fine setting chain
Circuit, the phase difference of the two clock signals is the step-length t of this coarse tuning circuit, and fine setting chain circuit is also controlled electricity by DLL simultaneously
Two input clock signals are postponed and integrated by the signal control of road vernier control position, and generation precision is that (n is fine setting chain to t/n
The digit of circuit) Single-end output clock.The phase accuracy of this signal is the degree of regulation of DLL circuit.
In existing DLL structures, in order to obtain the clock of higher precision, the digit for generally requiring to increase DLL fine setting chains is come
Realize, it is necessary to larger power consumption and chip area.
The content of the invention
The present invention provides a kind of delay locked loop and the method for improving delay locked loop precision, in increase version as few as possible
On the premise of the area of pictural surface and power consumption, delay locked loop precision is improved at least one times.
The particular technique solution of the present invention is as follows：
The delay locked loop includes DLL time delay chains, and the DLL time delay chains include DLL coarse adjustment chain and DLL fine setting chains, described
When the intermediate phase for producing the strange clock of input clock signal and even clock is provided between DLL coarse adjustment chain and DLL fine setting chains
The intermediate phase generator of clock.
The intermediate phase generator includes being used to receive the first phase inverter of strange clock signal and for receiving even clock
Second phase inverter of signal, the output end of the first phase inverter respectively with strange delay clock processing unit and middle delay process unit
Input connection, the output end of the second phase inverter is defeated with even delay clock processing unit and centre delay process unit respectively
Enter end connection；The strange delay clock processing unit, the output end of even delay clock processing unit and the connection of the 3rd phase inverter, in
Between delay process unit output end and the 4th phase inverter connection；The strange delay clock processing unit, even delay clock processing
Unit is connected triple gate composition again by the phase inverters of three series connection；The middle delay process unit includes strange phase inverter
Group, even phase inverter group, phase inverter and triple gate, the input of strange phase inverter group are connected with the output end of the first phase inverter, exported
End be connected with the input of phase inverter, the input of even phase inverter group is connected with the output end of the second phase inverter, output end and instead
The input connection of phase device, the output end of phase inverter is connected with triple gate；The strange phase inverter group and even phase inverter group are by two
The phase inverter composition of individual series connection.
First phase inverter, the second phase inverter and strange delay clock processing unit, even delay clock processing unit, centre
The phase inverter of delay process unit is identical, strange delay clock processing unit, even delay clock processing unit, middle delay process list
The triple gate of member is identical, and the 3rd phase inverter and the 4th phase inverter are identical.
The method of the raising delay locked loop precision comprises the following steps：By the even clock of two clock signals of input and
Strange clock produces two clock signals, is the phase difference of odd clock and sampling clock, odd clock and sampling clock respectively
It is the half of even clock and odd clock phases difference, i.e. original input phase difference is changed into phase difference output t/2's for t clock
Clock, the precision of former delay clock just can be changed into t/2n from t/n accordingly, and precision is doubled.
It is described that odd clock and sampling clock signal are produced by the two clock signals idol clock and strange clock of input
Specifically：
1] the even clock of input signal and the strange clock of input signal are inputted in different phase inverters respectively；
2] the even clock of the input signal for handling inverted device inputs even delay clock processing unit and middle delay respectively
Processing unit, the strange clock of input signal that inverted device is handled is inputted at strange delay clock processing unit and middle delay respectively
Manage unit；
3] clock signal for exporting even delay clock processing unit is believed with the clock that strange delay clock processing unit is exported
Number input simultaneously increases driving force into phase inverter and exports odd clock signal；
The strange clock of input signal and even clock for entering middle delay process unit in step 2 enter after same phase inverter
The clock signal of generation one simultaneously by even clock and strange clock control and phase in the middle of the two, is named as centre and prolongs
Shi Shizhong, the delay clock is inputted to a constantly on triple gate, increases driving force most by phase inverter again afterwards
Sampling clock signal is exported eventually.
The advantage of the invention is that：
Delay locked loop and improve the method for delay locked loop precision in increase domain as few as possible that the present invention is provided
On the premise of area and power consumption, delay locked loop precision is improved at least one times.
Brief description of the drawings
Fig. 1 is existing delay locked loop principle schematic；
Fig. 2 is delay locked loop principle schematic of the present invention；
Fig. 3 is the structure chart of intermediate phase generator；
Fig. 4 is waveform diagram；
Fig. 5 is signal corresponding relation figure；
Description of reference numerals：
0-the second phase inverter；1st, 2,3,11,12,13,14,15,21,22,23-phase inverter；4th, 16,24-triple gate；
5-the three phase inverter；17-the four phase inverter；20-the first phase inverter.
Embodiment
The core of the present invention is newly-increased intermediate phase generation circuit, and the effect of intermediate phase generation circuit is according to defeated
The strange clock and even clock entered, produces the clock of the two intermediate phase, and original input phase difference is changed into defeated for t clock
Go out phase difference t/2 clock.The precision of so former delay clock just can be changed into t/2n from t/n accordingly, and precision is doubled.
Input signal idol clock is inputted to phase inverter 0, while the strange clock of input signal is inputted to phase inverter 20；Even clock leads to
Cross after phase inverter 0 while being output to phase inverter 1,2,3 and phase inverter 11,12,13；Strange clock after phase inverter 20 by exporting simultaneously
To phase inverter 21,22,23 and phase inverter 14,15,13；Phase inverter 12,15 is exported to phase inverter 13 simultaneously, produce one simultaneously by
The clock signal of even clock and strange clock control and phase in the middle of the two, is named as middle delay clock.
The output of phase inverter 3 and 23 is respectively designated as even delay clock and strange delay clock, and they are separately input into tri-state
Door 4 and 24.The selection control of the suspension control signal odd even of triple gate 4 and 24, the even delay clock of selection output or strange delay clock, afterwards
Driving force final output odd clock signal is increased by phase inverter 5.Wherein odd even selection signal can be easily in original
Obtained in DLL controller circuitrys.Middle delay clock is equally inputted to a constantly on triple gate, passes through phase inverter afterwards
17 increase driving force final output sampling clock signals.
In order to which matching transmission delay and even clock, strange clock are to the Balance route of sampling clock, phase inverter 0~3,11~15
With 20~23 devices for selecting identical size, triple gate 4,16 and the device of the 24 identical sizes of selection, output driving phase inverter 5
With the device of the 7 identical sizes of selection.
It is described below in conjunction with waveform diagram：
Signal corresponding relation：clkeven：Even clock, clkodd：Strange clock, clkeb：Even delay clock, clkmb：It is middle
Delay clock, clkob：Strange delay clock, clkeo：Odd clock, clkmid：Sampling clock.
Clkeven and clkodd produces clkeb and clkob by identical delay, and produces phase simultaneously between the two
Between clkmb.Clkeb and clkob is by selecting driving output clkeo, clkmb driving output clkmid.
As can be seen that input clkeven and clkodd phase difference sheet is t, it is defeated after intermediate phase generator circuitry
Clkeo the and clkmid phase differences gone out are only changed into original half t/2.
DLL fine settings chain can use traditional a variety of circuit structures, and its major function is that two phase differences are believed for t clock
The clock signal that a precision step-length is t/n is converted to after number delay is comprehensive, wherein n is fine setting chain circuit digit.
It is hereby achieved that traditional DLL structures are respectively adopted and the DLL fine setting chain output signal eye patterns of DLL structures are improved,
The precision of this output signal is the output clock accuracy for representing whole DLL.As shown in Figure 5：Upper side waveform correspondence DLL conventional junctions
Structure, clkeven：Even clock, clkodd：Strange clock, clkfine：Delay clock, lower side waveform correspondence insertion intermediate phase is produced
The DLL improved structures of device, clkeo：Odd clock, clkmid：Sampling clock, clkfine：Delay clock.
From eye pattern as can be seen that during using DLL traditional structures, clkeven and clkodd phase difference are t, output delay
The precision step-length of clock is t/n；And when using improved DLL structures, clkeo and clkmid phase difference are t/2, output delay
The precision step-length of clock is t/2n.
Claims (3)
1. a kind of delay locked loop, including DLL time delay chains, the DLL time delay chains include DLL coarse adjustment chain and DLL fine setting chains, it is special
Levy and be：It is provided between DLL coarse adjustment chain and DLL the fine setting chain for producing the strange clock of input clock signal and even clock
The intermediate phase generator of intermediate phase clock；
The intermediate phase generator includes being used to receive the first phase inverter of strange clock signal and for receiving even clock signal
The second phase inverter, the output end of the first phase inverter is defeated with strange delay clock processing unit and middle delay process unit respectively
Enter end connection, the output end of the second phase inverter and the input of even delay clock processing unit and middle delay process unit connect
Connect；The strange delay clock processing unit, the output end of even delay clock processing unit and the connection of the 3rd phase inverter, centre delay
The output end of processing unit is connected with the 4th phase inverter；The strange delay clock processing unit, even delay clock processing unit are equal
It is made up of a phase inverters triple gate of connecting again for three series connection；The middle delay process unit includes strange phase inverter group, idol
Phase inverter group, phase inverter and triple gate, the input of strange phase inverter group are connected with the output end of the first phase inverter, output end with it is anti-
The input connection of phase device, the input of even phase inverter group is connected with the output end of the second phase inverter, output end and phase inverter
Input is connected, and the output end of phase inverter is connected with triple gate；The strange phase inverter group and even phase inverter group are by two series connection
Phase inverter composition.
2. delay locked loop according to claim 1, it is characterised in that：First phase inverter, the second phase inverter and strange
Delay clock processing unit, even delay clock processing unit, middle delay process unit phase inverter it is identical, at strange delay clock
Manage unit, even delay clock processing unit, middle delay process unit triple gate it is identical, the 3rd phase inverter and the 4th phase inverter
It is identical.
3. a kind of method for improving delay locked loop precision, it is characterised in that comprise the following steps：Pass through two clocks of input
Signal idol clock and strange clock produce two clock signals, are odd clock and sampling clock signal respectively, odd clock and
The phase difference of sampling clock signal is the half of even clock and odd clock phases difference, makes the precision of former delay clock corresponding by t/
N is changed into t/2n, wherein, t is the step-length of coarse tuning circuit, and n is the digit of fine setting chain circuit；
The even clock of two clock signals by input and strange clock are specific to produce odd clock and sampling clock signal
It is：
Step 1 inputs the even clock of input signal and the strange clock of input signal in different phase inverters respectively；
The even clock of input signal that step 2 handles inverted device is inputted at even delay clock processing unit and middle delay respectively
Unit is managed, the strange clock of input signal that inverted device is handled inputs strange delay clock processing unit and middle delay process respectively
Unit；
The clock signal that the clock signal that step 3 exports even delay clock processing unit is exported with strange delay clock processing unit
Input simultaneously increases driving force into phase inverter and exports odd clock signal；Enter middle delay process unit in step 2
The strange clock of input signal and even clock enter after same phase inverter generation one simultaneously by even clock and strange clock control and
Clock signal of the phase in the middle of the two, is named as middle delay clock, the delay clock input to one it is constantly on
Triple gate, afterwards again pass through phase inverter increase driving force final output sampling clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410376028.5A CN104124964B (en) | 2014-08-01 | 2014-08-01 | A kind of delay locked loop and the method for improving delay locked loop precision |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410376028.5A CN104124964B (en) | 2014-08-01 | 2014-08-01 | A kind of delay locked loop and the method for improving delay locked loop precision |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124964A CN104124964A (en) | 2014-10-29 |
| CN104124964B true CN104124964B (en) | 2017-08-25 |
Family
ID=51770245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410376028.5A Active CN104124964B (en) | 2014-08-01 | 2014-08-01 | A kind of delay locked loop and the method for improving delay locked loop precision |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124964B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716955B (en) * | 2015-03-25 | 2018-10-02 | 华为技术有限公司 | A kind of time-to-digit converter in phaselocked loop |
| CN105281755B (en) * | 2015-11-17 | 2018-05-08 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop and its filtering more new control method |
| CN105743463B (en) * | 2016-03-16 | 2019-03-01 | 珠海全志科技股份有限公司 | Clock duty cycle calibration and frequency multiplier circuit |
| CN110212912B (en) * | 2019-06-06 | 2020-07-03 | 复旦大学 | Multiple delay phase-locked loop with high-precision time-to-digital converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951260A (en) * | 2010-10-11 | 2011-01-19 | 上海电力学院 | Digital delay phase locked loop circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN204119210U (en) * | 2014-08-01 | 2015-01-21 | 西安华芯半导体有限公司 | A kind of delay locked loop |
-
2014
- 2014-08-01 CN CN201410376028.5A patent/CN104124964B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951260A (en) * | 2010-10-11 | 2011-01-19 | 上海电力学院 | Digital delay phase locked loop circuit |
| CN103684438A (en) * | 2013-11-25 | 2014-03-26 | 龙芯中科技术有限公司 | Delay locked loop |
| CN204119210U (en) * | 2014-08-01 | 2015-01-21 | 西安华芯半导体有限公司 | A kind of delay locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124964A (en) | 2014-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104124964B (en) | A kind of delay locked loop and the method for improving delay locked loop precision | |
| US11003203B2 (en) | Circuits for and methods of calibrating a circuit in an integrated circuit device | |
| CN105743463B (en) | Clock duty cycle calibration and frequency multiplier circuit | |
| CN106374890B (en) | A kind of clock duty correction circuit | |
| US10712770B1 (en) | Clock phase aligner for high speed data serializers | |
| CN103427798B (en) | A kind of multiphase clock generation circuit | |
| CN103502965A (en) | Inter-channel skew adjustment circuit | |
| CN103546151B (en) | High-speed DLL (Delay-locked loop) | |
| CN105099446A (en) | Phase-locked loop system | |
| CN103731136A (en) | Sequential equivalent sampling circuit and method based on delay signals | |
| CN104821802A (en) | Clock operation method and circuit | |
| US7659763B2 (en) | Conditioning input buffer for clock interpolation | |
| KR20220035243A (en) | Circuits and Methods for Calibrating Circuits in Integrated Circuit Devices | |
| CN106257835A (en) | A kind of 25% duty cycle clock signal produces circuit | |
| CN105827222A (en) | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus | |
| CN104820654B (en) | One kind delay adjuster | |
| CN204119210U (en) | A kind of delay locked loop | |
| CN106771990B (en) | Measuring circuit and measuring method for D trigger setup time | |
| CN104283550B (en) | A kind of delay phase-locked loop and dutycycle circuit for rectifying | |
| CN107395166A (en) | Clock duty cycle stabilizing circuit based on delay lock phase | |
| US20230121503A1 (en) | Calibration method, calibration device and multi-phase clock circuit | |
| CN104935253B (en) | Signal frequency multiplication circuit, method and the equipment being applicable in | |
| CN205407759U (en) | Clock duty cycle adjusting device | |
| CN106788403A (en) | A kind of large range high resolution rate delay control method for being applied to optical fiber time transmission | |
| US10454463B1 (en) | Adaptable quantizers having dedicated supply voltage for tail device drivers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |