CN103580681A - Phase-locked loop phase difference adjusting device - Google Patents
Phase-locked loop phase difference adjusting device Download PDFInfo
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- CN103580681A CN103580681A CN201210269962.8A CN201210269962A CN103580681A CN 103580681 A CN103580681 A CN 103580681A CN 201210269962 A CN201210269962 A CN 201210269962A CN 103580681 A CN103580681 A CN 103580681A
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Abstract
The invention provides a phase-locked loop phase difference adjusting device which comprises a phase difference detection module, a data processing module, and a digital-to-analog conversion module. A phase-locked loop inputting clock and a phase-locked loop output clock are connected to the input end of the phase difference detection module, and are used for detecting the phase difference of the input clock and the output clock; the data processing module is connected to the phase difference detection module, converts the detected phase difference data in proportion into DAC_data and outputs the DAC_data; the digital-to-analog conversion module is connected to the data processing module, takes the DAC_data as input data and converts the DAC_data as output currents, and the output currents are used as the input of a phase-locked loop filter. The phase-locked loop phase difference adjusting device is used in cooperation with an existing phase-locked loop, can adjust the phase between the input clock and the output clock dynamically under the situation that the losing lock phenomenon of the phase-locked loop does not occur, and improves synchronism.
Description
Technical field
The present invention relates to the signal processing technology in communication, relate in particular to the device that phase-locked loop phase difference regulates.
Background technology
Phase-locked loop is widely used in broadcast communication, frequency synthesis, automatically controls and the technical field such as clock synchronous.By phase discriminator, loop filter and voltage controlled oscillator, formed.Phase discriminator is used for differentiating the phase difference between input signal Ui and output signal U o, and output error voltage Ud.Noise and Interference composition in Ud, by the loop filter filtering of low pass character, forms the control voltage U c of voltage controlled oscillator (VCO).The result that Uc acts on voltage controlled oscillator is output clock and the input clock constant phase difference that makes phase-locked loop, thereby loop is locked, is called into lock.In common phase-locked loop, while entering to lock, the phase difference of input clock and output clock is uncontrollable at every turn, enters the rear phase difference of lock and remains unchanged.
Phase difference size between phase-locked loop input clock and output clock is an important technology index of phase-locked loop.Under current technology, the phase difference between common phase-locked loop input, output is larger, far can not meet the phase difference requirement in practical application.In addition, at present common phase-locked loop only just can start phase place adjustment in the situation that of losing lock, in losing lock situation, can not dynamically not adjust, and for the product of a lot of use phase-locked loops, losing lock can affect the normal operation of product, is unacceptable.This has directly affected the application in the field that phase-locked loop has relatively high expectations in numerous synchronisms.
Summary of the invention
The object of this invention is to provide a kind of phase-locked loop phase difference adjusting device, be used in conjunction with existing phase-locked loop, can not adjust the phase difference between input, output clock losing lock in the situation that at phase-locked loop, can, by adjusting offset in 80ps, improve synchronism.
In order to solve the problems of the technologies described above, the present invention has adopted following technological means: a kind of phase-locked loop phase difference adjusting device, comprise phase difference detection module, phase-locked loop input clock and output clock are connected to the input of phase difference detection module, for detection of the phase difference of described input clock and output clock;
Data processing module, connects described phase difference detection module, and detected described phase data is converted in proportion and exports data DAC_data;
D/A converter module, connects described data processing module, and using described DAC_data as input data, is converted to output current, as the input of described cycle of phase-locked loop filter.
Further, described phase difference detection module forms a carry chain by n parallel data output channel, and n is natural number.
Further, described each circuit-switched data output channel comprises a carry multiplexer MUXCY and a d type flip flop.
Further, the span of described n is: n>=1/f
1* Δ t, wherein f
1for the frequency of the output clock of phase-locked loop, the time delay between the input and output that Δ t is MUXCY.
The present invention is owing to adopting the above technical scheme, and the phase-locked loop that described phase-locked loop phase difference adjusting device can be different with form is used in conjunction with, and does not need to change the framework of original phase-locked loop; And this device can not losing lock in the situation that, dynamically adjust the phase place between phase-locked loop input clock and output clock at phase-locked loop, effectively prevent the appearance of phase-locked loop losing lock situation, and effectively improve the synchronism between phase-locked loop input clock and output clock.
Accompanying drawing explanation
Phase-locked loop phase difference adjusting device of the present invention is provided in detail by following embodiment and accompanying drawing.
Fig. 1 is the system construction drawing of embodiment of the present invention phase-locked loop phase difference adjusting device and phase-locked loop;
Fig. 2 is embodiment of the present invention phase-locked loop phase difference adjusting device structural representation;
Phase detecting module structural representation in Fig. 3 embodiment of the present invention.
Embodiment
Below will be described in further detail phase-locked loop phase difference adjusting device of the present invention.
As shown in Figure 1, phase-locked loop 10 and phase-locked loop phase difference adjusting device 20 have been comprised.
Phase-locked loop 10 has also comprised phase discriminator 11, loop filter 12, voltage controlled oscillator 13, and frequency divider 14.Phase discriminator 11 is used for differentiating the phase difference between input signal and output signal, and output error voltage.Noise and Interference composition in error voltage, by loop filter 12 filterings, forms the control voltage of voltage controlled oscillator 13.Controlling the result that voltage acts on voltage controlled oscillator 13 is that its output clock is pulled to loop filter 12 input clocks by frequency divider 14, and when the two phase difference is fixedly time, loop is locked, is called into lock.
As shown in Figure 2 a, described phase difference adjusting device 20 also comprises phase difference detection module 21, phase-locked loop 10 input clock Tin and output clock Tout are connected to the input of phase difference detection module 21, for detection of the phase difference of described input clock Tin and output clock Tout.
As shown in Figure 3, in described phase difference detection module 21, the Tin of the Tout using the frequency of the output clock of described phase-locked loop 10 as described phase difference detection module 21 using the frequency of the input clock of described phase-locked loop 10 as described phase difference detection module 21; Described phase difference detection module 21 is comprised of n data output channel Dn arranged side by side, and described data output channel Dn comprises that carry multiplexer MUXCY and a d type flip flop form.Described phase difference detection module 21 removes to gather n the signal C[1 of Tin after 1 to n multiplexer time delay at the rising edge of Tout]～C[n], obtain n position phase data D[1] and～D[n].Wherein n is natural number, and its span is: n>=1/f
1* Δ t, f
1for the frequency of the output clock of phase-locked loop, the time delay between the input and output that Δ t is MUXCY.Tout is very little to the cabling time delay of each d type flip flop, is approximately 0ps, and Tin is Δ t*n to the time delay of n MUXCY.As D[m-1]=1 and D[m]=0 time, can judge the rising edge that has collected Tin with the rising edge of Tout, the rising edge that can calculate thus Tout lags behind the rising edge m* Δ t of Tin, m* Δ t is exactly phase difference.The Δ t of MUXCY in main flow FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) is less than 40ps at present, and last Tout and Tin phase difference detection precision are 2* Δ t, and phase difference can be adjusted in 80ps.
Data processing module 22, connects described phase difference detection module 21, and detected described phase difference m* Δ t is converted in proportion and exports data DAC_data; Described ratio is determined by the parameter of DAC (digital to analog converter) and described voltage controlled oscillator 13.
D/A converter module 23, connects described data processing module 22, and using described DAC_data as input signal, is converted to output current Iout, as the input of described cycle of phase-locked loop filter.
As shown in Figure 2 b, in different embodiment, D/A converter module 23 can be converted to input signal output voltage U out according to actual needs, in described D/A converter module 23, connect again a voltage/current conversion circuit 24, output current Iout, as the input of described cycle of phase-locked loop filter.
In the present invention, phase-locked loop phase difference adjusting device 20 can, by being connected to upper type on described phase-locked loop 10, therefore, not need to change or destroy the framework of original phase-locked loop; On the other hand, by phase-locked loop phase difference adjusting device 20, dynamically adjust phase difference, realized better synchronous.
Owing to these are only preferred embodiment of the present invention; protection scope of the present invention should not be so limited; be that every simple equivalence of doing according to claims of the present invention and description of the present invention changes and modifies, all should still remain within the scope of the patent.
Claims (4)
1. a phase-locked loop phase difference adjusting device, comprises phase-locked loop input clock and output clock, characterized by further comprising:
Phase difference detection module, described phase-locked loop input clock and output clock are connected to the input of phase difference detection module, for detection of the phase difference of described input clock and output clock;
Data processing module, connects described phase difference detection module, and detected described phase data is converted in proportion and exports data DAC_data;
D/A converter module, connects described data processing module, and using described DAC_data as input data, is converted to output current, as the input of described cycle of phase-locked loop filter.
2. phase-locked loop phase difference adjusting device as claimed in claim 1, is characterized in that, described phase difference detection module forms a carry chain by n parallel data output channel, and n is natural number.
3. phase-locked loop phase difference adjusting device as claimed in claim 2, is characterized in that, described each circuit-switched data output channel comprises a carry multiplexer MUXCY and a d type flip flop.
4. phase-locked loop phase difference adjusting device as claimed in claim 3, is characterized in that, the span of described n is: n>=1/f
1* Δ t, wherein f
1for the frequency of the output clock of phase-locked loop, the time delay between the input and output that Δ t is described MUXCY.
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| CN201210269962.8A CN103580681B (en) | 2012-07-31 | 2012-07-31 | Phase-locked loop phase difference adjusting device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111256836A (en) * | 2020-03-19 | 2020-06-09 | 广州赛恩科学仪器有限公司 | Infrared temperature measurement real-time recording sensing system based on phase-locked capture technology |
| CN111446957A (en) * | 2020-04-21 | 2020-07-24 | 哈尔滨工业大学 | Multi-P LL parallel output clock synchronization system and working method thereof |
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| US7138841B1 (en) * | 2003-12-23 | 2006-11-21 | Cypress Semiconductor Corp. | Programmable phase shift and duty cycle correction circuit and method |
| US20070109030A1 (en) * | 2004-04-26 | 2007-05-17 | Samsung Electronics Co., Ltd. | Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics |
| CN101176258A (en) * | 2005-06-17 | 2008-05-07 | 三星电子株式会社 | Phase locked loop and receiver using the same, phase detecting method |
| CN102468844A (en) * | 2010-11-11 | 2012-05-23 | 晨星软件研发(深圳)有限公司 | Phase-locked loop |
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2012
- 2012-07-31 CN CN201210269962.8A patent/CN103580681B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138841B1 (en) * | 2003-12-23 | 2006-11-21 | Cypress Semiconductor Corp. | Programmable phase shift and duty cycle correction circuit and method |
| US20070109030A1 (en) * | 2004-04-26 | 2007-05-17 | Samsung Electronics Co., Ltd. | Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics |
| CN101176258A (en) * | 2005-06-17 | 2008-05-07 | 三星电子株式会社 | Phase locked loop and receiver using the same, phase detecting method |
| CN102468844A (en) * | 2010-11-11 | 2012-05-23 | 晨星软件研发(深圳)有限公司 | Phase-locked loop |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111256836A (en) * | 2020-03-19 | 2020-06-09 | 广州赛恩科学仪器有限公司 | Infrared temperature measurement real-time recording sensing system based on phase-locked capture technology |
| CN111446957A (en) * | 2020-04-21 | 2020-07-24 | 哈尔滨工业大学 | Multi-P LL parallel output clock synchronization system and working method thereof |
| CN111446957B (en) * | 2020-04-21 | 2023-05-09 | 哈尔滨工业大学 | Multi-PLL parallel output clock synchronization system and working method thereof |
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Address after: 201815 Shanghai city Jiading Industrial Zone No. 1180 Building 8 Xing Xian Lu Patentee after: Shanghai Lianying Medical Technology Co., Ltd Address before: 201815 Shanghai city Jiading Industrial Zone No. 1180 Building 8 Xing Xian Lu Patentee before: SHANGHAI UNITED IMAGING HEALTHCARE Co.,Ltd. |
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Address after: 201807 2258 Chengbei Road, Jiading District, Shanghai Patentee after: Shanghai Lianying Medical Technology Co.,Ltd. Address before: Building 8, 1180 Xingxian Road, Jiading Industrial Zone, Shanghai, 201815 Patentee before: Shanghai Lianying Medical Technology Co.,Ltd. |