CN103579134B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN103579134B
CN103579134B CN201210270391.XA CN201210270391A CN103579134B CN 103579134 B CN103579134 B CN 103579134B CN 201210270391 A CN201210270391 A CN 201210270391A CN 103579134 B CN103579134 B CN 103579134B
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semiconductor
semiconductor package
circuit
packing colloid
adhesion coating
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CN103579134A (zh
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张江城
李孟宗
黄荣邦
邱世冠
黄富堂
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：封装胶体，其具有相对的顶面和底面；嵌设于该封装胶体中的至少一半导体组件，其具有相对的第一表面与第二表面，且该第一表面外露出该封装胶体底面；聚合物层，其形成于该半导体组件与封装胶体之间，并延伸至该封装胶体底面上；以及线路增层结构，其形成于该半导体组件的第一表面上。以避免封装模压时半导体组件偏移，以提升后续工艺的对位精准度。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，特别是关于一种覆晶式半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，现今电子产品均朝向微型化、多功能、高电性及高速运作的方向发展。例如，随着前端半导体芯片工艺的集成化，半导体芯片的主动面上形成有密集的电极垫，以提供信号的输入/输出(I/O)。为了配合此发展趋势，后端半导体从业者则积极研发能顺利用互连结构将该等电极垫传输的信号扇出的半导体封装件，例如扇出式晶圆级芯片规模封装件。
在是种封装件中，如芯片的半导体组件通常借由一封装胶体镶嵌至一承载件。之后，该承载件会被移除，并在该半导体组件上形成互连结构。如图3A所示的封装胶体形成过程中，于承载件30整表面上形成粘着层32，接着，于该粘着层32上的预定位置A设置半导体组件36。之后，如图3B所使示，于该粘着层32上形成封装胶体37，以包覆该半导体组件36。然而，因进行模压时的温度变化，使得粘着层32发生伸缩，导致半导体组件36偏离预定位置A，影响模压以及后续工艺的对位精准度，例如，形成于该半导体组件上的增层线路无法电性连接该半导体组件，使产品良率降低。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺点，本发明的主要目的在于提供一种半导体封装件及其制法，可避免封装模压时半导体组件偏移，以提升后续工艺的对位精准度。
本发明的半导体封装件，包括：封装胶体，其具有相对的顶面和底面；嵌设于该封装胶体中的至少一半导体组件，其具有相对的第一表面与第二表面，且该第一表面外露出该封装胶体；聚合物层，其形成于该半导体组件与封装胶体之间，并延伸至该封装胶体底面上；以及线路增层结构，其形成于该半导体组件的第一表面上。
本发明还提供一种半导体封装件的制法，其包括：提供一表面上设有至少一半导体组件的承载件，其中，该半导体组件借由粘着层贴附于该承载件上，以使该承载件的部份表面显露于外；形成封装胶体，以包覆该半导体组件，其中，该封装胶体具有相对的顶面和与该粘着层同侧的底面；移除该粘着层和承载件，以外露出该半导体组件；以及于该外露的半导体组件上形成线路增层结构。
于一具体实施例中，前述半导体封装件的制法还包括于形成该封装胶体之前，于该显露的承载件表面及半导体组件表面上形成聚合物层，则该封装胶体形成于该聚合物层上。
前述半导体封装件的制法中，该半导体组件的设置包括下列步骤：于承载件的整表面上形成粘着层；于该粘着层上设置至少一半导体组件，并外露出部分该粘着层；以及移除外露的该粘着层。
此外，于一具体实施例中，于设置该至少一半导体组件之前，以屏蔽遮盖住部分该粘着层，以外露出该半导体组件的设置位置；以及对该半导体组件的设置位置照光。
相比于现有技术，本发明利用感旋光性的粘着层，使其形成多个分离的粘着层单元，避免温度变化时伸缩而相互影响，再于该显露的承载件表面及半导体组件表面上形成聚合物层，以固定该半导体组件，避免进行封装模压时造成半导体组件的偏移，以提升后续工艺的对位精准度，改善工艺良率。
附图说明
图1A至图1I，其为本发明的半导体封装件的第一实施例的制法的剖面示意图，其中，图1A至图1D，用于说明于承载件表面上设置半导体组件的方法；图1F’至图1I’用于说明无聚合物层的半导体封装件的制法；
图2A至图2F，其为本发明的半导体封装件的第二实施例的剖面示意图；以及
图3A及图3B为现有半导体封装件的制法的剖面示意图。
主要组件符号说明
10,30 承载件
12,32 粘着层
14 屏蔽
16,36 半导体组件
16a 第一表面
16b 第二表面
161 电极垫
18 聚合物层
20,37 封装胶体
20a 顶面
20b 底面
21 线路增层结构
211 介电层
212 增层线路
213 导电盲孔
214 电性连接垫
22 导电组件
201 穿孔
23 导电柱
24 导电迹线
25 绝缘层
A 预定位置。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“前”、“后”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。例如，本发明中，第一表面的“第一”是指形成电极垫的表面，而非限定所有半导体组件的第一表面皆为相同的用途。
请参阅图1A至图1I，其为本发明的半导体封装件的第一实施例的制法的剖面示意图。
请参阅图1A至图1D，其说明于承载件表面上设置半导体组件的方法，其中，该半导体组件借由粘着层贴附于该承载件上，且该承载件的部份表面显露于外。
如图1A所示，于例如基板的承载件10的整表面上形成粘着层12。
接着，如图1B所示，以屏蔽14遮盖住部分该粘着层12，以外露出该半导体组件的设置位置，以及对该半导体组件的设置位置照光。在本实施例中，该粘着层的材质为感旋光性粘着剂，例如照UV光可聚合的材料，使得未照光的部份可利用清洗液或显影液移除。
如图1C所示，于该粘着层12上设置至少一半导体组件16，并外露出部分该粘着层12。在本实施例中，设置三个半导体芯片，但不以此为限。此外，如图所示，该半导体组件16具有相对的第一表面16a与第二表面16b，该第一表面16a上具有多个电极垫161。
如图1D所示，移除外露的该粘着层12，使该粘着层12(此时为多个粘着层12)仅形成于该半导体组件16与承载件10之间。
如图1E所示，于该显露的承载件10表面及半导体组件16表面上形成例如聚酰亚胺的聚合物层18。
如图1F所示，于该聚合物层18上模压形成封装胶体20，以包覆该半导体组件16，其中，该封装胶体20具有相对的顶面20a和底面20b，该底面20b接触该聚合物层18。由于相邻半导体组件16之间的粘着层12被移除，且于该显露的承载件10表面及半导体组件16表面(包括侧面及第二表面16b)形成聚合物层18，可固定该半导体组件16于承载件10上，避免进行封装模压时造成半导体组件16的偏移，以提升后续工艺的对位精准度，改善工艺良率。
于图1F’所示的另一实施例中，该封装胶体20可直接形成于如图1D所示结构的承载件10表面上，由于该粘着层12仅形成于该半导体组件16与承载件10之间，可避免工艺期间两半导体组件16之间的粘着层12收缩，使半导体组件16的偏离原本位置，也可提升后续工艺的对位精准度。
如图1G所示，以机械方式及/或化学物质移除的方式，移除该粘着层12和承载件10，以外露出该半导体组件16，其中，该半导体组件16的第一表面16a外露出该聚合物层18。
如图1G’所示，该半导体组件16的第一表面16a外露出该封装胶体20。
如图1H所示，于该外露的半导体组件16上及封装胶体20底面20b上及聚合物层18上形成线路增层结构21。该线路增层结构21形成于该半导体组件16的第一表面16a上，且该线路增层结构21具有至少一介电层211、形成于该介电层211上的增层线路212、及形成于该介电层211中的导电盲孔213以电性连接该增层线路212和电极垫161。
此外，该线路增层结构21还具有外露的电性连接垫214，其电性连接该最外层的增层线路212，且前述的制法还包括于该电性连接垫214上形成如焊球的导电组件22。
接着，进行切单工艺，切割该封装胶体20、聚合物层18和线路增层结构21，即可得到如图1I所示的半导体封装件。
如图1H’和图1I’所示，用于显示未形成有聚合物层18的半导体封装件。
请参阅图2A至图2F，其为本发明的半导体封装件的第二实施例的剖面示意图。
如图2A所示，其接续图1F的步骤，于移除该粘着层12和承载件10之前，形成多个贯穿该封装胶体20和聚合物层18的穿孔201于该半导体组件16旁。若依据图1F’的步骤，该穿孔201则仅贯穿该封装胶体。
如图2B及图2C所示，于该穿孔201中形成导电柱23，再于该封装胶体20的顶面20a上形成电性连接该导电柱23的导电迹线24。具体而言，该导电柱的形成可于该封装胶体20表面和穿孔201内壁面形成晶种层(未图标)，再利用电镀法于该穿孔201中形成导电柱23。同样地，于封装胶体20的顶面20a上电镀形成导电迹线24。
如图2C所示，于该封装胶体20的顶面20a及导电迹线24上形成绝缘层25，其中，该绝缘层25外露部分导电迹线24。
如图2D所示，移除该粘着层12和承载件10，以外露出该半导体组件16，其中，该半导体组件16具有相对的第一表面16a与第二表面16b，该第一表面16a上具有多个电极垫161，且该第一表面16a外露出该聚合物层18。
如图2E所示，翻转该封装胶体20，于该外露的半导体组件16上形成线路增层结构21。该线路增层结构21形成于该半导体组件16的第一表面16a上，且该线路增层结构21具有至少一介电层211、形成于该介电层211上的增层线路212、及形成于该介电层211中的多个导电盲孔213以电性连接该增层线路212、电极垫161和导电柱23。
如图2F所示，该线路增层结构21还具有外露的电性连接垫214，且该制法还包括于该电性连接垫214上形成导电组件22。
接着，进行切单工艺，即可得到具有导电柱23的半导体封装件，并可借由该外露的部分导电迹线24接至其它电子组件，例如其它半导体封装件。
本发明提供一种半导体封装件，其包括：封装胶体20、嵌设于该封装胶体20中的至少一半导体组件16、聚合物层18、以及线路增层结构21。
所述的封装胶体20具有相对的顶面20a和底面20b。
所述的半导体组件16具有相对的第一表面16a与第二表面16b，且该第一表面16a外露出该封装胶体20。
所述的聚合物层18形成于该半导体组件16与封装胶体20之间，并延伸至该封装胶体20底面20b上，且该半导体组件16的第一表面16a与该聚合物层18形成一段差结构。
所述的线路增层结构21形成于该半导体组件16的第一表面16a上，其中，该半导体组件16的第一表面16a上具有多个电极垫161，且该线路增层结构21具有至少一介电层211、形成于该介电层211上的增层线路212、及形成于该介电层211中的导电盲孔213以电性连接该增层线路212和电极垫161。此外，该线路增层结构21还可具有外露的电性连接垫214，且该半导体封装件还包括导电组件22，形成于该电性连接垫214上。
于一具体实施例中，该半导体封装件还包括多个贯穿该封装胶体20和聚合物层18的穿孔201，且该穿孔201形成于该半导体组件16旁；形成于该穿孔201中的导电柱23；形成于该封装胶体20的顶面20a上且电性连接该导电柱23的导电迹线24；以及形成于该封装胶体20的顶面20a及导电迹线24上的绝缘层25。此实施例中，该半导体组件16的第一表面16a上具有多个电极垫161，且该线路增层结构21具有至少一介电层211、形成于该介电层211上的增层线路212、及形成于该介电层211中的多个导电盲孔213以电性连接该增层线路212、电极垫161和导电柱23。
综上所述，本发明利用感旋光性的粘着层，使其形成多个分离的粘着层单元，避免温度变化时伸缩而相互影响，再于该显露的承载件表面及半导体组件表面上形成聚合物层，以固定该半导体组件，避免进行封装模压时造成半导体组件的偏移，以提升后续工艺的对位精准度，改善工艺良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种半导体封装件，其包括：
封装胶体，其具有相对的顶面和底面；
嵌设于该封装胶体中的至少一半导体组件，其具有相对的第一表面与第二表面，且该第一表面外露出该封装胶体底面；
聚合物层，其形成于该半导体组件与封装胶体之间，且形成于该半导体组件的第二表面上并延伸至该封装胶体底面上；以及
线路增层结构，其形成于该半导体组件的第一表面上。
2.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件的第一表面上具有多个电极垫，且该线路增层结构具有至少一介电层、形成于该介电层上的增层线路、及形成于该介电层中的导电盲孔以电性连接该增层线路和电极垫。
3.根据权利要求1所述的半导体封装件，其特征在于，该线路增层结构还具有外露的电性连接垫，且该半导体封装件还包括导电组件，其形成于该电性连接垫上。
4.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括多个贯穿该封装胶体和聚合物层的穿孔，且该穿孔形成于该半导体组件旁；形成于该穿孔中的导电柱；形成于该封装胶体的顶面上且电性连接该导电柱的导电迹线；以及形成于该封装胶体的顶面及导电迹线上的绝缘层。
5.根据权利要求4所述的半导体封装件，其特征在于，该半导体组件的第一表面上具有多个电极垫，且该线路增层结构具有至少一介电层、形成于该介电层上的增层线路、及形成于该介电层中的多个导电盲孔以电性连接该增层线路、电极垫和导电柱。
6.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件的第一表面与该聚合物层形成一段差结构。
7.一种半导体封装件的制法，其包括：
提供一表面上设有至少一半导体组件的承载件，其中，该半导体组件具有相对的第一表面与第二表面，该第一表面上具有多个电极垫，该半导体组件的第一表面借由粘着层贴附于该承载件上，以使该半导体组件的第二表面显露于外；
于显露的该承载件表面及半导体组件的第二表面上形成聚合物层；
形成封装胶体，以包覆该半导体组件及聚合物层，其中，该封装胶体具有相对的顶面和与该粘着层同侧的底面；
移除该粘着层和承载件，以外露出该半导体组件及聚合物层；以及
于该外露的半导体组件上形成线路增层结构。
8.根据权利要求7所述的半导体封装件的制法，其特征在于，该半导体组件的设置包括下列步骤：
于承载件的整表面上形成粘着层；
于该粘着层上设置至少一半导体组件，并外露出部分该粘着层；以及
移除外露的该粘着层。
9.根据权利要求8所述的半导体封装件的制法，其特征在于，该半导体组件的设置还包括下列步骤：
于设置该至少一半导体组件之前，以屏蔽遮盖住部分该粘着层，以外露出该半导体组件的设置位置；以及
对该半导体组件的设置位置照光。
10.根据权利要求7所述的半导体封装件的制法，其特征在于，移除该粘着层和承载件后，该半导体组件的第一表面外露出该聚合物层。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，该线路增层结构形成于该半导体组件的第一表面上，且该线路增层结构具有至少一介电层、形成于该介电层上的增层线路、及形成于该介电层中的导电盲孔以电性连接该增层线路和电极垫。
12.根据权利要求7所述的半导体封装件的制法，其特征在于，该线路增层结构还具有外露的电性连接垫，且该制法还包括于该电性连接垫上形成导电组件。
13.根据权利要求7所述的半导体封装件的制法，其特征在于，该制法还包括于移除该粘着层和承载件之前，形成多个贯穿该封装胶体的穿孔于该半导体组件旁；于该穿孔中形成导电柱；于该封装胶体的顶面上形成电性连接该导电柱的导电迹线；以及于该封装胶体的顶面及导电迹线上形成绝缘层。
14.根据权利要求7所述的半导体封装件的制法，其特征在于，该制法还包括于移除该粘着层和承载件之前，形成多个贯穿该封装胶体和聚合物层的穿孔于该半导体组件旁；于该穿孔中形成导电柱；于该封装胶体的顶面上形成电性连接该导电柱的导电迹线；以及于该封装胶体的顶面及导电迹线上形成绝缘层。
15.根据权利要求7所述的半导体封装件的制法，其特征在于，该线路增层结构形成于该半导体组件的第一表面上，且该线路增层结构具有至少一介电层、形成于该介电层上的增层线路、及形成于该介电层中的多个导电盲孔以电性连接该增层线路、电极垫和导电柱。
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