CN103577627B - 捕获集成电路芯片与芯片封装体之间的互耦合效应 - Google Patents
捕获集成电路芯片与芯片封装体之间的互耦合效应 Download PDFInfo
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- CN103577627B CN103577627B CN201310322960.5A CN201310322960A CN103577627B CN 103577627 B CN103577627 B CN 103577627B CN 201310322960 A CN201310322960 A CN 201310322960A CN 103577627 B CN103577627 B CN 103577627B
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- chip
- parasite
- coupling
- packaging body
- design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/10—Noise analysis or noise optimisation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/561,760 | 2012-07-30 | ||
US13/561,760 US8640077B1 (en) | 2012-07-30 | 2012-07-30 | Capturing mutual coupling effects between an integrated circuit chip and chip package |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103577627A CN103577627A (zh) | 2014-02-12 |
CN103577627B true CN103577627B (zh) | 2016-12-28 |
Family
ID=49958104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310322960.5A Expired - Fee Related CN103577627B (zh) | 2012-07-30 | 2013-07-29 | 捕获集成电路芯片与芯片封装体之间的互耦合效应 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8640077B1 (zh) |
CN (1) | CN103577627B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10138749B2 (en) | 2016-03-16 | 2018-11-27 | United Technologies Corporation | Seal anti-rotation feature |
US10132184B2 (en) | 2016-03-16 | 2018-11-20 | United Technologies Corporation | Boas spring loaded rail shield |
US10513943B2 (en) | 2016-03-16 | 2019-12-24 | United Technologies Corporation | Boas enhanced heat transfer surface |
US10422240B2 (en) | 2016-03-16 | 2019-09-24 | United Technologies Corporation | Turbine engine blade outer air seal with load-transmitting cover plate |
US10563531B2 (en) | 2016-03-16 | 2020-02-18 | United Technologies Corporation | Seal assembly for gas turbine engine |
US10443424B2 (en) | 2016-03-16 | 2019-10-15 | United Technologies Corporation | Turbine engine blade outer air seal with load-transmitting carriage |
US10337346B2 (en) | 2016-03-16 | 2019-07-02 | United Technologies Corporation | Blade outer air seal with flow guide manifold |
US10161258B2 (en) | 2016-03-16 | 2018-12-25 | United Technologies Corporation | Boas rail shield |
US10138750B2 (en) | 2016-03-16 | 2018-11-27 | United Technologies Corporation | Boas segmented heat shield |
US10415414B2 (en) | 2016-03-16 | 2019-09-17 | United Technologies Corporation | Seal arc segment with anti-rotation feature |
US10443616B2 (en) | 2016-03-16 | 2019-10-15 | United Technologies Corporation | Blade outer air seal with centrally mounted seal arc segments |
US10422241B2 (en) | 2016-03-16 | 2019-09-24 | United Technologies Corporation | Blade outer air seal support for a gas turbine engine |
US10107129B2 (en) | 2016-03-16 | 2018-10-23 | United Technologies Corporation | Blade outer air seal with spring centering |
US11157676B2 (en) * | 2016-09-20 | 2021-10-26 | Octavo Systems Llc | Method for routing bond wires in system in a package (SiP) devices |
US10289793B1 (en) * | 2017-02-28 | 2019-05-14 | Cadence Design Systems, Inc. | System and method to generate schematics from layout-fabrics with a common cross-fabric model |
AT520046B1 (de) | 2017-06-12 | 2022-10-15 | Weber Hydraulik Gmbh | Hydraulikaggregat für hydraulische Rettungswerkzeuge sowie damit ausgestattetes Rettungswerkzeug |
US10643016B1 (en) * | 2017-12-19 | 2020-05-05 | Cadence Design Systems, Inc. | System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design |
US10592628B2 (en) * | 2018-01-17 | 2020-03-17 | Mentor Graphics Corporation | Parasitic extraction based on compact representation of process calibration data |
KR20190105337A (ko) * | 2018-03-05 | 2019-09-17 | 삼성전자주식회사 | 반도체 메모리 장치 |
CN108897915A (zh) * | 2018-10-08 | 2018-11-27 | 全球能源互联网研究院有限公司 | 一种igbt芯片矩阵模型自动生成方法及系统 |
CN115828822A (zh) * | 2022-01-15 | 2023-03-21 | 宁波德图科技有限公司 | 集成电路及封装结构寄生参数提取方法 |
CN115600539B (zh) * | 2022-11-10 | 2024-01-26 | 上海威固信息技术股份有限公司 | 一种芯片封装模块化设计方法及系统 |
CN117077596B (zh) * | 2023-09-15 | 2024-07-23 | 合芯科技有限公司 | 集成电路芯片的时序分析方法、装置、设备及介质 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7383058B2 (en) * | 2002-07-16 | 2008-06-03 | Intel Corporation | RF/microwave system with a system on a chip package or the like |
US8216887B2 (en) * | 2009-05-04 | 2012-07-10 | Advanced Micro Devices, Inc. | Semiconductor chip package with stiffener frame and configured lid |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5566083A (en) * | 1994-10-18 | 1996-10-15 | The Research Foundation Of State University Of New York | Method for analyzing voltage fluctuations in multilayered electronic packaging structures |
US6185722B1 (en) | 1997-03-20 | 2001-02-06 | International Business Machines Corporation | Three dimensional track-based parasitic extraction |
US6829754B1 (en) | 2002-06-04 | 2004-12-07 | Lsi Logic Corporation | Method and system for checking for power errors in ASIC designs |
US20040025136A1 (en) * | 2002-07-30 | 2004-02-05 | Carelli John A. | Method for designing a custom ASIC library |
US20040176939A1 (en) * | 2003-03-06 | 2004-09-09 | International Business Machines Corporation | Method, system, and product for determining loop inductance of an entire integrated circuit package |
US7131084B2 (en) | 2003-12-09 | 2006-10-31 | International Business Machines Corporation | Method, apparatus and computer program product for implementing automated detection excess aggressor shape capacitance coupling in printed circuit board layouts |
US7231618B2 (en) | 2004-04-22 | 2007-06-12 | Optimal Corporation | Fringe RLGC model for interconnect parasitic extraction |
JP2006031510A (ja) | 2004-07-20 | 2006-02-02 | Nec Electronics Corp | ジッタ解析方法、ジッタ解析装置及びジッタ解析プログラム |
EP1960921A1 (en) * | 2005-12-17 | 2008-08-27 | Gradient Design Automation, Inc. | Simulation of ic temperature distributions using an adaptive 3d grid |
JP2008009776A (ja) | 2006-06-29 | 2008-01-17 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法、設計装置、半導体集積回路システム、半導体集積回路実装基板、パッケージ、半導体集積回路 |
US7904864B2 (en) | 2006-10-07 | 2011-03-08 | Active-Semi, Inc. | Interconnect layer of a modularly designed analog integrated circuit |
US7590952B2 (en) * | 2006-11-28 | 2009-09-15 | International Business Machines Corporation | Compact chip package macromodels for chip-package simulation |
DE102007021561A1 (de) * | 2007-05-08 | 2009-01-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Entwurfswerkzeug für Art und Form einer Schaltungsrealisierung |
US7818698B2 (en) | 2007-06-29 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accurate parasitic capacitance extraction for ultra large scale integrated circuits |
US8826207B2 (en) | 2007-09-17 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of generating technology file for integrated circuit design tools |
TWI331488B (en) * | 2007-10-09 | 2010-10-01 | Unimicron Technology Corp | Printed circuit board and fabrication method thereof |
JP2010009179A (ja) | 2008-06-25 | 2010-01-14 | Elpida Memory Inc | 半導体装置もしくはプリント配線基板の設計方法および設計支援システム |
JP5429889B2 (ja) | 2008-10-27 | 2014-02-26 | 日本電気株式会社 | 半導体集積回路の動作解析方法、動作解析装置、動作解析プログラム及び動作解析システム |
US8312404B2 (en) | 2009-06-26 | 2012-11-13 | International Business Machines Corporation | Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages |
US8302067B2 (en) | 2009-10-19 | 2012-10-30 | National Chiao Tung University | Pin-out designation method for package-board codesign |
US8549447B2 (en) | 2010-04-24 | 2013-10-01 | Robert Eisenstadt | Integrated circuits with multiple I/O regions |
CN102314522B (zh) * | 2010-06-30 | 2013-03-06 | 中国科学院微电子研究所 | 一种模拟集成电路设计优化方法 |
CN101923595B (zh) * | 2010-08-25 | 2012-10-24 | 清华大学 | 模拟集成电路版图寄生器件提取系统及方法 |
-
2012
- 2012-07-30 US US13/561,760 patent/US8640077B1/en active Active
-
2013
- 2013-07-29 CN CN201310322960.5A patent/CN103577627B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7383058B2 (en) * | 2002-07-16 | 2008-06-03 | Intel Corporation | RF/microwave system with a system on a chip package or the like |
US8216887B2 (en) * | 2009-05-04 | 2012-07-10 | Advanced Micro Devices, Inc. | Semiconductor chip package with stiffener frame and configured lid |
Also Published As
Publication number | Publication date |
---|---|
US20140033149A1 (en) | 2014-01-30 |
CN103577627A (zh) | 2014-02-12 |
US8640077B1 (en) | 2014-01-28 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171030 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171030 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161228 Termination date: 20190729 |