CN103545184B - 金属栅极、其形成方法及cmos晶体管 - Google Patents
金属栅极、其形成方法及cmos晶体管 Download PDFInfo
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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Abstract
本发明公开了一种金属栅极、其形成方法及CMOS晶体管,采用氮气处理栅极金属层,形成一氮化物薄膜,从而使得金属铝和掩膜层间的粘附性大大增加,避免了peeling现象的发生,从而提高了器件的可靠性。
Description
技术领域
本发明涉及集成电路制造领域,特别涉及一种金属栅极、其形成方法及CMOS晶体管。
背景技术
随着现有工艺的不断进步,业内从开始避免使用金属栅极逐渐的过度到使用金属栅极。金属栅极的形成工艺通常为首先形成牺牲多晶硅栅极,作用在初始加工过程中,随后采用金属栅极代替,如此既保留了多晶硅栅极的优点,也具备了金属在电性能上的优势。
目前而言,在包括P型场效应管(PFET)和N型场效应管(NFET)的CMOS晶体管中,大多都采用金属栅极。图1所示为现有工艺的CMOS晶体管示意图。所述CMOS晶体管10包括NFET10a和PFET10b,NFET10a和PFET10b皆包括源漏极和栅极,其中,在采用上述替代的方法形成栅极金属层12后,继续形成一掩膜层13以覆盖,并在掩膜层13上形成一氧化层14,接着采用刻蚀工艺形成通孔以填充金属制作金属连线15。
然而,栅极金属层12与掩膜层13的粘附性较差,比如用铝做金属栅极时,尤其是在形成通孔后,就会产生剥离(peeling)16,这种缺陷通常是较为致命的,严重影响器件的可靠性。
发明内容
本发明的目的在于提供一种金属栅极、其形成方法及CMOS晶体,以解决现有工艺产生peeling的缺陷。
为解决上述技术问题,本发明提供一种金属栅极的形成方法,包括:
提供半导体结构,所述半导体结构包括栅极介电层及形成于所述栅极介电层上的牺牲多晶硅栅极;
将所述牺牲多晶硅栅极替换成栅极金属层;
对所述栅极金属层进行氮气处理,形成一氮化物薄膜。
可选的,对于所述的金属栅极的形成方法,所述栅极金属层的材料为铝。
可选的,对于所述的金属栅极的形成方法,在快速热处理腔内进行所述氮气处理。
可选的,对于所述的金属栅极的形成方法,所述氮化物薄膜的材料为氮化铝。
可选的,对于所述的金属栅极的形成方法,进行氮气处理的工艺条件为:氮气流量为2~100sccm,反应时间为2~50s,反应温度为300~500℃。
可选的,对于所述的金属栅极的形成方法,在化学气相沉积腔内进行所述氮气处理,所述氮气处理的工艺条件为:氮气流量为2~50sccm,反应时间为1~10s,反应功率为100~1000W。
本发明提供一种利用上述方法形成的金属栅极,包括:
栅极介电层,形成于所述栅极介电层上的栅极金属层;
形成于所述栅极金属层上的氮化物薄膜。
本发明还提供一种CMOS晶体管,包括:
NFET,所述NFET包括P阱,如上所述的金属栅极,所述金属栅极位于所述P阱上;
PFET,所述PFET包括N阱,如上所述的金属栅极,所述金属栅极位于所述N阱上。
可选的,对于所述的CMOS晶体管,还包括浅沟道隔离,所述N阱和P阱分列于所述浅沟道隔离两侧。
可选的,对于所述的CMOS晶体管,所述N阱和P阱内皆形成有源极和漏极。
可选的,对于所述的CMOS晶体管,还包括金属连线,所述金属连线与所述源极、漏极和金属栅极相连接。
可选的,对于所述的CMOS晶体管,所述金属连线外围形成有一保护层。
可选的,对于所述的CMOS晶体管,还包括位于N阱和P阱上的栅极侧墙,所述栅极侧墙紧靠所述栅极介电层、栅极金属层及氮化物薄膜。
可选的,对于所述的CMOS晶体管,所述相邻金属栅极的栅极侧墙之间为填充氧化层。
本发明提供的一种金属栅极、其形成方法及CMOS晶体中,采用氮气处理栅极金属层,形成一氮化物薄膜,从而使得金属铝和掩膜层间的粘附性大大增加,避免了peeling现象的发生,从而提高了器件的可靠性。
附图说明
图1为现有工艺的CMOS晶体管的结构示意图;
图2~7为本发明实施例的CMOS晶体管的形成过程中器件结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明提供的金属栅极、其形成方法及CMOS晶体管作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图2,本实施例提供一种具有金属栅极的场效应晶体管及其制造方法。
具体的,提供一半导体结构,所述半导体结构包括:衬底,所述衬底包括P阱20、N阱21及浅沟道隔离22,所述P阱20和N阱21分列于所述浅沟道隔离22两侧,所述P阱20和N阱21内皆形成有源漏极,所述源漏极可以具有硅锗等掺杂,所述N阱21的掺杂区可以为Σ状。形成于所述衬底上的栅极介电层23,所述栅极介电层23包括诸如二氧化硅(SiO2)的氧化物,或者氮化物等。所述衬底上还形成有位于所述栅极介电层23上的牺牲多晶硅栅极26及栅极侧墙24,所述栅极侧墙24紧靠所述栅极介电层23和牺牲多晶硅栅极26,相邻两个紧靠不同牺牲多晶硅栅极的栅极侧墙24可以相连,所述栅极侧墙24可以为氧化物或者氮化物结构,也可以ONO型结构,其形状可以为L型或者D型,图2所示的形状仅是示意,并未局限于L型。相邻两个紧靠不同牺牲多晶硅栅极的栅极侧墙24之间为填充氧化物25,可采取较为常见的材料。在此基础上完成本发明的金属栅极。相应的所述P阱20及其上结构形成为NFET,所述N阱21及其上结构形成为PFET。
请参考图3,去除牺牲多晶硅栅极,在栅极介电层23上形成栅极金属层30;所述栅极金属层30被栅极侧墙24包围,所述栅极侧墙24紧靠所述栅极介电层23和栅极金属层30,即采用金属替代原多晶硅的位置,其中栅极金属层30的材料可以铝,在栅极金属层30形成之后,优选的,采用CMP工艺研磨平整。
请参考图4,对所述栅极金属层30进行氮气(N2)处理,本实施例可在快速热处理腔(RTP chamber)内进行,具体的,应当满足如下工艺条件:氮气流量为2~100sccm,RTP腔内反应温度控制在300~500℃,并在RTP腔内反应2~50s,从而形成一致密氮化物薄膜,请参考图5,所述栅极金属层30上方形成一较薄的氮化物薄膜50,其为氮化铝,厚度可以为5~200埃,其能够与栅极金属层30有着良好的粘结,而不会在后续工艺中由于粘附性差而产生peeling。
通过上述工艺,形成了一金属栅极,所述金属栅极包括:
栅极介电层23及形成于所述栅极介电层23上的栅极金属层30;
形成于所述栅极金属层30上的氮化物薄膜50。
请参考图6,形成一掩膜层60,所述掩膜层60覆盖包括所述氮化物薄膜60、栅极侧墙24及填充氧化物25。所述掩膜层60可以在化学气相沉积腔内反应生成,其可以为氮化硅层。
在另一较佳实施例中,所述氮化物薄膜60也可不限于在RTP腔内形成,其可在形成掩膜层的60同一腔内生长,如化学气相沉积腔等,此时的工艺条件为:氮气流量为2~50sccm,反应时间为1~10s,反应功率为100~1000W。采用该方法能够简化生产中的传输过程,节省生产时间,也能避免由于传输可能引起的缺陷。
进一步的,在形成掩膜层60之后,还包括如下工艺步骤:形成一氧化层61,所述氧化层61覆盖所述掩膜层60;接着,请参考图7,刻蚀所述氧化层61、掩膜层60及氮化物薄膜(和/或填充氧化层25及栅极侧墙24)形成通孔,在通孔内填充金属形成金属连线,具体的,包括栅极金属连线71和源漏极金属连线72,金属连线可以为钨,铜等,为了隔绝金属与周围介质的物化反应,优选的,在金属连线周围形成一层保护层(未示出),所述保护层可以为氮化钛(TiN)等,其可以在刻蚀后所形成的通孔内先形成,之后再形成金属连线。
经上述方法可以得到一种CMOS晶体管,请参考图7,其具有以下结构:NFET70a,所述NFET70a包括P阱20,如上所述的金属栅极,所述金属栅极位于所述P阱20上;PFET70b,所述PFET70b包括N阱21,如上所述的金属栅极,所述金属栅极位于所述N阱21上。
如图7中所示,还包括:浅沟道隔离22,所述P阱20和N阱21分列于浅沟道隔离22两侧。栅极侧墙24,所述相邻金属栅极的相邻栅极侧墙24可以相连,相邻金属栅极的相邻栅极侧墙24之间为填充氧化层25。所述CMOS晶体管还包括金属连线,具体的,包括栅极金属连线71和源漏极金属连线72。
上述实施例提供的提供的金属栅极、其形成方法及CMOS晶体管中,采用氮气处理栅极金属层,形成一氮化物薄膜,从而使得金属铝和掩膜层间的粘附性大大增加,避免了peeling现象的发生,从而提高了器件的可靠性。
显然,本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包括这些改动和变型在内。
Claims (13)
1.一种金属栅极的形成方法,其特征在于,包括:
提供半导体结构,所述半导体结构包括栅极介电层及形成于所述栅极介电层上的牺牲多晶硅栅极;
将所述牺牲多晶硅栅极替换成栅极金属层,所述栅极金属层的材料为铝;
对所述栅极金属层进行氮气处理,形成一氮化物薄膜,提高栅极金属层与后续掩膜层的粘附性。
2.如权利要求1所述的金属栅极的形成方法,其特征在于,在快速热处理腔内进行所述氮气处理。
3.如权利要求2所述的金属栅极的形成方法,其特征在于,所述氮化物薄膜的材料为氮化铝。
4.如权利要求2所述的金属栅极的形成方法,其特征在于,进行氮气处理的工艺条件为:氮气流量为2~100sccm,反应时间为2~50s,反应温度为300~500℃。
5.如权利要求1所述的金属栅极的形成方法,其特征在于,在化学气相沉积腔内进行所述氮气处理,所述氮气处理的工艺条件为:氮气流量为2~50sccm,反应时间为1~10s,反应功率为100~1000W。
6.一种如权利要求1至5中的任一项所述的金属栅极的形成方法所形成的金属栅极,其特征在于,包括:
栅极介电层,形成于所述栅极介电层上的栅极金属层;
形成于所述栅极金属层上的氮化物薄膜,提高栅极金属层与后续掩膜层的粘附性。
7.一种CMOS晶体管,其特征在于,包括:
NFET,所述NFET包括P阱,如权利要求6所述的金属栅极,所述金属栅极位于所述P阱上;
PFET,所述PFET包括N阱,如权利要求6所述的金属栅极,所述金属栅极位于所述N阱上;
位于所述NFET和PFET的金属栅极上的所述掩膜层,所述掩膜层通过所述氮化物薄膜与所述金属栅极相连接。
8.如权利要求7所述的CMOS晶体管,其特征在于,还包括浅沟道隔离,所述N阱和P阱分列于所述浅沟道隔离两侧。
9.如权利要求8所述的CMOS晶体管,其特征在于,所述N阱和P阱内皆形成有源极和漏极。
10.如权利要求9所述的CMOS晶体管,其特征在于,还包括金属连线,所述金属连线与所述源极、漏极和金属栅极相连接。
11.如权利要求10所述的CMOS晶体管,其特征在于,所述金属连线外围形成有一保护层。
12.如权利要求7所述的CMOS晶体管,其特征在于,还包括位于N阱和P阱上的栅极侧墙,所述栅极侧墙紧靠所述栅极介电层、栅极金属层及氮化物薄膜。
13.如权利要求12所述的CMOS晶体管,其特征在于,相邻所述金属栅极的栅极侧墙之间为填充氧化层。
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